CN112103240B - A method for manufacturing a dielectric isolation structure based on SOI and a dielectric isolation structure - Google Patents
A method for manufacturing a dielectric isolation structure based on SOI and a dielectric isolation structure Download PDFInfo
- Publication number
- CN112103240B CN112103240B CN202011051681.6A CN202011051681A CN112103240B CN 112103240 B CN112103240 B CN 112103240B CN 202011051681 A CN202011051681 A CN 202011051681A CN 112103240 B CN112103240 B CN 112103240B
- Authority
- CN
- China
- Prior art keywords
- silicon
- dielectric isolation
- isolation structure
- soi
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002955 isolation Methods 0.000 title claims abstract description 53
- 238000000034 method Methods 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 42
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 41
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 41
- 239000010703 silicon Substances 0.000 claims abstract description 41
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 21
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 21
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 229920005591 polysilicon Polymers 0.000 claims abstract description 13
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 11
- 238000001039 wet etching Methods 0.000 claims abstract description 11
- 230000015556 catabolic process Effects 0.000 claims abstract description 10
- 230000003647 oxidation Effects 0.000 claims abstract description 9
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 9
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims abstract description 5
- 238000001312 dry etching Methods 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 37
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 8
- 239000012212 insulator Substances 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 239000011265 semifinished product Substances 0.000 claims description 3
- 239000002344 surface layer Substances 0.000 claims description 3
- 238000009413 insulation Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 10
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 9
- 230000003071 parasitic effect Effects 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 238000005498 polishing Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- YCIMNLLNPGFGHC-UHFFFAOYSA-N catechol Chemical compound OC1=CC=CC=C1O YCIMNLLNPGFGHC-UHFFFAOYSA-N 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000003014 reinforcing effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- -1 EPW Chemical compound 0.000 description 1
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 description 1
- 239000006061 abrasive grain Substances 0.000 description 1
- 230000003471 anti-radiation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- JJWKPURADFRFRB-UHFFFAOYSA-N carbonyl sulfide Chemical compound O=C=S JJWKPURADFRFRB-UHFFFAOYSA-N 0.000 description 1
- 238000012993 chemical processing Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76281—Lateral isolation by selective oxidation of silicon
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
公开了一种基于SOI的介质隔离结构制作方法及介质隔离结构，制作方法包括：在SDB硅片的顶层硅的上表面作氧化预处理得到二氧化硅层，再淀积氮化硅层；在所述氮化硅层上沉积光刻胶胶膜，并采用负胶接触式曝光；对所述氮化硅层进行干法刻蚀，对所述二氧化硅层进行湿法腐蚀，再进行深槽刻蚀；去胶；在刻蚀形成的槽内侧壁上氧化生长1.7‑1.8μm厚的二氧化硅，生长环境的气压大于十个标准大气压；低压力化学气相沉积多晶硅，且所述多晶硅填满所述刻蚀形成的槽；对所述多晶硅进行表面平坦化；去除氮化硅层，再进行场氧化。本发明制作工艺复杂度低，介电隔离结构的高低压两区之间的绝缘性能良好，击穿电压达到880V以上。
Disclosed is a method for manufacturing a dielectric isolation structure based on SOI and a dielectric isolation structure, the manufacturing method comprising: performing oxidation pretreatment on the upper surface of the top silicon of the SDB silicon wafer to obtain a silicon dioxide layer, and then depositing a silicon nitride layer; depositing a photoresist film on the silicon nitride layer, and using negative photoresist contact exposure; dry etching the silicon nitride layer, wet etching the silicon dioxide layer, and then deep trench etching; degumming; oxidation growth of 1.7-1.8μm thick silicon dioxide on the inner side wall of the groove formed by etching, the air pressure of the growth environment is greater than ten standard atmospheres; low-pressure chemical vapor deposition of polysilicon, and the polysilicon fills the groove formed by etching; surface flattening of the polysilicon; removing the silicon nitride layer, and then field oxidation. The manufacturing process of the present invention is low in complexity, the insulation performance between the high and low voltage areas of the dielectric isolation structure is good, and the breakdown voltage reaches more than 880V.
Description
Technical Field
The invention relates to the technical field of SOI (silicon on insulator), in particular to a manufacturing method of a dielectric isolation structure based on SOI and the dielectric isolation structure.
Background
The SOI (Silicon-On-Insulator) technology is used as an all-dielectric isolation technology, the defect of bulk Silicon materials is effectively overcome by the unique structure of the SOI (Silicon-On-Insulator) technology, the potential of the Silicon integrated circuit technology is fully exerted, and the SOI (Silicon-On-Insulator) technology is becoming the mainstream technology for manufacturing high-speed, low-power consumption, high-integration and high-reliability ultra-large-scale integrated circuits. The SOI technology adopts full dielectric isolation, thoroughly eliminates the parasitic latch-up effect of a CMOS (Complementary Metal Oxide Semiconductor ) device, reduces a single event upset interface, has excellent single event resistance and instantaneous irradiation resistance, enables the SOI chip to work in the worst cosmic ray environment, and is widely applied in space science. However, total dose ionization damage creates charge traps and interface states in the oxide layer that can cause inversion of the silicon substrate near the isolation oxide layer and form parasitic tube leakage under a certain source-drain bias.
In addition, the prior art has certain improvement on the structure or the material of the dielectric isolation region, and the opening of the parasitic channel is restrained. Either way, however, the process complexity is increased to some extent, which increases the manufacturing cost of the transistor device. However, for the SOI technology of a thick silicon film, the full-dielectric isolation technology between devices has great difficulty and high complexity, and the shallow trench isolation technology cannot meet the circuit requirement.
In the prior art, a manufacturing process of a dielectric isolation structure based on an SOI process of a thick silicon film is lacking.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a dielectric isolation structure manufacturing method based on SOI and a dielectric isolation structure, and the specific technical scheme is as follows:
On one hand, the invention discloses a manufacturing method of a dielectric isolation structure based on SOI, which enables the breakdown voltage of the dielectric isolation structure to be larger than 880V on SOI with the thickness of silicon film of 20 μm, and the method comprises the following steps:
S1, performing oxidation pretreatment on the upper surface of top silicon of an SDB silicon wafer to form a silicon dioxide layer with the thickness of 50-55nm, wherein the SDB silicon wafer is made of SOI (silicon on insulator) materials;
s2, depositing a silicon nitride layer with the thickness of 55-60nm on the silicon dioxide layer;
s3, depositing a photoresist film on the silicon nitride layer, and adopting negative photoresist contact exposure, wherein the thickness of the film is larger than 1 mu m;
s4, carrying out dry etching on the silicon nitride layer, carrying out wet etching on the silicon dioxide layer, and then carrying out deep groove etching to form grooves with the width of more than 5 mu m and less than 6.2 mu m;
s5, removing the residual photoresist;
s6, oxidizing and growing silicon dioxide on the inner side wall of the groove formed by etching in the step S4, wherein the air pressure of the growing environment is more than ten standard atmospheric pressures, and the growing thickness range of the silicon dioxide is 1.7-1.8 mu m;
S7, performing low-pressure chemical vapor deposition on the surface layer of the semi-finished product structure formed in the step S6, wherein the deposition thickness of the polysilicon is more than 3 mu m, and the polysilicon fills the grooves formed by etching;
s8, carrying out surface planarization on the polycrystalline silicon;
S9, removing the silicon nitride layer, and performing field oxidation to form a field oxide layer.
Further, the SDB silicon wafer comprises top silicon, an oxygen buried layer and a substrate from top to bottom, and the grooves obtained in the step S4 are engraved on the oxygen buried layer.
Further, before step S1, an SDB silicon wafer is manufactured, the thickness of the top silicon layer is 20 mu m, and the thickness of the oxygen-buried layer is 5-6 mu m.
Preferably, in step S8, a CMP process is used to planarize the surface of the polysilicon.
Preferably, the air pressure of the growth environment in step S6 is 10.8 standard atmospheres, and the growth thickness of the silicon dioxide is in the range of 1.76 μm.
Preferably, step S4 deep trench etching results in a trench having a width of 6.1 μm.
Optionally, the wet etching solution used in the wet etching process in step S4 includes any one of KOH, EPW, TMAH.
In another aspect, a dielectric isolation structure based on SOI is disclosed, which is fabricated using the fabrication method described above.
Further, the thickness of the top silicon on SOI is 20 μm, and the breakdown voltage of the dielectric isolation structure is greater than 880V.
The technical scheme of the invention has the beneficial effects that:
(a) The dielectric isolation structure is applied to a thick silicon film SOI process, and the breakdown voltage of the dielectric isolation structure reaches over 880V;
(b) The dielectric isolation structure has good insulating property between the high voltage region and the low voltage region, and the manufacturing process has low complexity.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a method for manufacturing an SOI-based dielectric isolation structure according to an embodiment of the present invention.
Detailed Description
For better understanding of the present invention, the objects, technical solutions and advantages thereof will be more clearly understood by those skilled in the art, and the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are merely some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, in the description and claims, are intended to cover a non-exclusive inclusion, such that a process, method, apparatus, article, or device that comprises a list of steps or elements is not necessarily limited to those steps or elements that are expressly listed or inherent to such process, method, article, or device.
In one embodiment of the present invention, a method for fabricating a dielectric isolation structure based on SOI is provided, such that a breakdown voltage of the dielectric isolation structure is greater than 880V achieved on SOI with a silicon film thickness of 20 μm, as shown in FIG. 1, the method comprises the steps of:
Firstly, manufacturing an SDB silicon wafer, wherein the SDB silicon wafer comprises top silicon, an oxygen burying layer and a substrate from top to bottom, the thickness of the top silicon is 20 mu m, and the thickness range of the oxygen burying layer is 5-6 mu m.
S1, performing oxidation pretreatment on the upper surface of top silicon of a Silicon Direct Bonding (SDB) silicon wafer to form a silicon dioxide layer of 50-55nm, wherein the SDB silicon wafer is made of SOI (silicon on insulator) materials;
s2, depositing a silicon nitride layer with the thickness of 55-60nm on the silicon dioxide layer;
s3, depositing a photoresist film on the silicon nitride layer, and adopting negative photoresist contact exposure, wherein the thickness of the film is larger than 1 mu m;
and S4, carrying out dry etching on the silicon nitride layer, carrying out wet etching on the silicon dioxide layer, and then carrying out deep groove etching to form grooves with the width of more than 5 mu m and less than 6.2 mu m (preferably 6.1 mu m), wherein the grooves are etched to the oxygen-buried layer.
Specifically, a wet etching process is adopted, and the expected depth of the dielectric isolation groove can be obtained by controlling the size and etching time of the etching window, so that the complete simultaneous completion of the full dielectric isolation and partial isolation structure of the thick silicon film SOI integrated circuit is realized, the integrated level of the integrated circuit is improved, the photoetching times are reduced, the process is simple and controllable, and the damage is small. The wet etching process adopts wet etching liquid comprising any one of KOH (potassium hydroxide), EPW (ethylenediamine and catechol) and TMAH (tetramethyl ammonium hydroxide).
S5, removing the residual photoresist;
S6, oxidizing and growing silicon dioxide on the inner side wall of the groove formed by etching in the step S4, wherein the air pressure of the growing environment is more than ten standard air pressures, and the growing thickness of the silicon dioxide is 1.7-1.8 mu m (preferably 1.76 mu m).
One of the key inventions of the present invention is that a high pressure environment of 10.8 atmospheres is preferably used to oxidize and grow silicon dioxide on the inner sidewalls of the etched trench, which plays a critical role in increasing the breakdown voltage of the dielectric isolation structure.
S7, performing Low Pressure Chemical Vapor Deposition (LPCVD) on the surface layer of the semi-finished product structure formed in the step S6, wherein the deposition thickness of the polysilicon is more than 3 mu m, and the polysilicon fills the grooves formed by etching;
the full-dielectric isolation groove is filled with polysilicon, so that long-time high-temperature annealing of the traditional isolation process is avoided, the influence on the diffusion of the total-dose reinforcing impurities is reduced, the total-dose irradiation resistance of the device is improved, the isolation process has small influence on other process procedures, and the isolation process can be completed before well injection of the device or before gate oxide.
S8, carrying out surface planarization on the polycrystalline silicon.
The polysilicon is preferably surface planarized using a chemical mechanical Polishing (CHEMICAL MECHANICAL CMP) process. CMP is a process of pressing a workpiece to be polished against a rotating elastic polishing pad, supplying a corrosive processing liquid to the workpiece, and simultaneously supplying a polishing material of ultra-fine abrasive grains (diameter 100nm or less) to selectively polish protrusions of the workpiece when the workpiece is subjected to corrosion processing (chemical processing). CMP is introduced into surface shaping of a dielectric isolation structure to reduce the field oxide sharp angle height and improve the breakdown voltage of the dielectric isolation.
S9, removing the silicon nitride layer, and performing field oxidation to form a field oxide layer.
In another aspect, a dielectric isolation structure based on SOI is disclosed, which is fabricated using the fabrication method described above.
Further, the thickness of the top silicon on SOI is 20 μm, and the breakdown voltage of the dielectric isolation structure is greater than 880V.
The dielectric isolation method is applied to the thick silicon film SOI process, and alkaline wet corrosion is adopted, so that dielectric isolation grooves with different depths can be simultaneously realized, the full dielectric isolation between devices is realized, the integration level of a circuit is improved, the photoetching times are reduced, the process manufacturing cost is reduced, and meanwhile, the process is simple and has small difficulty. The isolation process adopted by the invention can avoid long-time high-temperature annealing of the isolation structure, can reduce the influence on the diffusion of the total dose reinforcing impurities in the application of the anti-radiation circuit, improves the total dose irradiation resistance of the device, and simultaneously eliminates the parasitic latch-up effect of the CMOS device through all-medium isolation.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (6)
1. A method for fabricating a dielectric isolation structure based on SOI, wherein a breakdown voltage of the dielectric isolation structure is made to be greater than 880V on SOI having a silicon film thickness of 20 μm, the method comprising the steps of:
the method comprises the steps of pre-manufacturing an SDB silicon wafer, wherein the SDB silicon wafer comprises top silicon, an oxygen burying layer and a substrate from top to bottom, the thickness of the top silicon is 20 mu m, and the thickness range of the oxygen burying layer is 5-6 mu m;
S1, performing oxidation pretreatment on the upper surface of top silicon of an SDB silicon wafer to form a silicon dioxide layer with the thickness of 50-55nm, wherein the SDB silicon wafer is made of SOI (silicon on insulator) materials;
s2, depositing a silicon nitride layer with the thickness of 55-60nm on the silicon dioxide layer;
s3, depositing a photoresist film on the silicon nitride layer, and adopting negative photoresist contact exposure, wherein the thickness of the film is larger than 1 mu m;
s4, carrying out dry etching on the silicon nitride layer, carrying out wet etching on the silicon dioxide layer, and then carrying out deep groove etching to form grooves with the width of more than 5 mu m and less than 6.2 mu m, wherein the grooves are etched to the oxygen-buried layer;
s5, removing the residual photoresist;
S6, oxidizing and growing silicon dioxide on the inner side wall of the groove formed by etching in the step S4, wherein the air pressure of a growing environment adopts 10.8 standard atmospheric pressures, and the growing thickness range of the silicon dioxide is 1.7-1.8 mu m;
S7, performing low-pressure chemical vapor deposition on the surface layer of the semi-finished product structure formed in the step S6, wherein the deposition thickness of the polysilicon is more than 3 mu m, and the polysilicon fills the grooves formed by etching;
S8, carrying out surface planarization on the polysilicon by adopting a CMP process;
S9, removing the silicon nitride layer, and performing field oxidation to form a field oxide layer.
2. The method of fabricating a dielectric isolation structure according to claim 1, wherein the silicon dioxide grown in step S6 has a thickness in the range of 1.76 μm.
3. The method of fabricating a dielectric isolation structure based on SOI as claimed in claim 1, wherein step S4 deep trench etching results in a trench having a width of 6.1. Mu.m.
4. The method of claim 1, wherein the wet etching solution used in the wet etching process in step S4 includes any one of KOH, EPW, TMAH.
5. An SOI-based dielectric isolation structure produced by the method of any one of claims 1-4.
6. The SOI-based dielectric isolation structure of claim 5 wherein the top layer silicon on the SOI has a thickness of 20 μm and the dielectric isolation structure has a breakdown voltage greater than 880V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011051681.6A CN112103240B (en) | 2020-09-29 | 2020-09-29 | A method for manufacturing a dielectric isolation structure based on SOI and a dielectric isolation structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011051681.6A CN112103240B (en) | 2020-09-29 | 2020-09-29 | A method for manufacturing a dielectric isolation structure based on SOI and a dielectric isolation structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112103240A CN112103240A (en) | 2020-12-18 |
| CN112103240B true CN112103240B (en) | 2025-01-21 |
Family
ID=73782964
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011051681.6A Active CN112103240B (en) | 2020-09-29 | 2020-09-29 | A method for manufacturing a dielectric isolation structure based on SOI and a dielectric isolation structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112103240B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5480832A (en) * | 1991-10-14 | 1996-01-02 | Nippondenso Co., Ltd. | Method for fabrication of semiconductor device |
| US5872045A (en) * | 1997-07-14 | 1999-02-16 | Industrial Technology Research Institute | Method for making an improved global planarization surface by using a gradient-doped polysilicon trench--fill in shallow trench isolation |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2372631B (en) * | 2001-02-22 | 2005-08-03 | Mitel Semiconductor Ltd | Semiconductor-on-insulator structure |
| DE102005010944B4 (en) * | 2005-03-10 | 2009-09-10 | X-Fab Semiconductor Foundries Ag | Method for producing carrier disk contact in integrated circuits with high-voltage components based on SOI technology and integrated circuits with corresponding trench structures |
| EP1863081A3 (en) * | 2006-03-10 | 2008-03-05 | Hitachi, Ltd. | Dielectric material separated-type, high breakdown voltage semiconductor circuit device, and production method thereof |
| CN105990212A (en) * | 2015-01-29 | 2016-10-05 | 无锡华润上华半导体有限公司 | Preparation method of groove isolation structure |
| CN110379765B (en) * | 2019-08-27 | 2022-01-14 | 上海华虹宏力半导体制造有限公司 | Deep groove isolation process method |
-
2020
- 2020-09-29 CN CN202011051681.6A patent/CN112103240B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5480832A (en) * | 1991-10-14 | 1996-01-02 | Nippondenso Co., Ltd. | Method for fabrication of semiconductor device |
| US5872045A (en) * | 1997-07-14 | 1999-02-16 | Industrial Technology Research Institute | Method for making an improved global planarization surface by using a gradient-doped polysilicon trench--fill in shallow trench isolation |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112103240A (en) | 2020-12-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104795331B (en) | The forming method of transistor | |
| KR20040096365A (en) | Manufacturing method for semiconductor device | |
| US5318663A (en) | Method for thinning SOI films having improved thickness uniformity | |
| WO2011160477A1 (en) | Strained-channel field-effect transistor and manufacturing method thereof | |
| US20180315857A1 (en) | Device and method to improve fin top corner rounding for finfet | |
| WO2021218219A1 (en) | Manufacturing method for trench of bcd device, and bcd device | |
| CN103377912B (en) | Shallow trench isolation chemical mechanical planarization method | |
| US20130026573A1 (en) | Body contact soi transistor structure and method of making | |
| CN108878288A (en) | The manufacturing method of interlayer film | |
| US6645795B2 (en) | Polysilicon doped transistor using silicon-on-insulator and double silicon-on-insulator | |
| CN112103240B (en) | A method for manufacturing a dielectric isolation structure based on SOI and a dielectric isolation structure | |
| CN109545676A (en) | Grating of semiconductor element high planarization method | |
| CN111834286B (en) | Semiconductor insulating substrate, transistor and preparation method thereof | |
| JP2005129654A (en) | Manufacturing method of semiconductor device | |
| CN113889432A (en) | Method for manufacturing semiconductor-on-insulator structure | |
| JPS6039835A (en) | Flattening of surface of substrate | |
| WO2023155263A1 (en) | Shallow trench isolation structure, preparation method therefor, and semiconductor structure | |
| CN112909079B (en) | Semiconductor device and method of forming same | |
| CN108063112B (en) | Method for manufacturing localized SOI region | |
| CN115188704B (en) | Semiconductor-on-insulator substrate and method for manufacturing the same | |
| JPH10125880A (en) | Method of forming laminated soi substrate | |
| CN110164815A (en) | The method for forming isolation structure and semiconductor devices | |
| KR20000023238A (en) | Process for the production of semiconductor device | |
| CN111508891B (en) | Method for manufacturing SOI wafer | |
| CN102820251A (en) | Method for preparing SOI (silicon on insulator) material with high-K dielectric buried layer on basis of bonding technology |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20250114 Address after: Unit 1, 16th Floor, Building 1, No. 3 Changtong Road, Chaoyang District, Beijing, with a budget of 100000 RMB Patentee after: BEIJING SHITEMEI MEASUREMENT AND CONTROL TECHNOLOGY CO.,LTD. Country or region after: China Address before: Room 249a, building a, emerging industry development center, Zhangjiagang Free Trade Zone, Suzhou, Jiangsu 215000 Patentee before: Shitemei (Suzhou) measurement and Control Technology Co.,Ltd. Country or region before: China |