CN112086534B - Laminated battery and method of making the same - Google Patents

Abstract

The invention discloses a laminated cell and a manufacturing method thereof, relates to the technical field of solar energy, and aims to solve the problem that a perovskite laminated cell cannot be prepared on a textured surface of a bottom cell and improve the efficiency of the laminated cell. The laminate battery includes: the solar cell comprises a bottom battery, a hole transport layer deposited above the suede in vacuum and a perovskite absorption layer formed on the hole transport layer. The bottom cell has a textured surface. The manufacturing method of the laminated battery comprises the laminated battery provided by the technical scheme. The laminated battery and the manufacturing method thereof provided by the invention are used for manufacturing the laminated battery.

Description

Laminated battery and method of making the same

technical field

The present invention relates to the technical field of solar cells, in particular to a laminated cell and a manufacturing method thereof.

Background technique

The crystalline silicon-perovskite tandem battery is a tandem battery composed of a crystalline silicon battery and a perovskite battery. This tandem cell uses a crystalline silicon cell as the bottom cell to absorb the solar energy of 700nm-1200nm, and a perovskite cell as the top cell to absorb the solar energy of 300nm-800nm, and the crystalline silicon cell and perovskite The ore cells are connected through a composite layer, connecting the crystalline silicon cells and the perovskite cells in series.

When making a crystalline silicon-perovskite tandem battery, a solution spin coating method can be used to form a perovskite battery on the polished surface of the crystalline silicon battery to obtain a crystalline silicon-perovskite tandem battery. However, since the surface of the crystalline silicon cell needs to be polished, it not only increases the fabrication cost of the crystalline silicon-perovskite tandem cell, but also inhibits the light absorption rate and light utilization rate of the crystalline silicon-perovskite tandem cell. It is difficult to reflect the advantage of the efficiency gain of tandem cells.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a laminated battery and a manufacturing method thereof, which are used to improve the conversion efficiency of the laminated battery and reduce the manufacturing cost on the basis of retaining the textured structure of the bottom battery.

In a first aspect, the present invention provides a stacked battery. The tandem cell includes a bottom cell having a textured surface, a hole transport layer vacuum deposited over the textured surface, and a perovskite absorber layer formed on the hole transport layer. The perovskite absorber layer is a perovskite absorber layer containing lead ions. The hole transport layer is formed by co-depositing a metal sulfide hole transport material and an inorganic lead compound. Among them, the band gap of the metal sulfide is not less than 1.6 eV. The inorganic lead compound is one or more of lead chloride, lead bromide, lead iodide, lead oxide, lead thiocyanate, and lead acetate.

In the laminated battery provided by the present invention, the hole transport layer is formed by vacuum co-deposition of a metal sulfide hole transport material and an inorganic lead compound. Metal sulfides and inorganic lead compounds in the gas phase are uniformly deposited on the textured surface of the bottom cell without using an organic solvent. At this time, it is ensured that the suede surface of the bottom cell has a good light trapping effect, which can increase the light utilization rate of the stacked cell.

On this basis, in the laminated battery provided by the present invention, the perovskite absorbing layer is a perovskite absorbing layer with lead ions. Since both the perovskite absorbing layer and the hole transport layer contain lead ions, the holes in the When the perovskite absorption layer is formed on the transport layer, the hole transport layer can be used as the induction layer to induce the crystalline growth of the perovskite absorption layer material, so as to form a perovskite absorption layer with a high degree of order and good crystallinity, and then Improve photoelectric conversion efficiency. At the same time, the soft alkali ions contained in the semiconductor material of the hole transport layer can coordinate with the soft acid ions of the perovskite absorber layer material, so that the interface defects of the perovskite absorber layer can be passivated and reduced. The carrier recombination of the tandem cell improves the photoelectric conversion efficiency. In addition, due to the soft-acid-soft-base coordination force between the soft-base ions and the soft-acid ions in the perovskite absorber layer, the contact interface between the hole transport layer and the perovskite absorber layer has high compatibility, thereby The hole extraction performance of the hole transport layer can be improved.

The laminated battery provided by the present invention induces the formation of a uniform perovskite absorbing layer on the hole transport layer, so that the formed perovskite absorbing layer can be uniformly formed on the suede surface of the bottom battery, so as to realize the formation of the suede surface of the bottom battery. A uniform and dense perovskite absorption layer is formed on the top, which retains the textured structure of the bottom cell, improves the solar light absorption rate and utilization rate of the tandem cell, and further improves the conversion efficiency of the tandem cell.

In a possible implementation manner, the material ratio of the metal sulfide and the inorganic lead compound is 1:(0.01-0.5), for example, it can be 1:0.01, 1:0.25, 1:0.45, 1:0.5, etc. . In the hybrid hole transport layer, metal sulfides account for more than 50% of the hole transport functional host material, and inorganic lead compounds are used as inducing materials for the growth of the anchor layer on the hole transport layer, and their content ranges from 1% to 50%. %between.

In a possible implementation manner, the above-mentioned metal sulfides include manganese sulfide, zinc sulfide, nickel sulfide, titanium disulfide, molybdenum disulfide, magnesium sulfide, copper sulfide, digallium trisulfide, gallium monosulfide, germanium sulfide, One or more of germanium sulfide, arsenic trisulfide, tin disulfide, tungsten disulfide and lead sulfide. These semiconductor materials have large band gaps, basically do not absorb incident light in the absorption band of the battery, and can be fabricated by vacuum thermal evaporation. The fabrication method is simple and the price is low.

In a possible implementation, the general chemical formula of the perovskite absorbing layer is ABX ₃ ; wherein, A is one or more of alkylamine cations, methyldiamine cations, and cesium cations, and B is all One or more of the alkali metal cations, Pb ²⁺ and Sn ²⁺ , X is one or more of I ^- , Cl ^- and Br ^- .

In a possible implementation manner, the thickness of the above-mentioned perovskite absorption layer is 100 nm-1000 nm.

In a possible implementation manner, the thickness of the above hole transport layer is 5 nm-100 nm.

In a possible implementation manner, the stacked battery further includes a tunneling composite layer formed above the textured surface, and the hole transport layer is formed on the tunneling composite layer.

In a second aspect, the present invention also provides a method for manufacturing a laminated battery. The manufacturing method of the laminated battery includes:

A bottom battery is provided, the bottom battery having a suede finish.

A hole transport layer is formed by co-depositing a metal sulfide hole transport material and an inorganic lead compound on the textured surface by a vacuum co-deposition process. The band gap of metal sulfides is not less than 1.6 eV. The inorganic lead compound is one or more of lead chloride, lead bromide, lead iodide, lead oxide, lead thiocyanate, and lead acetate.

An anchor layer is formed by vacuum deposition on the hole transport layer, the anchor layer contains a metal halide, and the metal halide at least includes lead halide.

A solution method is used to coat the cationic salt on the anchoring layer, and the metal halide contained in the anchoring layer reacts with the cationic salt to form a perovskite absorption layer.

An electron transport layer is fabricated on the perovskite absorber layer, and an upper electrode is fabricated on the electron transport layer.

Since metal sulfides are easily deposited on various types of bottom cells, the bottom cells can be N-type polycrystalline silicon cells, single crystal silicon cells, and the like. The fabrication method of the stacked battery can also be applied to copper indium gallium selenide-perovskite stacked battery, perovskite-perovskite stacked battery, gallium arsenide-perovskite stacked battery, organic photovoltaic-perovskite stacked battery In the production of tandem batteries such as mine tandem batteries.

In a possible implementation manner, the above-mentioned metal halide further includes one or both of tin halide and alkali metal halide.

In a possible implementation manner, the above-mentioned co-depositing metal sulfide hole transport material and inorganic lead compound on the textured surface using a vacuum co-deposition process to form a hole transport layer includes: using a vacuum thermal evaporation process on the textured surface. A hole transport layer is obtained by co-depositing a metal sulfide and a lead compound. The vacuum thermal evaporation rates of metal sulfides and inorganic lead compounds are

卤化铅和卤化锡的真空蒸镀速率为

由于金属卤化物和卤化铅、卤化锡的物性有一定的差异，所以在真空蒸镀成膜的过程中需要控制碱金属卤化物的真空蒸镀速率在上述范围内。In a possible implementation manner, forming the anchor layer above the hole transport layer includes: co-depositing a metal halide on the hole transport layer by vacuum evaporation to obtain an anchor layer; The vacuum evaporation rate is

The vacuum evaporation rate of lead halide and tin halide is

Since the physical properties of metal halides, lead halides and tin halides are different to a certain extent, it is necessary to control the vacuum evaporation rate of alkali metal halides within the above range during the process of vacuum evaporation and film formation.

In a possible implementation manner, the above-mentioned applying a solution method to the cationic salt on the anchor layer includes: applying a solution method to a cationic salt solution on the anchoring layer, so that the metal halide contained in the anchoring layer reacts with the cationic salt A perovskite absorber layer is formed.

In a possible implementation manner, after the above-mentioned solution method is used to form the cation salt on the anchor layer, and before the electron transport layer is formed on the perovskite absorber layer, the method for fabricating the stacked battery further includes: adjusting the perovskite absorber layer. Perform annealing treatment. The temperature of the annealing treatment is 50°C-200°C, and the time of the annealing treatment is 5 minutes-60 minutes. Through the annealing treatment, a denser, more regular and more uniform perovskite absorber layer will be formed, which can improve the efficiency of the tandem cell.

In a possible implementation manner, before fabricating the electron transport layer on the perovskite absorber layer, the method for fabricating the tandem battery further includes: forming an electron transport interface layer on the perovskite absorber layer for transporting current carriers son. The electron transport interface layer includes the LiF layer and the _C60 layer. The LiF layer is formed on the perovskite absorber layer and the _C60 layer is formed on the LiF layer. Among them, the thickness of the LiF layer is 0.1 nm-10 nm, and the thickness of the C ₆₀ layer is 1 nm-20 nm.

In a possible implementation manner, before the above-mentioned conformal formation of the hole transport layer on the textured surface, the manufacturing method of the stacked battery further includes: forming a tunneling composite layer on the textured surface.

The beneficial effects of the method for fabricating the laminated battery provided in the second aspect are the same as those of the laminated battery provided in the first aspect, and details are not described herein again.

Description of drawings

The accompanying drawings described herein are used to provide further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the attached image:

1 is a schematic structural diagram of a crystalline silicon-perovskite tandem battery in the prior art;

FIG. 2 is a schematic structural diagram of a laminated battery in an embodiment of the present invention;

3A to 3H are schematic diagrams of states of various stages of a method for fabricating a laminated battery provided by an embodiment of the present invention;

4 is a SEM image of the textured cross-section of the laminated battery produced in Example 1 of the present invention;

5 is a SEM image of the textured surface of the laminated battery prepared in Example 1 of the present invention;

FIG. 6 is the I-V curves of the stacked batteries prepared in Example 1, Comparative Example 1 and Comparative Example 2 of the present invention.

Detailed ways

In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

In addition, the terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature defined as "first" or "second" may expressly or implicitly include one or more of that feature. In the description of the present invention, "plurality" means two or more, unless otherwise expressly and specifically defined. "Several" means one or more than one, unless expressly specifically defined otherwise.

In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", etc. are based on those shown in the accompanying drawings The orientation or positional relationship is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

In the description of the present invention, it should be noted that the terms "installed", "connected" and "connected" should be understood in a broad sense, unless otherwise expressly specified and limited, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; may be mechanical connection or electrical connection; may be direct connection or indirect connection through an intermediate medium, may be internal communication between two elements or an interaction relationship between the two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

Organic-inorganic hybrid perovskite solar cells have attracted worldwide attention as new high-efficiency and low-cost solar cells. In just a few years, the photoelectric conversion efficiency of perovskite cells has rapidly climbed from 3.8% in 2009 to more than 25%, which is close to the efficiency of commercial silicon-based solar cells. As a multi-component battery, the absorption spectral band gap of perovskite battery can be regulated in the range of 1.5eV-1.8eV through the component formulation. Crystalline silicon cell is a high-efficiency crystalline silicon photovoltaic cell technology, and its cell efficiency (26.7%) is close to its theoretical limit efficiency (29.4%), and tandem cell technology is an effective way to break through the efficiency of traditional crystalline silicon photovoltaic cells. Perovskites are ideal tandem top cell materials. Figure 1 shows a schematic structural diagram of a crystalline silicon-perovskite tandem battery in the prior art. As shown in Figure 1, the crystalline silicon-perovskite tandem battery sequentially includes silver electrodes 1-1 and transparent backs from bottom to top. Conductive film 1-2, P-type amorphous silicon layer 1-3, intrinsic amorphous silicon layer 1-4, bottom cell light absorption layer 1-5, N-type amorphous silicon layer 1-6, N-type heavily doped Tunneling junction layer 1-7, P-type heavily doped tunneling junction layer 1-8, hole transport layer 1-9, perovskite absorption layer 1-10, electron transport interface layer 1-11, SnO ₂ electron transport Layers 1-12, transparent front electrodes 1-13, silver electrode gridlines 1-14. The crystalline silicon-perovskite tandem cell uses the crystalline silicon cell as the bottom cell to absorb the solar energy of 700nm-1200nm, uses the perovskite cell as the top cell to absorb the sunlight energy of 300nm-800nm, and is connected by a composite layer in the middle to form two Connect the battery in series. The overall open circuit voltage of the tandem cell is the superposition of the voltages of the top cell and the bottom cell, while the current of the tandem cell requires good current matching between the upper and lower cells. Crystalline silicon-perovskite tandem cells are expected to achieve photoelectric conversion efficiencies above 30%.

At present, several literatures have reported that the conversion efficiency of crystalline silicon-perovskite tandem cells can reach more than 25%. In a typical perovskite cell, each functional layer in the device is fabricated by a solution spin-coating method. High-efficiency crystalline silicon cells generally use a double-sided suede light trapping structure to improve the absorption and utilization of sunlight, thereby improving cell conversion efficiency. The micron-scale pyramid-shaped textured light-trapping structure in crystalline silicon cells is a great challenge for solution-based fabrication of perovskite top cells. The difficulty is that the thickness of each functional layer of the perovskite battery is generally several hundred nanometers, and it is difficult to uniformly deposit on the micron-scale pyramid-shaped textured surface by the solution spin coating method. The current solution is to polish the crystalline silicon bottom cell to reduce the roughness of the textured surface to make solution-based perovskite top cells possible. Although this method can process perovskite top cells and tandem cells on the textured surface, it sacrifices the cell efficiency gain brought by the textured structure and its light trapping effect. At the same time, the polishing process greatly increases the production cost of the entire battery, and it is difficult to reflect the advantage of the efficiency gain of the stacked battery. Retaining the suede structure of the bottom cell and fabricating perovskite cells directly on the suede surface of the bottom cell is the key to achieving high efficiency of the tandem cell. However, the key to making a perovskite battery directly on the suede surface of the bottom battery is how to uniformly deposit the functional layers of the perovskite top battery on the suede surface. The functional layers of the perovskite top battery here include a hole transport layer and a perovskite layer. , electron transport layer, hole blocking layer, electrode buffer layer, electrode, etc. Compared with solution processing methods, the vacuum evaporation deposition process can uniformly deposit various vapor-depositable functional materials on various substrates, which is an effective solution to overcome the difficulty of fabricating perovskite top cells on the textured surface of bottom cells. Vacuum evaporation electron transport layer, hole blocking layer, electrode buffer layer and sputtering electrode all have mature functional materials and deposition processes. The conformal deposition of hole transport layer and perovskite layer by vacuum evaporation on the textured surface of the bottom cell is the difficulty and key to the fabrication of high-efficiency crystalline silicon-perovskite tandem cells.

In order to solve the above technical problems, embodiments of the present invention provide a stacked battery. The stacked battery is not only suitable for the stacked battery with crystalline silicon battery as the bottom battery, but also suitable for any one of polycrystalline silicon battery, copper indium gallium selenide battery, perovskite battery, gallium arsenide battery, organic photovoltaic battery A tandem battery that is a bottom battery, and is not limited to this.

FIG. 2 shows a schematic structural diagram of a laminated battery provided by an embodiment of the present invention. As shown in FIG. 2 , the stacked battery provided by the embodiment of the present invention includes: a bottom battery 1 , a hole transport layer 2 and a perovskite absorption layer 3 .

As shown in FIG. 2 , the bottom battery 1 described above has a textured surface. The bottom cell 1 may be any one of the bottom cells 1 described above, and is not limited thereto. The suede surface may be a suede surface with a pyramid shape, or a suede surface with an inverted pyramid shape, or the like.

As shown in FIG. 2 , the hole transport layer 2 is formed above the textured surface, and the hole transport layer 2 is formed by vacuum co-depositing metal sulfide hole transport materials and inorganic lead compounds, which can be formed by vacuum co-depositing. way deposited over the suede.

As shown in FIG. 2 , if the stacked cell further includes a tunneling composite layer 4 , the tunneling composite layer 4 is formed on the bottom cell 1 . The tunneling composite layer 4 may be a tunneling junction composite layer 4 made of heavily doped silicon opposite to the pn junction of the bottom cell 1 . For example, the tunnel junction composite layer 4 is mainly composed of an n-type doped microcrystalline silicon layer and a p-type doped microcrystalline silicon layer. Specifically, the n-type doped microcrystalline silicon layer can be a microcrystalline silicon layer doped with Group VA atoms such as phosphorus, arsenic, antimony, and bismuth, and the p-type doped microcrystalline silicon layer can be doped with boron, aluminum , gallium, indium, thallium and other group IIIA atoms of microcrystalline silicon layer.

Of course, the tunneling composite layer 4 can also be a tunneling composite layer 4 made of other materials, for example, tin-doped indium oxide (ITO), zinc-doped indium oxide (IZO), tungsten-doped indium oxide (IWO), titanium-doped oxide A composite layer made of transparent metal oxides such as indium (ITIO), fluorine-doped tin oxide (FTO), and aluminum-doped zinc oxide (AZO).

As shown in FIG. 2 , the above-mentioned hole transport layer 2 is formed on the tunneling composite layer 4 , and the hole transport layer 2 is formed by vacuum co-deposition of a metal sulfide and an inorganic lead compound. The substance ratio of the metal sulfide and the inorganic lead compound is 1:(0.01-0.5), for example, 1:0.01, 1:0.25, 1:0.45, 1:0.5, and the like. In the hole transport layer 2 formed by the above ratio, the proportion of metal sulfide is large, so that the hole transport performance of the hole transport layer 2 is not affected. At the same time, adding lead ions in the hole transport layer 2 makes the contact interface between the hole transport layer 2 and the perovskite absorption layer 2 have high compatibility, and the hole transport layer 2 can induce the perovskite absorption layer 2 The crystal of the material grows to form a perovskite absorption layer 2 with a high degree of order and good crystallinity, thereby improving the photoelectric conversion efficiency.

As shown in Figure 2, the above-mentioned inorganic lead compound is one or more of lead chloride, lead bromide, lead iodide, lead oxide, lead thiocyanate, and lead acetate. The thickness of the hole transport layer 2 can be set according to the actual situation, for example, the thickness of the hole transport layer 2 is 5 nm-100 nm. The hole transport layer 2 is formed on the tunneling composite layer 4 . The bottom cell 1 and the perovskite top cell are connected through the tunneling composite layer 4 to form a tandem cell at both ends. The formation method here may be conformal formation.

As shown in Figure 2, the metal sulfide and the inorganic lead compound can be uniformly deposited on the suede surface of the bottom cell 1 by the vacuum co-deposition process, so that the light trapping effect of the suede surface of the bottom cell 1 can be retained, and the pair of bottom cell 1 can be guaranteed. Good absorption of incident light. At the same time, since the hole transport layer 2 obtained by the above process has good compatibility and adaptability with the fabrication of other functional layers, the bottom cell 1 in the stacked cell of the embodiment of the present invention can be based on actual needs to make a selection. Since the metal sulfide and the inorganic lead compound are relatively cheap, using the metal sulfide and the inorganic lead compound as the material for the hole transport layer can reduce the cost of the stacked battery and make its application range wider.

As shown in FIG. 2 , the above-mentioned perovskite absorption layer 3 is formed on the hole transport layer 2 , and the perovskite absorption layer 3 is a perovskite absorption layer 3 having lead ions. The thickness of the perovskite absorption layer 3 can be set according to the actual situation, for example, the thickness of the perovskite absorption layer 3 is 100 nm-1000 nm.

On the one hand, as shown in FIG. 2 , according to the principle of easy and stable combination of soft acid and soft base in the theory of soft and hard acid-base, the sulfide ions contained in the hole transport layer 2 are soft alkali ions, which together with the perovskite absorption layer 3 contain There is a strong interaction force between the soft acid ions (lead ions). Since both the perovskite absorption layer 3 and the hole transport layer 2 contain lead ions, when the perovskite absorption layer 3 is formed on the hole transport layer 2, the hole transport layer 2 can be used as the inducing layer to induce the perovskite Crystal growth of the material of the mineral absorption layer 3 to form the perovskite absorption layer 3 with higher order and good crystallinity, thereby improving the photoelectric conversion efficiency. At the same time, the soft alkali ions contained in the semiconductor material of the hole transport layer 2 can coordinate with the soft acid ions of the material of the perovskite absorption layer 3, so that the interface of the perovskite absorption layer 3 can be passivated Defects, reduce the carrier recombination of the tandem cell, and improve the photoelectric conversion efficiency. In addition, due to the soft-acid-soft-base coordination force between the soft-base ions and the soft-acid ions in the perovskite absorption layer 3, the contact interface between the hole transport layer 2 and the perovskite absorption layer 3 has a higher Therefore, the hole extraction performance of the hole transport layer 2 can be improved.

On the other hand, as shown in FIG. 2 , the laminated battery provided by the present invention induces the formation of a uniform perovskite absorption layer 3 on the hole transport layer 2 , so that the formed perovskite absorption layer 3 can be uniformly formed on the hole transport layer 2 . The suede surface of the bottom cell 1, so as to form a uniform and dense perovskite absorption layer 3 on the suede surface of the bottom cell 1, retain the suede structure of the bottom cell 1, and improve the solar light absorption rate and utilization rate of the stacked cell , thereby improving the conversion efficiency of tandem cells.

In some embodiments, as shown in FIG. 2 , the general chemical formula of the perovskite absorption layer 3 is ABX ₃ ; wherein, A is one or more of alkylamine cations, methyldiamine cations, and cesium cations , B is one or more of the alkali metal cations, Pb ²⁺ , Sn ²⁺ , and X is one or more of I ⁻ , Cl ⁻ , and Br ⁻ . Wherein, the alkylamine cation includes one or a combination of two of CH ₃ NH ₃ cation and C ₄ H ₉ NH ₃ cation.

As shown in Figure 2, the band gap of the above metal sulfide is not less than 1.6eV, and the metal sulfide with a wide band gap is selected, so that the formed hole transport layer hardly absorbs incident light in the absorption band of the tandem cell, so that the The light loss of the formed hole transport layer is small.

As shown in FIG. 2, the metal sulfide may include manganese sulfide, zinc sulfide, nickel sulfide, titanium disulfide, molybdenum disulfide, magnesium sulfide, copper sulfide, digallium trisulfide, gallium monosulfide, germanium sulfide, germanium monosulfide , one or more of arsenic trisulfide, tin disulfide, tungsten disulfide, lead sulfide, but not limited thereto.

In one example, when the metal sulfide is manganese sulfide, since manganese sulfide is a high-mobility P-type semiconductor with an optical band gap of 3.25 eV, it does not absorb incident light in the absorption band of the tandem cell. And the valence band energy level of manganese sulfide is -5.24eV, which is very close to the highest occupied molecular orbital (Highest Occupied Molecular Orbital, abbreviated as HOMO) energy level of perovskite (about -5.30eV), which is conducive to the collection of hole charges. The conduction band energy level of manganese sulfide is -1.61eV, which is far from the lowest unoccupied molecular orbital (Lowest Unoccupied Molecular Orbital, abbreviated as LUMO) energy level of perovskite (about -3.90eV), which can effectively block electrons to the electrode. diffusion. And when the anchor layer is formed on the hole transport layer 2 made of manganese sulfide, the sulfur ion (soft base) in the manganese sulfide will form a strong bond with the lead ion (soft acid) in the anchor layer, This facilitates the subsequent formation of a uniform perovskite absorption layer 3 on the suede surface of the bottom battery.

3A-3H are schematic diagrams showing states of various stages of a method for fabricating a laminated battery provided by an embodiment of the present invention. A method for fabricating a laminated battery provided by an embodiment of the present invention includes:

As shown in FIG. 3A, a bottom battery 1 is provided, and the bottom battery 1 has a textured surface. Taking the N-type silicon wafer as the silicon substrate as an example, the manufacturing method of the bottom cell 1 includes:

Commercial grade M2 N-type silicon wafers are selected to undergo polishing, texturing and cleaning in sequence to form a monocrystalline silicon substrate. The resistivity of the N-type silicon wafer is 1Ω·cm-10Ω·cm, and the thickness is 50 μm-200 μm.

Plasma Enhanced Chemical VaporDeposition (PECVD for short) is used to deposit intrinsic amorphous silicon passivation layers on both sides of the monocrystalline silicon substrate to form a front passivation layer film and a back passivation layer film. The thickness of the passivation layer film and the backside passivation layer film is 1 nm-20 nm.

A phosphorus-doped N-type amorphous/microcrystalline silicon layer with a thickness of 1nm-30nm is deposited on the front side of the silicon wafer by PECVD to form a front field structure.

A boron-doped P-type amorphous/microcrystalline silicon layer with a thickness of 1nm-30nm is deposited on the backside of the silicon wafer by PECVD to form an emitter structure.

A transparent conductive material layer with a thickness of 30nm-120nm is fabricated by a magnetron sputtering method. In practical applications, the transparent conductive material layer may be an ITO transparent conductive material layer, an IZO transparent conductive material layer, an IWO transparent conductive material layer, an ITiO transparent conductive material layer, and the like.

As shown in FIG. 3B, a tunnel composite layer 4 is formed over the textured surface. Specifically, phosphorus and boron doped microcrystalline silicon films with thicknesses of 1 nm-30 nm are respectively fabricated on the textured surface of the bottom cell 1 to form a tunneling composite layer 4 to realize the tunneling composite collection of photogenerated carriers.

空穴传输层2厚度为5nm-100nm。As shown in FIG. 3C , the hole transport layer 2 is formed by co-depositing a metal sulfide hole transport material and an inorganic lead compound on the textured surface by a vacuum co-deposition process. Wherein, the band gap of the metal sulfide is not less than 1.6 eV, and the material ratio of the metal sulfide and the inorganic lead compound is 1:(0.01-0.5). Specifically, the hole transport layer 2 is formed by co-depositing metal sulfide and lead compound on the textured surface of the bottom cell 1 by using a vacuum thermal evaporation process. The inorganic lead compound is one or more of lead chloride, lead bromide, lead iodide, lead oxide, lead thiocyanate, and lead acetate. Metal sulfides are manganese sulfide, zinc sulfide, nickel sulfide, titanium disulfide, molybdenum disulfide, magnesium sulfide, copper sulfide, digallium trisulfide, gallium monosulfide, germanium sulfide, germanium monosulfide, arsenic trisulfide, disulfide One or more of tin, tungsten disulfide, lead sulfide. The vacuum thermal evaporation rates of metal sulfides and inorganic lead compounds are

The thickness of the hole transport layer 2 is 5 nm-100 nm.

卤化铅和卤化锡的真空蒸镀速率为

锚定层5的厚度为250nm-1000nm。As shown in FIG. 3D , the anchor layer 5 is formed by vacuum deposition on the hole transport layer 2 . The material contained in the anchor layer 5 is metal halide, and the metal halide includes at least lead halide. Specifically, the metal halide is co-deposited on the hole transport layer 2 by vacuum evaporation to obtain the anchor layer 5 . Wherein, the metal halide also includes one or both of tin halide and alkali metal halide. The vacuum evaporation rate of alkali metal halide is

The vacuum evaporation rate of lead halide and tin halide is

The thickness of the anchor layer 5 is 250nm-1000nm.

As shown in FIG. 3E , the cationic salt is coated on the anchor layer 5 by a solution method. Specifically, a solution method is used to coat the anchor layer 5 with a cationic salt solution, so that the material contained in the anchor layer 5 reacts with the cationic salt to form the perovskite absorption layer 3 . The perovskite absorption layer 3 is a perovskite absorption layer 3 having lead ions.

As shown in FIG. 3E, the perovskite absorber layer 3 is annealed. Specifically, the temperature of the annealing treatment is 50° C.-200° C., the time of the annealing treatment is 5 minutes-60 minutes, and the thickness of the formed dense and uniform perovskite absorption layer 3 is 100 nm-1000 nm.

As shown in FIG. 3F , an electron transport interface layer is formed on the perovskite absorber layer 3 . In practical applications, the electron transport interface layers can be LiF electron transport interface layer 6 and C ₆₀ electron transport interface layer 7 . The LiF electron transport interface layer 6 is formed on the perovskite absorption layer 3, and the thickness of the LiF electron transport interface layer 6 is 0.1 nm-10 nm. The C ₆₀ electron transport interface layer 7 is formed on the LiF electron transport interface layer 6 , and the thickness of the C ₆₀ electron transport interface layer 7 is 1 nm-20 nm. In practical applications, the LiF electron transport interface layer 6 and the C ₆₀ electron transport interface layer 7 may be omitted, or all of them may be omitted.

As shown in FIG. 3G , an electron transport layer 8 is formed on the perovskite absorber layer 3 . In practical applications, the material of the electron transport layer can be SnO ₂ , the layer thickness can be 1nm-30nm, and the manufacturing process can be atomic layer deposition (ALD), chemical vapor deposition, physical vapor deposition, solution coating process any of the.

As shown in FIG. 3H , electrodes 9 are formed on the electron transport layer 8 . In practical applications, the magnetron sputtering method can be used to make the transparent conductive film, and the thickness of the transparent conductive film is 30nm-200nm. The silver electrode grid line 9 can be made on the transparent conductive film by means of evaporation, screen printing, etc. The thickness of the silver electrode grid line 9 can be 100nm-500nm, and the material of the silver electrode grid line can be conductive silver, copper, aluminum, etc. Metal with better performance.

Compared with the prior art, the beneficial effects of the method for fabricating a laminated battery provided by the embodiment of the present invention are the same as those of the above-mentioned laminated battery, which will not be repeated here.

In order to verify the performance of the laminated battery manufactured by the manufacturing method of the laminated battery provided in the embodiment of the present invention, the following description is made by comparing the embodiment and the comparative example with each other.

Example 1

The manufacturing method of the n-type silicon heterojunction-perovskite tandem battery provided by the embodiment of the present invention is as follows:

The first step: providing an N-type M2 silicon wafer with a resistivity of 2Ω·cm-4Ω·cm and a thickness of 180 μm. The silicon wafer is polished, textured and cleaned to form an n-type single crystal silicon substrate with textured surfaces.

Step 2: Use plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) to deposit intrinsic amorphous silicon passivation layers on both sides of the n-type single crystal silicon substrate respectively to form the front passivation layer film and the back side Passivation film. The thickness of the front passivation layer film and the back passivation layer film is 5 nm.

The third step: depositing an N-type amorphous silicon layer doped with phosphorus (doping concentration 10 ²⁰ cm ^-3 ) on the front side of the silicon wafer by PECVD method, and the thickness of the N-type amorphous silicon layer is 10 nm to form a front-side emitter.

The fourth step: depositing a P-type amorphous silicon layer doped with boron (doping concentration 10 ¹⁹ cm ^-3 ) on the back of the silicon wafer by PECVD method, and the thickness of the P-type amorphous silicon layer is 10 nm to form a back field structure.

The fifth step: using a magnetron sputtering process to prepare a transparent conductive layer of ITO material with a thickness of 100 nm on the P-type amorphous silicon layer.

The sixth step: respectively fabricating phosphorus- and boron-doped microcrystalline silicon films with a thickness of 8 nm on the textured surface of the bottom cell to form a tunneling composite layer.

空穴传输层厚度为15nm。Step 7: Co-deposit manganese sulfide and lead oxide on the bottom battery suede surface by vacuum thermal evaporation to form a hole transport layer. The substance ratio of manganese sulfide and lead oxide is 1:0.25. By controlling the current, the vacuum thermal evaporation rates of manganese sulfide and lead oxide are both

The hole transport layer thickness was 15 nm.

溴化铯的真空蒸镀速率为

锚定层的厚度为350nm。The eighth step: co-depositing lead iodide and cesium bromide on the hole transport layer by vacuum evaporation to obtain an anchor layer. Among them, the vacuum evaporation rate of lead iodide is

The vacuum evaporation rate of cesium bromide is

The thickness of the anchor layer was 350 nm.

The ninth step: configure a mixed solution of Formamidinium Iodide (Formamidinium Iodide, abbreviated as FAI) and Formamidinium Bromide (abbreviated as FABr), the molar concentration ratio is 3:1, and the solvent is ethanol. 100 μL of the mixed solution of FAI and FABr was spin-coated on the anchor layer and reacted to form a perovskite absorbing material film.

The tenth step: annealing the perovskite absorbing material film to form a dense and uniform perovskite absorbing layer with a thickness of 500 nm. The temperature of the annealing treatment is 150° C., the time of the annealing treatment is 30 min, and the material composition of the perovskite absorbing layer is Cs _x FA _1-x Pb(Br _y I _1-y ) ₃ .

Step 11: Evaporate LiF on the perovskite absorber layer to form a LiF electron transport interface layer with a thickness of 1 nm. Then, C _{60 with a thickness of 10 nm was evaporated on the LiF electron transport interface layer to form the C 60 electron} transport interface layer.

The twelfth step: using atomic layer deposition (Atomic layer deposition, abbreviated as ALD) to fabricate a SnO ₂ electron transport layer with a thickness of 10 nm.

The thirteenth step: using a magnetron sputtering method to fabricate an ITO transparent conductive film with a thickness of 100 nm. Then, a silver electrode grid line was fabricated on the ITO transparent conductive film by evaporation method to obtain a stacked battery, and the thickness of the silver electrode grid line was 100 nm.

Embodiment 2

The manufacturing method of the n-type silicon heterojunction-perovskite tandem battery provided by the embodiment of the present invention is as follows:

The first step: providing an N-type M2 silicon wafer with a resistivity of 5Ω·cm-10Ω·cm and a thickness of 50 μm. The silicon wafer is polished, textured and cleaned to form an n-type single crystal silicon substrate with textured surfaces.

The second step: using plasma enhanced chemical vapor deposition (PlasmaEnhancedChemicalVaporDeposition, abbreviated PECVD) to deposit intrinsic amorphous silicon passivation layers on both sides of the n-type single crystal silicon substrate respectively to form a front passivation layer film and a back passivation layer film. The thickness of the front passivation layer film and the back passivation layer film is 1 nm.

The third step: using the PECVD method to deposit an N-type amorphous silicon layer doped with phosphorus (doping concentration 10 ²⁰ cm ^-3 ) on the front side of the silicon wafer. The thickness of the N-type amorphous silicon layer is 1 nm to form a front-side emitter.

The fourth step: depositing a boron-doped (doping concentration of 10 ¹⁹ cm ^-3 ) P-type amorphous silicon layer on the back of the silicon wafer by PECVD, and the thickness of the P-type amorphous silicon layer is 1 nm to form a back field structure.

The fifth step: using a magnetron sputtering process to prepare a transparent conductive layer of IZO material with a thickness of 30 nm on the P-type amorphous silicon layer.

The sixth step: respectively fabricating phosphorus and boron doped microcrystalline silicon films with a thickness of 7 nm on the textured surface of the bottom cell to form a tunneling composite layer.

空穴传输层厚度为5nm。The seventh step: using the vacuum thermal evaporation process to co-deposit zinc sulfide and lead chloride on the suede surface of the bottom battery to form a hole transport layer. The substance ratio of zinc sulfide and lead chloride is 1:0.01. By controlling the current, the vacuum thermal evaporation rates of zinc sulfide and lead chloride are both

The hole transport layer thickness was 5 nm.

溴化铯的真空蒸镀速率为

锚定层的厚度为250nm。The eighth step: co-depositing lead iodide and cesium bromide on the hole transport layer by vacuum evaporation to obtain an anchor layer. Among them, the vacuum evaporation rate of lead iodide is

The vacuum evaporation rate of cesium bromide is

The thickness of the anchor layer was 250 nm.

The ninth step: configure a mixed solution of Formamidinium Iodide (Formamidinium Iodide, abbreviated as FAI) and Formamidinium Bromide (abbreviated as FABr), the molar concentration ratio is 3:1, and the solvent is ethanol. 100 μL of the mixed solution of FAI and FABr was spin-coated on the anchor layer and reacted to form a perovskite absorbing material film.

The tenth step: annealing the perovskite absorbing material film to form a dense and uniform perovskite absorbing layer with a thickness of 200 nm. The temperature of the annealing treatment was 50° C., and the time of the annealing treatment was 5 min.

Step 11: Evaporate LiF on the perovskite absorber layer to form a LiF electron transport interface layer with a thickness of 0.1 nm. Then, C _{60 with a thickness of 1 nm was evaporated on the LiF electron transport interface layer to form the C 60 electron} transport interface layer.

The twelfth step: using atomic layer deposition (Atomic layer deposition, abbreviated as ALD) to fabricate a SnO ₂ electron transport layer with a thickness of 30 nm.

The thirteenth step: using a magnetron sputtering method to fabricate an IZO transparent conductive film with a thickness of 100 nm. Then, a silver electrode grid line was fabricated on the IZO transparent conductive film by evaporation method to obtain a stacked battery, and the thickness of the silver electrode grid line was 200 nm.

Embodiment 3

The manufacturing method of the n-type silicon heterojunction-perovskite tandem battery provided by the embodiment of the present invention is as follows:

The first step: providing an N-type M2 silicon wafer with a resistivity of 1Ω·cm-5Ω·cm and a thickness of 200 μm. The silicon wafer is polished, textured and cleaned to form an n-type single crystal silicon substrate with textured surfaces.

Step 2: Use plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) to deposit intrinsic amorphous silicon passivation layers on both sides of the n-type single crystal silicon substrate respectively to form the front passivation layer film and the back side Passivation film. The thickness of the front passivation layer film and the back passivation layer film is 20 nm.

The third step: using the PECVD method to deposit an N-type amorphous silicon layer doped with phosphorus (doping concentration 10 ²⁰ cm ^-3 ) on the front side of the silicon wafer. The thickness of the N-type amorphous silicon layer is 30 nm to form a front-side emitter.

The fourth step: depositing a boron-doped (doping concentration 10 ¹⁹ cm ^-3 ) P-type amorphous silicon layer on the back of the silicon wafer by PECVD, and the thickness of the N-type amorphous silicon layer is 30 nm to form a back field structure.

The fifth step: using a magnetron sputtering process to prepare a transparent conductive layer of IWO material with a thickness of 120 nm on the P-type amorphous silicon layer.

The sixth step: respectively fabricating phosphorus- and boron-doped microcrystalline silicon films with a thickness of 30 nm on the textured surface of the bottom cell to form a tunneling composite layer.

空穴传输层厚度为100nm。The seventh step: using a vacuum thermal evaporation process to co-deposit a mixture of nickel sulfide and titanium disulfide and lead iodide on the suede surface of the bottom battery to form a hole transport layer. The mass ratio of the mixture of nickel sulfide and titanium disulfide to lead iodide is 1:0.5. By controlling the current, the vacuum thermal evaporation rates of the mixture of nickel sulfide and titanium disulfide and lead iodide are both

The hole transport layer thickness was 100 nm.

碘化铯的真空蒸镀速率为

锚定层的厚度为1000nm。Step 8: Co-deposit lead bromide and cesium iodide on the hole transport layer by vacuum evaporation, wherein the vacuum evaporation rate of lead bromide is

The vacuum evaporation rate of cesium iodide is

The thickness of the anchor layer was 1000 nm.

The ninth step: configure a mixed solution of Formamidinium Iodide (Formamidinium Iodide, abbreviated as FAI) and Formamidinium Bromide (abbreviated as FABr), the molar concentration ratio is 3:1, and the solvent is ethanol. 100 μL of the mixed solution of FAI and FABr was spin-coated on the anchor layer and reacted to form a perovskite absorbing material film.

The tenth step: annealing the perovskite absorbing material film to form a dense and uniform perovskite absorbing layer with a thickness of 1000 nm. The temperature of the annealing treatment was 200° C., and the time of the annealing treatment was 30 min.

Step 11: Evaporate LiF on the perovskite absorber layer to form a LiF electron transport interface layer with a thickness of 10 nm. Then, C _{60 with a thickness of 20 nm was evaporated on the LiF electron transport interface layer to form the C 60 electron} transport interface layer.

The twelfth step: using atomic layer deposition (Atomic layer deposition, abbreviated as ALD) to fabricate a SnO ₂ electron transport layer with a thickness of 1 nm.

The thirteenth step: using a magnetron sputtering method to fabricate an IWO transparent conductive film with a thickness of 30 nm. Then use the evaporation method to make silver electrode gridlines on the IWO transparent conductive film to obtain a stacked battery, and the thickness of the silver electrode gridlines is 500 nm.

Embodiment 4

The manufacturing method of the n-type silicon heterojunction-perovskite tandem battery provided by the embodiment of the present invention is as follows:

The first step: providing an N-type M2 silicon wafer with a resistivity of 1Ω·cm-4Ω·cm and a thickness of 150 μm. The silicon wafer is polished, textured and cleaned to form an n-type single crystal silicon substrate with textured surfaces.

Step 2: Use plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) to deposit intrinsic amorphous silicon passivation layers on both sides of the n-type single crystal silicon substrate respectively to form the front passivation layer film and the back side Passivation film. The thickness of the front passivation layer film and the back passivation layer film was 15 nm.

The third step: depositing a phosphorus-doped (doping concentration 10 ²⁰ cm ^-3 ) N-type amorphous silicon layer on the front side of the silicon wafer by PECVD, the thickness of the N-type amorphous silicon layer is 15nm, to form a front-side emitter.

The fourth step: depositing a boron-doped (doping concentration 10 ¹⁹ cm ^-3 ) P-type amorphous silicon layer on the backside of the silicon wafer by PECVD, and the thickness of the P-type amorphous silicon layer is 15 nm to form a back field structure.

The fifth step: using a magnetron sputtering process to prepare a transparent conductive layer made of ITiO with a thickness of 70 nm on the P-type amorphous silicon layer.

The sixth step: respectively fabricating phosphorus and boron doped microcrystalline silicon films with a thickness of 15 nm on the textured surface of the bottom battery to form a tunneling composite layer.

空穴传输层厚度为55nm。Step 7: Co-deposit molybdenum disulfide and lead bromide on the bottom battery suede surface by vacuum thermal evaporation to form a hole transport layer. The substance ratio of molybdenum disulfide and lead bromide is 1:0.45. By controlling the current, the vacuum thermal evaporation rates of molybdenum disulfide and lead bromide are both

The hole transport layer thickness was 55 nm.

氯化铯的真空蒸镀速率为

锚定层的厚度为500nm。The eighth step: co-depositing lead iodide, tin iodide and cesium chloride on the hole transport layer by vacuum evaporation to obtain an anchor layer. Among them, the vacuum evaporation rate of lead iodide and tin iodide is

The vacuum evaporation rate of cesium chloride is

The thickness of the anchor layer was 500 nm.

The ninth step: configure a mixed solution of Formamidinium Iodide (Formamidinium Iodide, abbreviated as FAI) and Formamidinium Bromide (abbreviated as FABr), the molar concentration ratio is 3:1, and the solvent is ethanol. 100 μL of the mixed solution of FAI and FABr was spin-coated on the anchor layer and reacted to form a perovskite absorbing material film.

The tenth step: annealing the perovskite absorbing material film to form a dense and uniform perovskite absorbing layer with a thickness of 100 nm. The temperature of the annealing treatment was 170° C., and the time of the annealing treatment was 60 min.

Step 11: Evaporate LiF on the perovskite absorber layer to form a LiF electron transport interface layer with a thickness of 5 nm. Then, C _{60 with a thickness of 15 nm was evaporated on the LiF electron transport interface layer to form the C 60 electron} transport interface layer.

The twelfth step: using atomic layer deposition (Atomic layer deposition, abbreviated as ALD) to fabricate a SnO ₂ electron transport layer with a thickness of 15 nm.

The thirteenth step: using a magnetron sputtering method to fabricate an ITiO transparent conductive film with a thickness of 200 nm. Then, a silver electrode grid line was fabricated on the ITiO transparent conductive film by evaporation method to obtain a stacked battery, and the thickness of the silver electrode grid line was 255 nm.

Embodiment 5

The manufacturing method of the n-type silicon heterojunction-perovskite tandem battery provided by the embodiment of the present invention is as follows:

The first step: providing an N-type M2 silicon wafer with a resistivity of 1Ω·cm-5Ω·cm and a thickness of 200 μm. The silicon wafer is polished, textured and cleaned to form an n-type single crystal silicon substrate with textured surfaces.

Step 2: Use plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) to deposit intrinsic amorphous silicon passivation layers on both sides of the n-type single crystal silicon substrate respectively to form the front passivation layer film and the back side Passivation film. The thickness of the front passivation layer film and the back passivation layer film is 20 nm.

The third step: using the PECVD method to deposit an N-type amorphous silicon layer doped with phosphorus (doping concentration 10 ²⁰ cm ^-3 ) on the front side of the silicon wafer. The thickness of the N-type amorphous silicon layer is 30 nm to form a front-side emitter.

The fourth step: depositing a boron-doped (doping concentration 10 ¹⁹ cm ^-3 ) P-type amorphous silicon layer on the back of the silicon wafer by PECVD, and the thickness of the N-type amorphous silicon layer is 30 nm to form a back field structure.

The fifth step: using a magnetron sputtering process to prepare a transparent conductive layer of IWO material with a thickness of 120 nm on the P-type amorphous silicon layer.

The sixth step: respectively fabricating phosphorus- and boron-doped microcrystalline silicon films with a thickness of 30 nm on the textured surface of the bottom cell to form a tunneling composite layer.

空穴传输层厚度为100nm。Step 7: Co-depositing magnesium sulfide and a mixture of lead thiocyanate and lead acetate on the bottom battery suede by a vacuum thermal evaporation process to form a hole transport layer. The substance ratio of nickel sulfide and the mixture of lead thiocyanate and lead acetate is 1:0.5. By controlling the current, the vacuum thermal evaporation rates of nickel sulfide and the mixture of lead thiocyanate and lead acetate are both

The hole transport layer thickness was 100 nm.

碘化铯的真空蒸镀速率为

锚定层的厚度为1000nm。The eighth step: co-deposit lead chloride and cesium iodide on the hole transport layer by vacuum evaporation, wherein the vacuum evaporation rate of lead chloride is

The vacuum evaporation rate of cesium iodide is

The thickness of the anchor layer was 1000 nm.

The ninth step: configure a mixed solution of Formamidinium Iodide (Formamidinium Iodide, abbreviated as FAI) and Formamidinium Bromide (abbreviated as FABr), the molar concentration ratio is 3:1, and the solvent is ethanol. 100 μL of the mixed solution of FAI and FABr was spin-coated on the anchor layer and reacted to form a perovskite absorbing material film.

The tenth step: annealing the perovskite absorbing material film to form a dense and uniform perovskite absorbing layer with a thickness of 1000 nm. The temperature of the annealing treatment was 200° C., and the time of the annealing treatment was 30 min.

Step 11: Evaporate LiF on the perovskite absorber layer to form a LiF electron transport interface layer with a thickness of 10 nm. Then, C _{60 with a thickness of 20 nm was evaporated on the LiF electron transport interface layer to form the C 60 electron} transport interface layer.

The twelfth step: using atomic layer deposition (Atomic layer deposition, abbreviated as ALD) to fabricate a SnO ₂ electron transport layer with a thickness of 1 nm.

The thirteenth step: using a magnetron sputtering method to fabricate an IWO transparent conductive film with a thickness of 30 nm. Then use the evaporation method to make silver electrode gridlines on the IWO transparent conductive film to obtain a stacked battery, and the thickness of the silver electrode gridlines is 500 nm.

Comparative Example 1

The manufacturing method of the laminated battery provided in this comparative example is basically the same as the method described in the above-mentioned first embodiment, the only difference is that the material of the hole transport layer is Spiro-TTB.

Comparative Example 2

The manufacturing method of the laminated battery provided by this comparative example is basically the same as the method described in the above-mentioned Embodiment 1, except that the material of the hole transport layer is nickel oxide.

In order to verify the performance of the tandem cells, scanning electron microscope (SEM) and I-V tests were carried out on the tandem cells prepared in Example 1, Comparative Example 1 and Comparative Example 2, and the photoelectric conversion efficiency, fill factor and open circuit voltage of each device were compared. , short-circuit current and other performance parameters (Table 1).

Table 1 The performance parameters of the tandem battery

According to Table 1, it can be seen that the performance parameters of the tandem battery prepared by using manganese sulfide and inorganic lead compounds as hole transport materials are obviously better than those of the currently widely used materials such as Spiro and nickel oxide.

FIG. 4 shows the SEM image of the textured surface of the laminated battery produced in Example 1, and FIG. 5 is the SEM image of the textured surface of the laminated battery prepared in Example 1. It can be seen from FIGS. 4 and 5 The lower surface of the perovskite layer is closely attached to the bottom cell, there is no interfacial void and peeling phenomenon, and the perovskite thin film grows uniformly without obvious grain boundary defects, which proves that the laminate prepared by the method of the embodiment of the present invention is used. The cell can retain the textured structure of the bottom cell and increase the efficiency of the tandem cell.

FIG. 6 shows the IV curves of the tandem cells prepared in Example 1, Comparative Example 1 and Comparative Example 2 of the present invention under the strong irradiation of AM1.5G sunlight. It can be seen from FIG. 6 that the short-circuit current J _sc of the laminated battery prepared in Example 1 is 20.0 mA/cm ² , the open-circuit voltage V _oc is 1.68 V, the filling factor FF is 77%, and the final battery conversion efficiency is 26.0%. The device performance parameters of the laminated battery prepared in Example 1 are obviously better than those of the traditional laminated battery.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as those described above. Additionally, although the various embodiments have been described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

Embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims (12)

1. a manufacturing method of a laminated battery, is characterized in that, comprises: providing a bottom cell, the bottom cell having a suede surface; A hole transport layer is formed by co-depositing a metal sulfide hole transport material and an inorganic lead compound on the textured surface by a vacuum co-deposition process; the band gap of the metal sulfide is not less than 1.6 eV, and the inorganic lead compound is One or more of lead chloride, lead bromide, lead iodide, lead oxide, lead thiocyanate, and lead acetate; An anchor layer is formed by vacuum deposition on the hole transport layer, and the material contained in the anchor layer is a metal halide; the metal halide at least includes lead halide; The anchoring layer is coated with a cationic salt by a solution method; the material contained in the anchoring layer reacts with the cationic salt to form a perovskite absorption layer; wherein, the perovskite absorption layer and the hole transport layer are both containing lead ions, so that when the perovskite absorption layer is formed on the hole transport layer, the hole transport layer acts as an induction layer, inducing crystal growth of the perovskite absorption layer material; forming an electron transport layer on the perovskite absorber layer; Electrodes are formed on the electron transport layer. 2 . The method for manufacturing a stacked battery according to claim 1 , wherein the metal halide further comprises one or both of tin halide and alkali metal halide. 3 . 3. The method for manufacturing a laminated battery according to claim 1 or 2, wherein the vacuum co-deposition process is used to co-deposit a metal sulfide and an inorganic lead compound on the textured surface to form a hole transport layer The method includes: co-depositing a metal sulfide and an inorganic lead compound on the suede surface using a vacuum thermal evaporation process to obtain a hole transport layer; the vacuum thermal evaporation rate of the metal sulfide and the inorganic lead compound is:

4 . The method for manufacturing a laminated battery according to claim 2 , wherein the forming the anchor layer by vacuum deposition on the hole transport layer comprises: vacuum evaporation on the hole transport layer. 5 . Co-depositing metal halide to obtain an anchor layer; the vacuum evaporation rate of the alkali metal halide is

The vacuum evaporation rate of the lead halide and tin halide is

5 . The method for manufacturing a laminated battery according to claim 1 or 2 , wherein the applying a solution method to coating a cationic salt on the anchor layer comprises: applying a solution method to the anchor layer. 6 . distributing a cationic salt solution such that the metal halide contained in the anchor layer reacts with the cationic salt to form a perovskite absorber layer; and/or, After the solution method is used to form the cationic salt on the anchor layer, and before the electron transport layer is formed on the perovskite absorption layer, the method for manufacturing the stacked battery further includes: applying the perovskite to the perovskite absorbing layer. The absorption layer is subjected to annealing treatment; the temperature of the annealing treatment is 50° C.-200° C., and the time of the annealing treatment is 5 minutes to 60 minutes. 6. The manufacturing method of the stacked battery according to claim 1 or 2, wherein before the electron transport layer is fabricated on the perovskite absorption layer, the manufacturing method of the stacked battery further comprises: An electron transport interface layer is formed on the perovskite absorber layer; the electron transport interface layer includes a LiF layer and a C ₆₀ layer; the LiF layer is formed on the perovskite absorber layer, and the C ₆₀ layer is formed On the LiF layer; wherein, the thickness of the LiF layer is 0.1nm-10nm, and the thickness of the _C60 layer is 1nm-20nm; and / or, Before forming the hole transport layer on the textured surface, the manufacturing method of the stacked battery further includes: forming a tunneling composite layer on the textured surface. 7. A laminated battery formed by the manufacturing method of any one of claims 1-6, comprising: a bottom cell, the bottom cell having a suede surface; A hole transport layer formed above the textured surface, the hole transport layer is formed by vacuum co-deposition of a metal sulfide hole transport material and an inorganic lead compound, the band gap of the metal sulfide is not less than 1.6eV, so The inorganic lead compound is one or more of lead chloride, lead bromide, lead iodide, lead oxide, lead thiocyanate, and lead acetate; wherein, the metal sulfide and the inorganic lead compound are uniformly deposited on the on the textured surface of the bottom battery, so that the light trapping effect of the textured surface is retained; A perovskite absorber layer formed on the hole transport layer, the perovskite absorber layer containing lead ions. 8 . The laminated battery according to claim 7 , wherein the material ratio of the metal sulfide and the inorganic lead compound is 1:(0.01˜0.5). 9 . 9 . The laminated battery according to claim 7 , wherein the metal sulfides include manganese sulfide, zinc sulfide, nickel sulfide, titanium disulfide, molybdenum disulfide, magnesium sulfide, copper sulfide, and digallium trisulfide. 10 . , one or more of gallium monosulfide, germanium sulfide, germanium monosulfide, arsenic trisulfide, tin disulfide, tungsten disulfide and lead sulfide. 10 . The stacked battery according to claim 7 , wherein the chemical formula of the perovskite absorber layer is ABX ₃ ; wherein, A is one or more of alkylamine cation, methyldiamine cation, cesium cation, B is one or more of alkali metal cation, Pb ²⁺ , Sn ²⁺ , X is I ^- , Cl ^{- ,} one or more of Br-. 11. The tandem battery according to any one of claims 7-10, wherein the perovskite absorption layer has a thickness of 100 nm-1000 nm; and/or, The thickness of the hole transport layer is 5nm-100nm. 12. The stacked battery according to any one of claims 7-10, wherein the stacked battery further comprises a tunneling composite layer formed above the textured surface, and the hole transport layer is formed on the on the tunneling composite layer.

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