CN112083791B - Chip power consumption optimization method, apparatus, computer equipment and storage medium - Google Patents

Abstract

The present application relates to a chip power consumption optimization method, apparatus, computer equipment and storage medium. By adopting the present application, the automatic management process of chip power consumption optimization can be completed, and the power consumption can be further saved. The method includes: by storing the wake-up mode command and the power-down mode command in the wake-up mode register and the power-down mode register, respectively, in response to the power-down mode command, triggering the power-down enable register to start the power-down process, and in the power-down process control the power domain specified by the above power-down mode command to enter the low power consumption mode; receive the wake-up signal generated by the wake-up source corresponding to the above-mentioned wake-up source information; if the wake-up signal is a valid wake-up signal, control the wake-up mode command specified above. The power domain enters the power switch mode described above.

Description

Chip power consumption optimization method, apparatus, computer equipment and storage medium

technical field

The present application relates to the field of battery technology, and in particular, to a method, device, computer equipment and storage medium for optimizing chip power consumption.

Background technique

With the development of Internet of Things technology, people's demand for wearable electronic products has increased, and at the same time, there are further requirements for the battery life of wearable electronic products. Limited by the development of battery capacity, the power consumption optimization of chips is becoming more and more important. received attention.

There are many chip power optimization technologies, and the multi-power domain technology is one of the effective and widely used technologies. The multi-power domain technology divides the chip architecture into multiple power domains to supply power separately. Each power domain can use different voltages to supply power as needed, and when a power domain is not required to work, the power of the power domain can be turned off. To achieve the purpose of reducing chip power consumption.

The current multi-power domain technology is not enough to reduce power consumption when the chip is in some modes, and cannot meet the current demand for chip endurance.

SUMMARY OF THE INVENTION

Based on this, it is necessary to provide a method, apparatus, computer device and storage medium for optimizing chip power consumption in response to the above technical problems.

A method for optimizing chip power consumption, the method comprising:

The wake-up mode instruction is stored in the wake-up mode register; the wake-up mode instruction carries the wake-up source information and the power switch mode entered by the chip system after the chip system is woken up;

Store the power-down mode command in the power-down mode register;

In response to the power-down mode instruction, trigger the power-down enable register to start the power-down process and control the power domain specified by the power-down mode instruction to enter the low power consumption mode in the power-down process;

receiving a wake-up signal generated by a wake-up source corresponding to the wake-up source information;

If the wake-up signal is a valid wake-up signal, the power domain specified by the wake-up mode instruction is controlled to enter the power switch mode.

In one of the embodiments, it further includes that the chip system includes a plurality of power domains; a level converter or an isolation unit is arranged between each power domain; wherein,

When the absolute value of the difference between the respective power supply voltages of the two power supply domains is greater than a preset value, and there is digital signal communication between the two power supply domains, the level converter is provided between the two power supply domains;

The isolation unit is provided between the two power domains when there is digital signal communication between the two power domains, and one of the two power domains is powered down and the other is not powered off.

In one embodiment, in response to the power-down mode command, triggering a power-down enable register to initiate a power-down process and control the power domain specified by the power-down mode command to enter a low state during the power-down process power modes, including:

According to the power-down mode command, the power-down enable register is triggered to send a power-down enable signal to the power domain specified by the power-down mode command, so as to enable the clock signal of the power domain specified by the power-down mode command closure;

triggering a reset of the power domain specified by the power-down mode instruction in response to the clock signal being turned off;

The isolation unit corresponding to the power domain specified by the power-down mode command after reset is enabled, and the voltage controller corresponding to the power domain specified by the power-down mode command after the reset is turned off.

In one embodiment, the controlling the power domain specified by the wake-up mode instruction to enter the power switch mode includes:

According to the valid wake-up signal, turn on the voltage controller corresponding to the power domain specified by the wake-up mode command, and de-reset the power domain specified by the wake-up mode command;

disabling the isolation unit corresponding to the power supply domain specified by the wake-up mode command after de-resetting;

Restart the clock signal corresponding to the power domain specified by the wake-up mode instruction.

In one of the embodiments, the chip system includes a normally-on power supply domain and a flip-flop; the method further includes:

When the wake-up source information is an invalid internal wake-up signal, if the power-down mode command includes one of deep-sleep mode or static memory retention mode, the trigger is used to trigger the clock signal of the normally-on power domain. closure.

In one of the embodiments, after the triggering of the trigger by the flip-flop to turn off the clock signal of the normally-on power domain, the method further includes:

When the wake-up source information is that the internal wake-up signal is invalid and the external wake-up signal is valid, the flip-flop triggered to reset generates a clock enable signal and sends it to the normally-on power domain, so that the normally-on power domain Restart the clock signal.

In one of the embodiments, the chip system includes a software wake-up register; the method further includes:

When the low power consumption mode is one of flash off mode, bluetooth off mode or flash memory and bluetooth off mode at the same time, use the valid wake-up signal as a software wake-up command and store it in the software wake-up register;

According to the software wake-up command, the voltage controller corresponding to the power domain specified by the software wake-up command is turned on; the power domain specified by the software wake-up command is a flash power domain or a Bluetooth power domain;

De-reset the power domain specified by the software wake-up instruction;

disabling the isolation unit corresponding to the power supply domain specified by the software wake-up command after de-resetting;

Restart the clock signal corresponding to the power domain specified by the software wake-up instruction.

A device for optimizing chip power consumption, the device comprising:

a wake-up mode instruction storage module, used for storing the wake-up mode instruction in the wake-up mode register; the wake-up mode instruction carries the wake-up source information and the power switch mode entered by the chip system after the chip system is woken up;

The power-down mode command storage module is used to store the power-down mode command in the power-down mode register;

A power domain power-down module, configured to trigger a power-down enable register to start a power-down process in response to the power-down mode command, and control the power domain specified by the power-down mode command to enter a low-power state during the power-down process in consumption mode;

a wake-up signal receiving module, configured to receive a wake-up signal generated by a wake-up source corresponding to the wake-up source information;

A power domain wake-up module, configured to control the power domain specified by the wake-up mode instruction to enter the power switch mode if the wake-up signal is a valid wake-up signal.

A computer device includes a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of any of the above-mentioned methods for optimizing chip power consumption are implemented.

A computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, implements the steps of any one of the above-mentioned methods for optimizing chip power consumption.

The above-mentioned chip power consumption optimization method, device, computer equipment and storage medium, by storing the wake-up mode command and the power-down mode command in the wake-up mode register and the power-down mode register, respectively, in response to the power-down mode command, triggering the power-down mode command. The power register starts the power-down process and controls the power domain specified by the above power-down mode command to enter the low-power mode in the power-down process; receives the wake-up signal generated by the wake-up source corresponding to the above wake-up source information; if the wake-up signal is a valid wake-up signal, then control the power domain specified by the above wake-up mode command to enter the above-mentioned power switch mode. The chip power consumption optimization method pre-stores the corresponding wake-up mode command or power-down mode command through a preset register, enters the corresponding low-power mode under the trigger of the power-down mode command, and executes the specified wake-up signal and wake-up mode command. The corresponding power switch mode is entered under the trigger of the , and the automatic management process of chip power consumption optimization is completed, and the power consumption of the chip can be further saved.

Description of drawings

1 is an architecture diagram of a chip power domain of a method for optimizing chip power consumption in one embodiment;

2 is a schematic flowchart of a method for optimizing chip power consumption in one embodiment;

3 is a schematic structural diagram of a flip-flop in one embodiment;

4 is a schematic flowchart of a method for optimizing chip power consumption in another embodiment;

5 is a structural block diagram of an apparatus for optimizing chip power consumption in one embodiment;

FIG. 6 is a diagram of the internal structure of a computer device in one embodiment.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present application more clearly understood, the present application will be described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application.

The chip power consumption optimization method provided by the present application can be applied to the chip power domain architecture as shown in FIG. 1 . Among them, the entire chip system is divided into 5 power domains, namely power domain 1 (Always-on domain, normally open power domain), power domain 2 (Retention SRAM domain, static memory power domain), power domain 3 (CORE domain) , core power domain), power domain 4 (BLE domain, Bluetooth power domain), power domain 5 (FLASH domain, flash memory power domain), each power domain uses its own voltage to supply power, as shown in Figure 1.

Power domain 1 (Always-on domain, normally-on power domain) is powered by an external power supply VCC, and the power supply voltage is 1.8V to 3.6V. The power supply of power domain 1 is always on. The power domain 1 includes a power management unit (PMU), and also includes a controller (AON) of the power management unit. The power management unit PMU mainly includes the voltage controller (LPLDO_SRAM) of power domain 2, the voltage controller of power domain 3 (MLDO_CORE), the voltage controller of power domain 4 (MLDO_RF), and the voltage controller of power domain 5 (LPLDO_FLASH). The voltage controller LPLDO_SRAM of power domain 2 outputs 1.2V to power domain 2, the voltage controller MLDO_CORE of power domain 3 outputs 1.2V to power domain 3, and the voltage controller MLDO_RF of power domain 4 outputs 1.3V to the power domain 4. LPLDO_FLASH outputs 1.2V to power domain 5.

Power Domain 2 is powered by the LPLDO_SRAM in Power Domain 1. The power domain 2 includes multiple SRAMs, and each SRAM has an independent power switch in the power domain 2. When the system is working normally, these SRAMs can be used as ordinary SRAMs; when other power domains that can be powered off are powered off, one or more SRAMs in power domain 2 can be selected to not be powered off, and will not be powered off at this time. The power SRAM plays a data retention function, which is used to store the data that you do not want to lose after power failure.

Power Domain 3 is powered by MLDO_CORE in Power Domain 1. Power domain 3 contains the main logic circuits of the chip, including CPU, peripherals, etc. When MLDO_CORE is powered, it can provide two modes, normal operation mode and low voltage operation mode. In the low-voltage working mode, the output voltage of MLDO_CORE is reduced to 1.02V, which can reduce the power consumption of the power domain 3 compared to the normal working mode.

Power Domain 4 is powered by MLDO_RF in Power Domain 1. The power domain 4 mainly includes a Bluetooth module (BLE). When the chip does not need to use the Bluetooth function temporarily, the power domain 4 can be powered off.

Power Domain 5 is powered by LPLDO_FLASH in Power Domain 1. The power domain 5 mainly includes a FLASH, and the software program runs in the FLASH during normal operation. When the software program running on the chip is not large, it can be selected to run in the RAM inside the power domain 2, and the power domain 5 can be powered off at this time.

In one embodiment, as shown in FIG. 2 , a schematic flowchart of a method for optimizing chip power consumption is provided, and the method is applied to power domain 3 (CORE domain, core power domain) in FIG. 1 as an example for illustration. Include the following steps:

Step S201, store a wake-up mode instruction in a wake-up mode register (WUR); the wake-up mode instruction carries wake-up source information and a power switch mode entered by the chip system after the chip system is woken up.

Among them, the CPU (central processing unit) in the power domain 3 (CORE domain, core power domain) is set with different registers, including a wake-up mode register (WUR, Wake Up Register), a power-down mode register (POFFR, Power OffRegister) and Power Off Enable Register (POER, Power Off Enable Register); the wake-up mode command refers to the command to convert the specified power domain from the low-power state to the normal working state; the power-down mode command refers to the conversion of the normal working state to the normal working state. The command of the low-power state; the power switch mode is a combination of power domain switch modes generated for the entire chip system under the premise of following certain principles.

In this embodiment, taking the chip system shown in FIG. 1 as an example, the following principles must be followed for the five power domains shown in FIG. 1 to be powered off and on:

1. The power supply of power domain 1 is always on and will not be powered off;

2. When power domain 3 is not powered off, power domain 2 cannot be powered off;

3. When power domain 3 is not powered off, power domain 4 and power domain 5 can independently choose to power off or not power off;

4. When power domain 3 is powered off, power domain 2 can choose to power off or not;

5. When power domain 3 is powered off, power domain 4 and power domain 5 must be powered off.

According to the principles described above, there are six power switch modes after the system is connected to the power supply, which are:

1. Normal working mode (SYSTEM ON), that is, all power domains are in normal working state, and no power domain is powered off;

2. FLASH OFF mode (FLASH OFF), that is, only power domain 5 is powered off, and other power domains are working normally;

3. Bluetooth off mode (BLE OFF), that is, only power domain 4 is powered off, and other power domains work normally;

4. FLASH & Bluetooth off mode (FLASH & BLE OFF), that is, power domain 4 and power domain 5 are powered off, and the rest of the power domains work normally;

5. Deep sleep mode (DEEP SLEEP), at this time, power domain 2, power domain 3, power domain 4, and power domain 5 are all powered off, and only power domain 1 works;

6. In SRAM RETENTION mode, power domain 3, power domain 4, and power domain 5 are powered off, and power domain 1 and power domain 2 work.

In a power-up or power-down process, the conversion relationship between various power switch modes is shown in the following table:

Table 1 Power switch mode conversion relationship

According to the above table (Table 1), there are a total of 26 conversion relationships between various power switch modes (the number marked with √ in the table), which can be simplified into the following 13 conversion relationships:

1. SYSTEM ON<-->BLE OFF;

2. SYSTEM ON<-->FLASH OFF;

3. SYSTEM ON<-->FLASH&BLE OFF;

4. SYSTEM ON<-->DEEP SLEEP;

5. SYSTEM ON<-->SRAM RETENTION;

6. BLE OFF<-->FLASH&BLE OFF;

7. BLE OFF<-->DEEP SLEEP;

8. BLE OFF<-->SRAM RETENTION;

9. FLASH OFF<-->FLASH&BLE OFF;

10. FLASH OFF<-->DEEP SLEEP;

11. FLASH OFF<-->SRAM RETENTION;

12. FLASH&BLE OFF<-->DEEP SLEEP;

13. FLASH&BLE OFF<-->SRAM RETENTION.

In addition, the chip power consumption optimization method can also preset wake-up source information. The wake-up source information includes an internal wake-up signal and an external wake-up signal. The internal wake-up signal can be a clock signal set regularly, and the external wake-up signal can be a chip wake-up caused by an external event. Operations, such as user triggering of external keys set by the chip system.

In this step, the CPU receives the wake-up mode command preset by the user and stores it in the wake-up mode register (WUR). The instruction corresponding to the mode is stored in the wake-up mode register (WUR).

Step S202, the power-down mode command is stored in the power-down mode register (POFFR).

Specifically, for example, the preset power-down mode instruction is to start power-down after a preset time period or start power-down under the action of a user-triggered signal, and enter the BLE OFF mode, then store the instruction in the power-down mode register (POFFR )middle.

Step S203, in response to the power-down mode command, trigger the power-down enable register (POER) to start the power-down process and control the power domain specified by the power-down mode command to enter the low power consumption mode in the power-down process.

Specifically, when the preset clock signal comes, or under the action of the user triggering the button, the power-down enable register is triggered, and the chip system starts the power-down process, and controls the corresponding power-down mode command according to the power-down process. For example, according to the BLE OFF mode in the power-down mode command, the power domain 4, that is, the Bluetooth power domain, is controlled to enter the low power consumption mode, that is, the power domain 4 is turned off.

Step S204, receiving a wake-up signal generated by a wake-up source corresponding to the wake-up source information;

Specifically, the chip receives a valid wake-up signal specified by the wake-up source information, such as an external wake-up signal or an internal wake-up signal specified by the wake-up source information. The internal wake-up signal can be a clock signal set regularly, and the external wake-up signal can be the chip wake-up caused by an external event. Operations, such as user triggering of external keys set by the chip system.

Step S205, if the wake-up signal is a valid wake-up signal, control the power domain specified by the wake-up mode command to enter the power switch mode.

Specifically, it is judged whether the current wake-up signal is a valid wake-up signal according to the wake-up source information preset in the wake-up mode command. If it is a valid wake-up signal, the chip system is controlled to enter the specified power supply according to the wake-up mode command pre-stored in the wake-up mode register (WUR). The switch mode, for example, if the pre-specified power switch mode is SYSTEM ON, the chip system will be woken up from the BLE OFF mode to the SYSTEM ON mode under the trigger of an effective wake-up signal.

In the above embodiment, by storing the wake-up mode command and the power-down mode command in the wake-up mode register and the power-down mode register, respectively, in response to the power-down mode command, the power-down enable register is triggered to start the power-down process and the power-down process is executed. Control the power domain specified by the above power-down mode command to enter the low power consumption mode; receive the wake-up signal generated by the wake-up source corresponding to the above-mentioned wake-up source information; if the wake-up signal is a valid wake-up signal, control the wake-up mode specified by the above. The power domain enters the power switch mode described above. The chip power consumption optimization method pre-stores the corresponding wake-up mode command or power-down mode command through a preset register, enters the corresponding low-power mode under the trigger of the power-down mode command, and executes the specified wake-up signal and wake-up mode command. It enters the corresponding power switch mode under the trigger of the device, completes the automatic management process of chip power consumption optimization, reduces chip power consumption, and saves power resources.

In one embodiment, the chip system includes a plurality of power domains; a level shifter or an isolation unit is arranged between each power domain; wherein the absolute value of the difference between the power supply voltages of the two power domains is greater than a preset value , and there is digital signal communication between the two power domains, a level converter is provided between the two power domains; there is digital signal communication between the two power domains, and one of the two power domains is powered down and the other In the case of no power failure, an isolation unit is provided between the two power domains.

Specifically, the chip system includes multiple power domains. For example, the chip system shown in FIG. 1 has 5 power domains. Since the power supply voltages between some power domains are significantly different, there are also signal connections between them, and there are signal connections between them. There may be a situation in which one of the two power domains is powered down and the other is not powered down, so a Level Shifter and an Isolation Cell need to be used between the power domains. The principle followed when inserting Level Shifter and IsolationCell is: Assume that the two power domains with signal connections are power domain A and power domain B. If there is a significant difference between the power supply voltages of power domain A and power domain B, the connected The signal needs to insert a Level Shifter between the two power domains; if there is a situation where power domain A is powered off but power domain B is not powered off, the signal output from power domain A to power domain B must be between the two power domains Insert Isolation Cell and vice versa.

As shown in Figure 1, according to the principle of inserting Level Shifter and Isolation Cell described above, since the power supply voltage of power domain 1 is significantly higher than that of the other three power domains, and power domain 1 and power domain 3 are only connected Signal connection, so the signal connecting power domain 1 and power domain 3 needs to insert a level shifter (Level Shifter) between the two power domains; in addition, power domain 1 is normally open, so there is a power failure in power domain 3. When the power domain 1 is working normally, the signal output from the power domain 3 to the power domain 1 needs to be inserted into the isolation unit (IsolationCell) between the two power domains, and the signal output from the power domain 1 to the power domain 3 does not need to be inserted into the Isolation Cell. Cell. The power supply voltages of power domain 2, power domain 3, power domain 4, and power domain 5 are the same or similar, so the signal transmission between these three power domains does not require LevelShifter. Power domain 2 only has signal connection with power domain 3. According to the above six power switch modes, there is a situation where power domain 3 is powered off but power domain 2 is not powered off (SRAM RETENTION), so power domain 3 outputs to power domain 2. If the signal is normal, the Isolation Cell should be inserted, but before entering the SRAM RETENTION, the CPU will set the SRAM in the power domain 2 to the retention mode. When the system enters the SRAM RETENTION, only the SRAM itself has power supply in the power domain 2. , other logic circuits are not powered, and the signal output from power domain 3 to power domain 2 is only connected to the logic circuit, not to the SRAM itself, so the signal output from power domain 3 to power domain 2 does not need to be inserted into the Isolation Cell; There is a situation in which power domain 2 is powered off but power domain 3 is not powered off. Therefore, the signal output from power domain 2 to power domain 3 does not need to be inserted into the Isolation Cell. Power domain 4 only has signal connection with power domain 3. According to the above six power switch modes, there is a situation where power domain 4 is powered off but power domain 3 is not powered off. Therefore, the signal output from power domain 4 to power domain 3 needs to be placed here. An Isolation Cell is inserted between the two power domains; since there is no situation where the power domain 3 is powered off but the power domain 4 is not powered off, the signal output from the power domain 3 to the power domain 4 does not need to be inserted into the Isolation Cell. Power domain 5 is the same as power domain 4, and the signal output from power domain 5 to power domain 3 also needs to be inserted between the two power domains.

In the above-mentioned embodiment, by setting certain principles and inserting level converters or isolation units between the corresponding power domains, it is ensured that different power domains can work together, so as not to cause one power domain to be powered down and the other to be associated. Power domains also don't work properly.

In one embodiment, the above step S203 includes: according to the power-down mode command, triggering the power-down enable register (POER) to send a power-down enable signal to the power domain specified by the power-down mode command, so that the power-down mode command The clock signal of the specified power domain is turned off; in response to the clock signal being turned off, the reset of the power domain specified by the power-down mode command is triggered; the isolation unit corresponding to the power domain specified by the power-down mode command after reset is enabled and reset The voltage controller corresponding to the power domain specified by the power-down mode command is turned off.

Specifically, according to the power switch mode entered after the power down set in step S202, the CPU firstly turns off the clocks of the power domains that need to be powered off, then resets these power domains, then enables the relevant isolation cells, and finally Turn off the voltage controllers in power domain 1 corresponding to these power domains to power off the power domain that needs to be powered off.

In the above-mentioned embodiment, the power-down process of the power domain is completed in an orderly manner, and the power consumption of the chip is reduced by sequentially controlling the clock shutdown, power-domain reset, isolation unit enable, and voltage controller shutdown of the power-supply domain that needs to be powered down in the power-down process. At the same time, ensure that other power domains work normally.

In one embodiment, the above step S205 includes: according to a valid wake-up signal, turning on the voltage controller corresponding to the power domain specified by the wake-up mode command, and de-resetting the power domain specified by the wake-up mode command; The isolation unit corresponding to the power domain specified by the wake-up mode command is disabled; the clock signal corresponding to the power domain specified by the wake-up mode command is restarted.

Specifically, when the required wake-up signal is valid, the CPU first turns on the voltage controller in the power domain 1 corresponding to the power domain that needs to be powered on according to the power switch mode entered by the system after the wake-up set in step S201, and secondly turns on the voltage controller in the power domain 1 corresponding to the power domain to be powered on. De-enable the relevant isolation cell, then de-reset these power domains, and finally turn on the clock of the power domain that needs to be powered on, so that the power domain that needs to be powered on resumes normal operation.

In the above embodiment, the wake-up process of the power domain is completed by sequentially turning on the voltage controller of the power domain that needs to be powered on, disabling the relevant isolation unit, de-resetting the power domain, and turning on the clock in the wake-up process. The power domain is functioning normally.

In one embodiment, as shown in FIG. 3 , the chip system includes a normally-on power supply domain and a flip-flop; the above-mentioned chip power consumption optimization method further includes:

In the case that the wake-up source information is invalid internal wake-up signal, if the power-down mode command includes one of deep sleep mode or static memory retention mode, the clock signal of the normally-on power domain is triggered by a trigger to turn off.

Specifically, in order to turn off the clock of power domain 1 when the system is in deep sleep mode DEEP SLEEP or static memory retention mode SRAM RETENTION, and turn on the clock of power domain 1 when the external wake-up is valid, it is necessary to use a D with an asynchronous reset terminal. trigger, as shown in Figure 3. The D terminal of this D flip-flop is connected to logic 1; the CLK terminal is connected (!int_wu_en&&system_off_flag); the Q terminal is connected to an inverter, and the signal after the inversion is the enable signal aon_clk_en of aon_clk; the RESET terminal is connected to the external wake-up signal ext_wake_up. Among them, int_wu_en is the internal wake-up enable signal. When the internal wake-up is enabled, the signal is 1; system_off_flag is a pulse signal. When the system enters DEEPSLEEP or SRAM RETENTION, the system_off_flag signal will generate a pulse. If the internal wake-up is not enabled at this time, that is, int_wu_en is 0, then the CLK terminal of the D flip-flop receives a pulse, and the value of the Q terminal becomes 1. After passing through the inverter, the generated aon_clk_en becomes 0, the enable signal of aon_clk becomes 0, and aon_clk is turned off.

In the above embodiment, the clock signal of the power domain 1 (normally open power domain) is controlled by the D flip-flop, and when the chip system is in the deep sleep mode DEEP SLEEP or the static memory retention mode SRAM RETENTION, the clock of the power domain 1 is turned off, which further saves the energy consumption. system power consumption.

In an embodiment, after the above-mentioned triggering the triggering of the clock signal of the normally-on power domain to be turned off by the trigger, the chip power consumption optimization method further includes:

When the wake-up source information is that the internal wake-up signal is invalid and the external wake-up signal is valid, the reset trigger generates a clock enable signal and sends it to the normally-on power domain, so that the normally-on power domain restarts the clock signal.

Specifically, after the clock signal of the above-mentioned normally-on power domain, that is, the power domain 1, is turned off, when the external wake-up signal (ext_wake_up) is valid, the D flip-flop is reset, and the output value of the Q terminal becomes 0. After the inverter After that, the generated aon_clk_en becomes 1, aon_clk is enabled, and normal operation is resumed.

In the above embodiment, the reset of the D flip-flop is triggered by an external wake-up signal, so that the clock signal of power domain 1 is turned on, and the chip system resumes normal operation, which is convenient for the chip system to pass the external wake-up signal when the chip system is in the deep sleep mode DEEP SLEEP or the static memory retention mode SRAM RETENTION. wake.

In one embodiment, the chip system includes a software wakeup register (SWUR, Software Wake UpRegister); the chip power consumption optimization method further includes:

When the low power consumption mode is one of flash off mode, bluetooth off mode or flash and bluetooth off mode, the effective wake-up signal is used as a software wake-up command and stored in the software wake-up register (SWUR); according to the software wake-up command, the software The voltage controller corresponding to the power domain specified by the wake-up command is turned on; the power domain specified by the software wake-up command is the flash power domain or the Bluetooth power domain; unreset the power domain specified by the software wake-up command; The isolation unit corresponding to the power supply domain is disabled; restart the clock signal corresponding to the power supply domain specified by the software wake-up command.

Specifically, when one or more power domains are in a power-down state, the system waits for the arrival of a wake-up signal. If you want to use the internal wake-up, the CPU needs to set the target count value of the wake-up counter in addition to enabling the internal wake-up. When the internal wake-up is enabled and the system enters a low power switch mode (one of the three power switch modes of BLE OFF, DEEP SLEEP, and SRAM RETENTION), the wake-up counter starts counting from 0, and when the wake-up counter count value reaches the set target count value When the internal wake-up signal is generated, one or some power domains in the power-down state of the system can be woken up and entered into the set power switch mode after wake-up. If you want to use external wake-up, after the system enters the low power switch mode, the state machine AON_FSM waits for the wake-up signal input from the external pin. When the external wake-up signal is valid, you can wake up one or some power domains in the power-down state of the system. Enter the set power switch mode after wake-up. If the system wakes up from the BLE OFF, FLASHOFF or FLASH&BLE OFF state, since the CPU is working normally at this time, the software wake-up method can also be used. The specific method is to configure the software wake-up register (SWUR) for the CPU to be a valid value to generate a software wake-up. signal to wake up power domain 4 or power domain 5. During the wake-up process, firstly turn on the voltage controller in the power domain 1 corresponding to the power domain that needs to be powered on, then de-reset these power domains, and finally disable the related isolation cell, so that the power domain that needs to be powered on returns to normal Work.

In the above embodiment, by setting the software wake-up register, the software wake-up method can be used when the system wakes up from the BLE OFF, FLASH OFF or FLASH&BLE OFF state, which is more concise and efficient.

As shown in FIG. 4, FIG. 4 is a schematic diagram of a power-down process and a power-up process in an embodiment:

The power-down and power-up procedures of each power domain are controlled by the state machine (AON_FSM) in the AON in the power domain 1, and the state machine is located in the AON Logic in Figure 1. The control flow is shown in Figure 2.

When the chip is not connected to the power supply, the state machine is in the reset state, waiting for power-on. When the chip is powered on for the first time, first, the state machine turns on the power domain 2 voltage controller, power domain 3 voltage controller, power domain 4 voltage controller, and power domain 5 voltage controller in power domain 1, respectively. These four power domains supply power;

Secondly, the state machine releases the reset signals of power domain 2, power domain 3, power domain 4, and power domain 5;

After that, the state machine disables the Isolation Cell between the power domains (the Isolation Cell is in the enabled state when it is not powered on);

Finally, the system enters the normal working mode (SYSTEM ON).

When some power domains do not need to work, they can be powered off. The CPU first configures the wake-up mode register (WUR) in advance to set the wake-up source and the power switch mode that the system enters after wake-up. The wake-up source can select internal wake-up and external wake-up. If the external wake-up is enabled but the internal wake-up is not enabled, when the system is in DEEP SLEEP or SRAMRETENTION, the clock (aon_clk) of power domain 1 will be turned off; if the internal wake-up is enabled, the system needs to pass the clock in power domain 1 The wake-up counter (wake_counter) performs internal wake-up, so aon_clk cannot be turned off at this time. The CPU can configure the power-down mode register (POFFR) to select the power switch mode entered after power-down. The CPU starts the power-down process by configuring the power-down enable register (POER).

In the power-down process, first shut down the clock of the power domain to be powered down,

Second, reset the power domain to be powered down,

Then enable the related Isolation Cell,

Finally, turn off the voltage controller in power domain 1 corresponding to the power domain to be powered off.

In a specific scenario, for example, when the power switch mode transition from SYSTEM ON->BLE OFF->SYSTEM ON needs to be completed and an external wake-up is used, the operation steps are as follows:

Step 1. The CPU configures the wake-up mode register (WUR), sets the wake-up source as the external wake-up source, and sets the power switch mode that the system enters after wake-up to SYSTEM ON;

Step 2. The CPU configures the power-down mode register (POFFR), and selects the power switch mode entered after power-down as BLE OFF;

Step 3. The CPU starts the power-down process by configuring the power-down enable register (POER);

Step 4. The hardware turns off the clock of power domain 4, then resets power domain 4, then enables the isolation cell between power domain 4 and power domain 3, and finally controls the voltage in power domain 1 corresponding to power domain 4. shuts down the power supply domain 4;

Step 5. The hardware waits for the arrival of the external wake-up signal;

Step 6. When the external wake-up signal is valid, the voltage controller in the power domain 1 corresponding to the hardware power domain 4 is turned on, then the Isolation cell is disabled, then the power domain 4 is de-reset, and finally the clock of the power domain 4 is turned on. Return power domain 4 to normal operation.

The chip power consumption optimization method in the above-mentioned embodiment pre-stores the corresponding wake-up mode command or power-down mode command through a preset register, enters the corresponding low-power consumption mode under the trigger of the power-down mode command, and executes a specified wake-up signal. The corresponding power switch mode is entered under the trigger of the wake-up mode command, which completes the automatic management process of chip power consumption optimization, reduces chip power consumption, and saves power resources.

It should be understood that although the steps in the flowcharts of FIGS. 1-4 are shown in sequence according to the arrows, these steps are not necessarily executed in the sequence shown by the arrows. Unless explicitly stated herein, the execution of these steps is not strictly limited to the order, and these steps may be performed in other orders. Moreover, at least a part of the steps in FIGS. 1-4 may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but may be executed at different times. The execution of these steps or stages The order is also not necessarily sequential, but may be performed alternately or alternately with other steps or at least a portion of the steps or phases within the other steps.

In one embodiment, as shown in FIG. 5, an apparatus 500 for optimizing chip power consumption is provided, including: a wake-up mode command storage module 501, a power-down mode command storage module 502, a power-domain power-down module 503, a wake-up signal receiving module Module 504 and Power Domain Wake Module 505, where:

The wake-up mode command storage module 501 is used for storing the wake-up mode command in the wake-up mode register; the wake-up mode command carries the wake-up source information and the power switch mode entered by the chip system after the chip system is woken up.

The power-down mode instruction storage module 502 is used for storing the power-down mode instruction in the power-down mode register;

The power domain power-down module 503 is configured to, in response to the power-down mode command, trigger the power-down enable register to start a power-down process, and control the power domain specified by the power-down mode command to enter a low state during the power-down process in power mode;

A wake-up signal receiving module 504, configured to receive a wake-up signal generated by a wake-up source corresponding to the wake-up source information;

The power domain wake-up module 505 is configured to control the power domain specified by the wake-up mode instruction to enter the power switch mode if the wake-up signal is a valid wake-up signal.

In one embodiment, the chip system includes a plurality of power domains; a level shifter or an isolation unit is arranged between each power domain; wherein,

When the absolute value of the difference between the respective power supply voltages of the two power supply domains is greater than a preset value, and there is digital signal communication between the two power supply domains, the level converter is provided between the two power supply domains;

The isolation unit is provided between the two power domains when there is digital signal communication between the two power domains, and one of the two power domains is powered down and the other is not powered off.

In one embodiment, the power domain power down module 503 is further configured to:

According to the power-down mode command, the power-down enable register (POER) is triggered to send a power-down enable signal to the power domain specified by the power-down mode command, so that the power domain specified by the power-down mode command is enabled The clock signal is turned off;

triggering a reset of the power domain specified by the power-down mode instruction in response to the clock signal being turned off;

The isolation unit corresponding to the power domain specified by the power-down mode command after reset is enabled, and the voltage controller corresponding to the power domain specified by the power-down mode command after the reset is turned off.

In one embodiment, the above-mentioned power domain wake-up module 505 is further configured to:

According to the valid wake-up signal, turn on the voltage controller corresponding to the power domain specified by the wake-up mode command, and de-reset the power domain specified by the wake-up mode command;

disabling the isolation unit corresponding to the power supply domain specified by the wake-up mode command after de-resetting;

Restart the clock signal corresponding to the power domain specified by the wake-up mode instruction.

In one embodiment, the above-mentioned chip system includes a normally-on power supply domain and a flip-flop; the above-mentioned method further includes:

When the wake-up source information is an invalid internal wake-up signal, if the power-down mode command includes one of deep-sleep mode or static memory retention mode, the trigger is used to trigger the clock signal of the normally-on power domain. closure.

In an embodiment, after the triggering of the trigger by the trigger to turn off the clock signal of the normally-on power domain, the method further includes:

When the wake-up source information is that the internal wake-up signal is invalid and the external wake-up signal is valid, the flip-flop triggered to reset generates a clock enable signal and sends it to the normally-on power domain, so that the normally-on power domain Restart the clock signal.

In one embodiment, the chip system includes a software wake-up register (SWUR); the method further includes:

When the low power consumption mode is one of flash off mode, bluetooth off mode or flash and bluetooth off mode simultaneously, use the valid wake-up signal as a software wake-up command and store it in the software wake-up register (SWUR);

According to the software wake-up command, the voltage controller corresponding to the power domain specified by the software wake-up command is turned on; the power domain specified by the software wake-up command is a flash power domain or a Bluetooth power domain;

De-reset the power domain specified by the software wake-up instruction;

disabling the isolation unit corresponding to the power supply domain specified by the software wake-up command after de-resetting;

Restart the clock signal corresponding to the power domain specified by the software wake-up instruction.

For the specific limitation of the device for optimizing the power consumption of a chip, reference may be made to the limitation of the method for optimizing the power consumption of the chip above, which will not be repeated here. Each module in the above-mentioned device for optimizing chip power consumption may be implemented in whole or in part by software, hardware, and combinations thereof. The above modules can be embedded in or independent of the processor in the computer device in the form of hardware, or stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

In one embodiment, a computer device is provided, the internal structure of which can be shown in FIG. 6 . The computer device includes a processor, memory, and a network interface connected by a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium, an internal memory. The nonvolatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the execution of the operating system and computer programs in the non-volatile storage medium. The database of the computer device is used to store wake-up mode command or power-down mode command data. The network interface of the computer device is used to communicate with an external terminal through a network connection. The computer program, when executed by the processor, implements a chip power consumption optimization method.

Those skilled in the art can understand that the structure shown in FIG. 6 is only a block diagram of a partial structure related to the solution of the present application, and does not constitute a limitation on the computer equipment to which the solution of the present application is applied. Include more or fewer components than shown in the figures, or combine certain components, or have a different arrangement of components.

In one embodiment, a computer device is provided, including a memory and a processor, where a computer program is stored in the memory, and the processor implements the steps in the foregoing method embodiments when the processor executes the computer program.

In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the steps in the foregoing method embodiments are implemented.

Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be implemented by instructing relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage In the medium, when the computer program is executed, it may include the processes of the above-mentioned method embodiments. Wherein, any reference to memory, storage, database or other media used in the various embodiments provided in this application may include at least one of non-volatile and volatile memory. The non-volatile memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash memory or optical memory, and the like. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, the RAM may be in various forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM).

The technical features of the above embodiments can be combined arbitrarily. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features It is considered to be the range described in this specification.

The above-mentioned embodiments only represent several embodiments of the present application, and the descriptions thereof are specific and detailed, but should not be construed as a limitation on the scope of the invention patent. It should be pointed out that for those skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the scope of protection of the patent of the present application shall be subject to the appended claims.

Claims (10)

1. A method for optimizing chip power consumption, the method comprising:

storing the wake mode instruction in a wake mode register; the awakening mode instruction carries awakening source information and a power switch mode which is entered by the chip system after the chip system is awakened;

storing the power down mode instruction in a power down mode register;

responding to the power-down mode instruction, triggering a power-down enabling register to start a power-down process and controlling a power domain specified by the power-down mode instruction to enter a low-power-consumption mode in the power-down process; the method specifically comprises the following steps: triggering the power-down enabling register to send a power-down enabling signal to a power domain specified by the power-down mode instruction according to the power-down mode instruction, so that a clock signal of the power domain specified by the power-down mode instruction is turned off; triggering power domain reset designated by the power down mode instruction in response to the clock signal being turned off; enabling an isolation unit corresponding to the reset power domain specified by the power down mode instruction, and closing a voltage controller corresponding to the reset power domain specified by the power down mode instruction;

receiving a wake-up signal generated by a wake-up source corresponding to the wake-up source information;

and if the wake-up signal is an effective wake-up signal, controlling a power domain specified by the wake-up mode instruction to enter the power switch mode.

2. The method of claim 1, wherein the system-on-a-chip comprises a plurality of power domains; level converters or isolation units are arranged between every two power domains; wherein,

the absolute value of the difference value of the respective power supply voltages of the two power domains is larger than a preset value, and the level converter is arranged between the two power domains under the condition that digital signal communication exists between the two power domains;

digital signal communication is arranged between the two power domains, and the isolation unit is arranged between the two power domains under the condition that one power domain is powered down and the other power domain is not powered down.

3. The method of claim 2, wherein the plurality of power domains comprises a normally-on power domain, a static memory power domain, a core power domain, a bluetooth power domain, and a flash power domain.

4. The method of claim 2, wherein the controlling the power domain specified by the wake mode instruction to enter the power switch mode comprises:

according to the effective wake-up signal, a voltage controller corresponding to the power domain specified by the wake-up mode instruction is turned on, and the power domain specified by the wake-up mode instruction is reset;

disabling the isolation unit corresponding to the power domain specified by the wake mode instruction after the reset is released;

restarting the clock signal corresponding to the power domain specified by the wake-up mode instruction.

5. The method of claim 1, wherein the system-on-a-chip comprises a normally-on power domain and a flip-flop; the method further comprises the following steps:

and under the condition that the awakening source information is invalid, if the power-down mode instruction comprises one of a deep sleep mode or a static memory retention mode, triggering the clock signal of the normally-open power domain to be closed through the trigger.

6. The method of claim 5, wherein after the clock signal triggering the normally-open power domain by the flip-flop is turned off, the method further comprises:

and under the condition that the awakening source information is that the internal awakening signal is invalid and the external awakening signal is valid, the triggered and reset trigger generates a clock enabling signal and sends the clock enabling signal to the normally open power domain so as to enable the normally open power domain to restart the clock signal.

7. The method of claim 2, wherein the system-on-a-chip comprises a software wake-up register; the method further comprises the following steps:

when the low power consumption mode is one of a flash memory closing mode, a Bluetooth closing mode or a flash memory and Bluetooth simultaneous closing mode, taking the effective wake-up signal as a software wake-up instruction and storing the effective wake-up instruction in the software wake-up register;

according to the software awakening instruction, a voltage controller corresponding to a power domain specified by the software awakening instruction is turned on; the power domain designated by the software awakening instruction is a flash memory power domain or a Bluetooth power domain;

resetting a power domain specified by the software wake-up instruction;

enabling the isolation unit corresponding to the power domain appointed by the software awakening instruction after the software awakening instruction is reset;

and restarting a clock signal corresponding to the power domain specified by the software wake-up instruction.

8. An apparatus for optimizing power consumption of a chip, the apparatus comprising:

the wake-up mode instruction storage module is used for storing the wake-up mode instruction in a wake-up mode register; the awakening mode instruction carries awakening source information and a power switch mode which is entered by the chip system after the chip system is awakened;

the power-down mode instruction storage module is used for storing the power-down mode instruction in a power-down mode register;

the power domain power-down module is used for responding to the power-down mode instruction, triggering a power-down enabling register to start a power-down flow and controlling a power domain specified by the power-down mode instruction to enter a low-power-consumption mode in the power-down flow; the method specifically comprises the following steps: triggering the power-down enabling register to send a power-down enabling signal to a power domain specified by the power-down mode instruction according to the power-down mode instruction, so that a clock signal of the power domain specified by the power-down mode instruction is turned off; triggering power domain reset designated by the power down mode instruction in response to the clock signal being turned off; enabling an isolation unit corresponding to the reset power domain specified by the power down mode instruction, and closing a voltage controller corresponding to the reset power domain specified by the power down mode instruction;

the wake-up signal receiving module is used for receiving wake-up signals generated by a wake-up source corresponding to the wake-up source information;

and the power domain awakening module is used for controlling the power domain appointed by the awakening mode instruction to enter the power switch mode if the awakening signal is an effective awakening signal.

9. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor, when executing the computer program, implements the steps of the method of any of claims 1 to 7.

10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 7.

Images