CN109613970B - Low-power-consumption processing method based on FPGA and DSP framework - Google Patents
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Abstract
The invention relates to a low-power-consumption processing method based on an FPGA (field programmable gate array) and a DSP (digital signal processor) framework, belonging to the technical field of digital signal processing. The method comprises the following steps: after the system is powered on and started, the FPGA completes self configuration and the DSP completes initialization, and the FPGA and the DSP are in a low-power-consumption working mode; when the DSP receives external data, the low power consumption mode is interrupted, and the normal working mode is jumped to; when the DSP detects an external normal working instruction, the FPGA is controlled to jump to a normal working mode to complete normal time sequence work; after the normal time sequence work is finished, the FPGA enters a low-power-consumption working mode according to the external control of the DSP or automatically. The invention effectively solves or relieves the problems of unstable work and high consumption of the system caused by high power consumption of the FPGA and the DSP.
Description
Technical Field
The invention relates to the technical field of digital signal processing, in particular to a low-power-consumption processing method based on an FPGA (field programmable gate array) and a DSP (digital signal processor) framework.
Background
In the current signal processing design, the processing mode based on the FPGA and DSP framework is widely applied to the fields of communication, computers, electronics and the like. The processing equipment with the FPGA and the DSP can meet various application systems with large data volume, complex operation and high real-time requirement.
With the development of signal processing systems, the complexity of equipment is continuously improved, and the power consumption and heat consumption in a chip are increased. Too high power consumption mainly causes two problems: firstly, the heat dissipation is increased rapidly, and secondly, the energy of the equipment is consumed rapidly. The untimely heat dissipation or the temperature exceeding the required temperature of the chip may cause unstable operation of the chip, and even damage to the chip, and the rapid energy consumption is also an important factor affecting the usage of the device. Therefore, it is a very troublesome problem to reduce the power consumption of the device and to satisfy the usage conditions of the device.
When the existing system works, the DSP and the FPGA are in a normal working state for a long time, a large amount of heat consumption is generated inside a chip, power consumption and heat consumption pressure are brought to the whole equipment, and particularly when the equipment is subjected to a high-temperature test, the high-temperature problem of the chip is obvious.
Disclosure of Invention
In view of the above analysis, the present invention aims to provide a low power consumption processing method based on FPGA and DSP architecture, which effectively solves the problem of unstable operation and high consumption of the system caused by high power consumption of FPGA and DSP in the existing method.
The purpose of the invention is mainly realized by the following technical scheme:
the invention provides a low-power consumption processing method based on an FPGA (field programmable gate array) and a DSP (digital signal processor) framework, which comprises the following steps of: after the system is powered on and started, the FPGA completes self configuration and the DSP completes initialization, and the FPGA and the DSP are in a low-power-consumption working mode; when the DSP receives external data, the low power consumption mode is interrupted, and the normal working mode is jumped to; when the DSP detects an external normal working instruction, the FPGA is controlled to jump to a normal working mode to complete normal time sequence work; after the normal time sequence work is finished, the FPGA enters a low-power-consumption working mode according to the external control of the DSP or automatically.
Preferably, the FPGA completing self-configuration and DSP completing initialization includes: after the FPGA is electrified, a static area is configured, and the reconfigurable area is configured into a low-power-consumption module; the external pin of the DSP is initialized to be a low-power-consumption interrupt response port.
Preferably, the code modules of the FPGA include a static configuration file, a low-power consumption reconfigurable file, and a normal operation reconfigurable file.
Preferably, after the FPGA is powered on, the static configuration file is loaded for the first time to configure the static region, and the reconfigurable region is configured as the low power consumption module at a time through an ICAP protocol according to the low power consumption reconfigurable file.
Preferably, the initializing of the external pin of the DSP to the low power consumption interrupt response port includes: before the low-power-consumption working state, the external pin of the DSP is initialized to be a low-power-consumption awakening pin for low-power-consumption awakening, and the external pin of the DSP uses the same external input data.
Preferably, after the low power consumption wake-up, the external pin of the DSP is initialized to a reusable communication pin, and receives an external control instruction using the reusable communication pin.
Preferably, an external pin of the DSP is connected to an external serial port simulator, and the external pin of the DSP is pulled down by sending any data through the external serial port to activate the DSP to initialize the DSP as a reusable communication pin.
Preferably, when the DSP detects an external normal operation instruction, controlling the FPGA to jump to the normal operation mode includes: and when the DSP receives an external control instruction of normal work, the FPGA carries out secondary configuration dynamic reconfiguration on the reconfigurable area through ICAP (independent component analysis protocol) control according to the normal work reconfigurable file to form a normal work module.
Preferably, the entering of the FPGA into the low power consumption operating mode according to the external control of the DSP includes: and the FPGA carries out three times of configuration and dynamic reconfiguration on the reconfigurable area to form a low-power-consumption module.
Preferably, the automatic entry of the FPGA into the low power consumption operating mode includes: and receiving external control through a static logic area of the FPGA, and realizing low power consumption control by a way of awakening the DSP by FPGA master control.
The technical scheme has the beneficial effects that: the invention discloses a low-power consumption processing method based on an FPGA and a DSP framework, which comprises the following steps: after the system is powered on and started, the FPGA completes self configuration and the DSP completes initialization, and the FPGA and the DSP are in a low-power-consumption working mode; when the DSP receives external data, the low power consumption mode is interrupted, and the normal working mode is jumped to; when the DSP detects an external normal working instruction, the FPGA is controlled to jump to a normal working mode to complete normal time sequence work; after the normal time sequence work is finished, the FPGA enters a low-power-consumption working mode according to the external control of the DSP or automatically. The processing mode based on the FPGA and the DSP as the framework greatly reduces the generation of power consumption, improves the stability of the system, and effectively solves or relieves the problems of unstable work and high consumption possibly brought by the high power consumption of the FPGA and the DSP to the work of the system by adopting a mode of time-sharing processing with high power consumption and low power consumption.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
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The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention, wherein like reference numerals are used to designate like parts throughout.
FIG. 1 is a flow chart of a low power consumption processing method based on FPGA and DSP architecture according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the system operation based on the FPGA and DSP architecture according to the embodiment of the present invention;
FIG. 3 is a flow chart of the DSP according to the embodiment of the present invention;
FIG. 4 is a schematic diagram of an FPGA of an embodiment of the present invention;
fig. 5 is a schematic diagram of FPGA dynamic reconfiguration according to an embodiment of the present invention.
Detailed Description
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate preferred embodiments of the invention and together with the description, serve to explain the principles of the invention and not to limit the scope of the invention.
According to a specific embodiment of the present invention, as shown in fig. 1, a low power consumption processing method based on FPGA and DSP architecture is disclosed, which includes the following steps:
s101, after the system is powered on and started, the FPGA completes self configuration and the DSP completes initialization, and the FPGA and the DSP are in a low-power-consumption working mode;
s102, when the DSP receives external data, interrupting the low power consumption mode and jumping to a normal working mode;
s103, when the DSP detects an external normal working instruction, the FPGA is controlled to jump to a normal working mode to complete normal time sequence work;
and S104, after the normal time sequence work is finished, the FPGA automatically enters a low-power-consumption working mode according to the external control of the DSP.
As shown in fig. 1, the low power consumption processing method based on the FPGA and DSP architecture according to the embodiment of the present invention includes that after the system is powered on and started, the FPGA completes its configuration and the DSP completes initialization, and the FPGA is in a low power consumption operating mode; when the DSP detects an external control instruction, the FPGA jumps to a normal working mode to complete normal time sequence work; after the normal time sequence work is finished, the FPGA enters a low-power-consumption working mode according to the external control of the DSP or automatically. The embodiment of the invention solves the problems that when the existing system works, the DSP and the FPGA are in a normal working state for a long time, a large amount of heat consumption is generated in the chip, and the whole equipment is subjected to power consumption and heat consumption pressure, and particularly when the equipment is subjected to a high-temperature test, the high-temperature problem of the chip is obvious. The invention adopts a mode of processing the high-power-consumption working mode and the low-power-consumption working mode in different periods, and can effectively solve or alleviate the problems.
That is, the complete working flow of the system based on the FPGA and DSP architecture shown in fig. 2 is as follows:
a. and when the power is on and started, the DSP and the FPGA respectively complete self configuration and initialization.
b. After initialization is completed, the DSP and the FPGA are in a low power consumption mode state respectively.
c. And (5) waiting for external control in real time, and when a working instruction is detected, skipping the DSP and the FPGA to a normal working mode.
d. And in a normal working mode, completing relevant operations required by the system.
e. After the normal work is finished, the low power consumption mode can be entered again according to an external control system or automatically.
FIG. 3 is a flow chart of the DSP operation of the present invention.
FIG. 4 is a schematic diagram of the FPGA of the present invention.
In a specific embodiment of the present invention, as shown in fig. 3 and 4, the FPGA completing self configuration and the DSP completing initialization includes: after the FPGA is electrified, a static area is configured, and the reconfigurable area is configured into a low-power-consumption module; the external pin of the DSP is initialized to be a low-power-consumption interrupt response port. That is, the system based on the FPGA and the DSP architecture is powered on for the first time to complete configuration and initialization, so that the DSP and the FPGA are in a low power consumption mode state respectively.
In a specific embodiment of the present invention, the code modules of the FPGA include a static configuration file, a low power consumption reconfigurable file, and a normal operation reconfigurable file. Referring to fig. 4, the FPGA is modularly designed during design, and the code module divides a static configuration file, a low power consumption reconfigurable file, and a normal operation reconfigurable file, which correspond to the files of the static control, the low power consumption operation state, and the normal operation state, respectively.
According to a specific embodiment of the invention, after the FPGA is powered on, the static configuration file is loaded for the first time to configure the static region, and the reconfigurable region is configured into the low-power-consumption module at one time through an ICAP (independent component analysis protocol) according to the low-power-consumption reconfigurable file. Referring to fig. 4, specifically, the static configuration file is loaded to configure the static area for the first power-on configuration, and then the low-power-consumption reconfigurable file is loaded to complete the control of the low-power-consumption work through the ICAP protocol.
In a specific embodiment of the present invention, initializing an external pin of the DSP to a low power consumption interrupt response port includes: before the low-power-consumption working state, the external pin of the DSP is initialized to be a low-power-consumption awakening pin for low-power-consumption awakening, and the external pin of the DSP uses the same external input data.
It should be noted that, when the DSP multiplexing pin is used to perform low power consumption wake-up, the external control pin of the DSP may use data of the same external input source.
In a specific embodiment of the present invention, after the low power consumption wake-up, the external pin of the DSP is initialized to the reusable communication pin, and the reusable communication pin is used to receive the external control instruction.
It should be noted that, before the DSP enters low power consumption, its external pin is initialized to the low power consumption wake-up pin, and after the device wakes up, its external pin is initialized to the reusable communication pin and is used to receive external control instruction data. The embodiment of the invention uses the reusable configuration of the external serial port of the DSP, and other communication ports which can be configured by the DSP can also be adopted for control in practical engineering.
According to a specific embodiment of the invention, the external pin of the DSP is connected with an external serial port simulator, and any data is sent through the external serial port to pull down the external pin of the DSP so as to activate the DSP to initialize the DSP as a reusable communication pin.
It should be noted that, during the hardware design, the external pin GPIO11 (reusable as SCIRXDB) of the DSP may be connected to the external serial port simulator. The DSP can be activated only by pulling down the GPIO11 pin from the outside, because the pin is connected to the serial port on the hardware, the pin can be pulled down when any data is sent through the serial port, and the purpose of activating the DSP is achieved.
In a specific embodiment of the present invention, when the DSP detects an external normal operation instruction, controlling the FPGA to jump to the normal operation mode includes: and when the DSP receives an external control instruction of normal work, the FPGA carries out secondary configuration dynamic reconfiguration on the reconfigurable area through ICAP (independent component analysis protocol) control according to the normal work reconfigurable file to form a normal work module. That is to say, when the FPGA normally works, the reconfigurable area is reconfigured by the ICAP, so that the reconfigurable file that normally works is intermittently used, and the purpose of low power consumption of the system can be achieved.
The following description is made of the low-power processing procedure of the DSP and the low-power processing procedure of the FPGA, respectively:
in practical applications, a digital signal processor DSP is usually adopted, and other digital signal processors with low power consumption modes such as an MCU, an ARM, etc. may also be adopted, that is, many digital signal processors (MCU, ARM, DSP) have low power consumption modes. Specifically, taking DSP28335 as an example, the low power consumption processing of the whole processing system is guided by the characteristics of fast wake-up response time with low power consumption of DSP, multiplexing of external pins, and the like, and the specific work flow of DSP28335 is shown in fig. 3. During hardware design, an external pin GPIO11 (reusable as SCIRXDB) of the DSP28335 may be connected to an external serial port simulator. When the DSP28335 is initialized, the GPIO11 is initialized to be a low power interrupt response port, and enters a low power consumption (HALT MODE) MODE after the entire DSP is initialized, at this time, the clock and the like of the DSP28335 are all turned off, and the DSP is in the low power consumption MODE. DSP28335 can only be activated if GPIO11 pin is pulled down externally, because the pin is connected to the serial port on the hardware, the pin can be pulled down when any data is sent through the serial port, so as to activate DSP 28335.
FIG. 5 is a schematic diagram of the FPGA dynamic reconfiguration of the present invention.
With reference to fig. 4 and 5, the FPGA supports a configuration module built inside itself, and dynamically reconfigures and manages an internal area of the FPGA through an internal configuration interface of the FPGA. The FPGA is subjected to modular design during design, and a static configuration file and a normal work reconfigurable file are divided (the normal work reconfigurable file comprises two state files of normal work and low-power-consumption work). After the FPGA is electrified, the static configuration file is loaded for the first time, the normal working area of the FPGA is configured to be in a low-power-consumption working state, and after the FPGA is completely configured, the FPGA can be operated in a low-power-consumption mode. When the DSP receives an external normal work operation instruction, the DSP can control the FPGA to complete the dynamic reconstruction (reconstruction into a normal work state) of the normal work module through an internal configuration port (ICAP) and complete the normal time sequence work. After the normal work is finished, the FPGA can dynamically reconstruct the normal work module again (to be in a low power consumption state), and the high-power-consumption normal work is discontinuously used in such a way to achieve the purpose of low-power-consumption processing.
In a specific embodiment of the present invention, the entering of the low power consumption operation mode by the FPGA according to the external control of the DSP includes: and the FPGA carries out three times of configuration and dynamic reconfiguration on the reconfigurable area to form a low-power-consumption module.
In a specific embodiment of the present invention, as shown in fig. 2, the automatic entry of the FPGA into the low power consumption operating mode includes: and receiving external control through a static logic area of the FPGA, and realizing low power consumption control by a way of awakening the DSP by FPGA master control.
It should be noted that, in the design of the embodiment of the present invention, the DSP is used to receive the external control, and the FPGA is controlled by the DSP to perform dynamic reconfiguration to achieve the purpose of low power consumption control, and the external control may also be received by the static logic area of the FPGA, and the FPGA is controlled by the FPGA to wake up the DSP to achieve the purpose of low power consumption control.
In summary, the low power consumption processing method based on the FPGA and DSP architecture of the embodiment of the present invention includes the following steps: after the system is powered on and started, the FPGA completes self configuration and the DSP completes initialization, and the FPGA and the DSP are in a low-power-consumption working mode; when the DSP receives external data, the low power consumption mode is interrupted, and the normal working mode is jumped to; when the DSP detects an external normal working instruction, the FPGA is controlled to jump to a normal working mode to complete normal time sequence work; after the normal time sequence work is finished, the FPGA enters a low-power-consumption working mode according to the external control of the DSP or automatically. The FPGA completes self configuration and the DSP completes initialization, and the method comprises the following steps: after the FPGA is electrified, a static area is configured, and the reconfigurable area is configured into a low-power-consumption module; the external pin of the DSP is initialized to be a low-power-consumption interrupt response port. The code module of the FPGA comprises a static configuration file, a low-power consumption reconfigurable file and a normal work reconfigurable file. And after the FPGA is electrified, the static configuration file is loaded for the first time to configure the static region, and the reconfigurable region is configured into a low-power-consumption module at one time through an ICAP (independent component analysis protocol) according to the low-power-consumption reconfigurable file. The initialization of the external pin of the DSP to the low-power-consumption interrupt response port comprises the following steps: before the low-power-consumption working state, the external pin of the DSP is initialized to be a low-power-consumption awakening pin for low-power-consumption awakening, and the external pin of the DSP uses the same external input data. After low-power wake-up, initializing the external pin of the DSP to a reusable communication pin, and receiving an external control instruction by using the reusable communication pin. And an external pin of the DSP is connected with an external serial port simulator, and any data is sent through the external serial port to pull down the external pin of the DSP so as to activate the DSP and initialize the DSP into a reusable communication pin. When the DSP detects an external normal working instruction, the step of controlling the FPGA to jump to a normal working mode comprises the following steps: and when the DSP receives an external control instruction of normal work, the FPGA carries out secondary configuration dynamic reconfiguration on the reconfigurable area through ICAP (independent component analysis protocol) control according to the normal work reconfigurable file to form a normal work module. The FPGA enters a low-power-consumption working mode according to the external control of the DSP, and the low-power-consumption working mode comprises the following steps: and the FPGA carries out three times of configuration and dynamic reconfiguration on the reconfigurable area to form a low-power-consumption module. The FPGA automatically enters a low-power-consumption working mode and comprises the following steps: and receiving external control through a static logic area of the FPGA, and realizing low power consumption control by a way of awakening the DSP by FPGA master control. The embodiment of the invention solves the problems that when the existing system works, the DSP and the FPGA are in a normal working state for a long time, a large amount of heat consumption is generated in the chip, and the whole equipment is subjected to power consumption and heat consumption pressure, and particularly when the equipment is subjected to a high-temperature test, the high-temperature problem of the chip is obvious. The processing mode based on the FPGA and the DSP as the framework greatly reduces the generation of power consumption, improves the stability of the system, and effectively solves or relieves the problems of unstable work and high consumption possibly brought by the high power consumption of the FPGA and the DSP to the work of the system by adopting a mode of time-sharing processing with high power consumption and low power consumption.
In summary, the technical key points and the protection points of the present invention are as follows:
(1) the mode of combining FPGA dynamic reconfiguration and DSP low-power-consumption control is adopted, and a mode of working by using FPGA and DSP low power consumption intermittently is established.
(2) The characteristic that the external pins of the DSP are reusable is utilized, the external functional pins of the DSP are combined with the low-power consumption awakening pins, and the use efficiency of the low-power consumption mode of the DSP is improved.
Those skilled in the art will appreciate that all or part of the processes for implementing the methods in the above embodiments may be implemented by a computer program, which is stored in a computer-readable storage medium, to instruct associated hardware. The computer readable storage medium is a magnetic disk, an optical disk, a read-only memory or a random access memory.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Claims (4)
1. A low-power consumption processing method based on FPGA and DSP framework is characterized by comprising the following steps:
after the system is powered on and started, the FPGA completes self configuration and the DSP completes initialization, and the FPGA and the DSP are in a low-power-consumption working mode, which comprises the following steps: after the FPGA is electrified, a static area is configured, and the reconfigurable area is configured into a low-power-consumption module; initializing an external pin of the DSP to be a low-power-consumption interrupt response port;
the code module of the FPGA comprises a static configuration file, a low-power consumption reconfigurable file and a normal working reconfigurable file, which respectively correspond to files of a static control state, a low-power consumption working state and a normal working state;
after the FPGA is electrified, the static configuration file is loaded for the first time to configure a static region, and the reconfigurable region is configured into a low-power-consumption module at one time through an ICAP (independent component analysis protocol) according to the low-power-consumption reconfigurable file;
when the DSP receives external data, the low power consumption mode is interrupted, and the normal working mode is jumped to;
when the DSP detects an external normal working instruction, the FPGA is controlled to jump to a normal working mode to complete normal time sequence work, and the method comprises the following steps: when the DSP receives an external control instruction of normal work, the FPGA carries out secondary configuration dynamic reconfiguration on the reconfigurable area through ICAP (independent component analysis protocol) control according to the normal work reconfigurable file to form a normal work module;
after normal time sequence work is finished, the FPGA enters a low-power-consumption working mode according to the external control or the automation of the DSP, and the method comprises the following steps: the FPGA carries out three times of configuration and dynamic reconfiguration on the reconfigurable area to form a low-power-consumption module, or receives external control through a static logic area of the FPGA, and the FPGA is controlled by the way of waking up the DSP by main control to achieve low-power-consumption control.
2. The method of claim 1, wherein initializing an external pin of the DSP to a low power interrupt response port comprises: before the low-power-consumption working state, the external pin of the DSP is initialized to be a low-power-consumption awakening pin for low-power-consumption awakening, and the external pin of the DSP uses the same external input data.
3. The method of claim 2, wherein after the low power wake-up, the external pin of the DSP is initialized to a reusable communication pin and receives an external control command using the reusable communication pin.
4. The method according to claim 3, wherein an external pin of the DSP is connected with an external serial port simulator, and any data sent through the external serial port pulls down the external pin of the DSP to activate the communication pin which is initialized to be reusable.
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