CN112018025A - Preparation method of III-V group compound semiconductor heterojunction structure - Google Patents

Abstract

The invention provides a preparation method of a III-V group compound semiconductor heterojunction structure, which comprises the following steps: providing a monocrystalline group III-V compound semiconductor base and a heterogeneous support substrate, wherein the monocrystalline group III-V compound semiconductor base is provided with a first bonding surface, and the heterogeneous support substrate is provided with a second bonding surface; forming a first aluminum oxide dielectric layer on the first bonding surface, and forming a second aluminum oxide dielectric layer on the second bonding surface; and bonding the first aluminum oxide dielectric layer and the second aluminum oxide dielectric layer. The alumina film has high surface energy, can obtain high bonding quality under the condition of low-temperature bonding, is an amorphous material, has good absorptivity and permeability to water molecules, and can effectively remove gas generated at a bonding interface in the bonding process, so that the III-V compound semiconductor heterogeneous bonding is realized by adopting the alumina dielectric layer, and a high-quality bonding interface with high bonding strength and no bubbles at the bonding interface can be obtained.

Description

Method for preparing Ⅲ-V group compound semiconductor hetero-bonded structure

technical field

The invention belongs to the technical field of preparation of heterogeneous substrates, and particularly relates to a preparation method of a III-V group compound semiconductor hetero-bonded structure.

Background technique

In recent years, there have been important breakthroughs in the field of silicon photonics, and various silicon-based optical devices have been emerging, which makes silicon-based photonics systems play an important role in future information processing and communication, especially in data centers and supercomputers. .

However, because silicon is an indirect band gap semiconductor, it cannot be an effective light emitting material, while most III-V compound semiconductor materials are direct band gap semiconductor materials, which are very good materials for preparing optical devices. In order to realize the silicon-based optical system, there are two main methods, one is to directly epitaxially grow III-V compound semiconductor materials on a silicon substrate to prepare optical devices, and the other is to prepare the III-V group optical devices. No matter which method is directly combined with the silicon substrate, it is necessary to realize the heterogeneous integration of III-V compound semiconductor materials with the silicon substrate, which is also the biggest challenge of the current silicon-based optical system. Due to the large lattice mismatch and thermal mismatch between III-V compound semiconductors and silicon, more dislocations will occur when III-V compound semiconductors are heteroepitaxially grown on silicon substrates. It is difficult to achieve hetero-integration of high-quality III-V compound semiconductors with silicon substrates, thereby reducing the performance and reliability of late-stage devices. The advent of bonding technology has made it possible to combine III-V compound semiconductor materials with heterogeneous materials such as silicon. The bonding technology refers to contacting the surfaces of two atomically flat substrate sheets, forming chemical bonds at the entire interface, and then strengthening the bonding strength through high temperature annealing. After bonding the two heterogeneous material substrates together, the integration of thin film heterogeneous materials can be achieved by grinding thinning, chemical mechanical polishing or ion beam lift-off techniques. Later, the chip-to-wafer bonding technology was developed, that is, the prepared device is bonded to a heterogeneous substrate to achieve integration.

However, whether it is the direct integration of dissimilar materials through bonding or the integration of devices through chip-to-wafer bonding, there are problems of thermal mismatch and bonding interface bubbles. Large thermal mismatch can lead to wafer fragmentation or debonding, and at the same time, the air bubbles generated at the interface during the bonding process will also affect the bonding strength and the quality of the bonding interface, thereby reducing the performance and reliability of integrated devices.

Therefore, it is necessary to provide a method for preparing a III-V compound semiconductor hetero-bonded structure to solve the above problems in the prior art.

SUMMARY OF THE INVENTION

In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a method for preparing a III-V compound semiconductor hetero-bonded structure, which is used to solve the problem of the III-V compound semiconductor and the hetero liner in the prior art. Problems such as low bonding strength of bottom bonding and poor quality of bonding interface.

In order to achieve the above object and other related objects, the present invention provides a preparation method of a III-V compound semiconductor hetero-bonded structure, and the preparation method at least comprises the steps:

A single crystal III-V compound semiconductor substrate and a heterogeneous supporting substrate are provided, wherein the single crystal III-V compound semiconductor substrate has a first bonding surface, and the heterogeneous supporting substrate has a second bonding surface;

forming a first aluminum oxide dielectric layer on the first bonding surface, and forming a second aluminum oxide dielectric layer on the second bonding surface;

Bonding the first aluminum oxide dielectric layer and the second aluminum oxide dielectric layer.

Optionally, the material of the single crystal III-V compound semiconductor substrate includes one selected from the group consisting of indium phosphide, gallium arsenide, gallium antimonide, indium antimonide, indium arsenide and gallium nitride .

Optionally, the material of the heterogeneous support substrate includes one selected from the group consisting of silicon, silicon oxide, germanium, silicon carbide, and gallium arsenide.

Optionally, the first alumina dielectric layer is formed by atomic layer deposition, magnetron sputtering deposition or chemical vapor deposition, and the second oxide layer is formed by atomic layer deposition, magnetron sputtering deposition or chemical vapor deposition. Aluminum dielectric layer.

Optionally, the thickness of the first aluminum oxide dielectric layer is between 2 nm and 100 nm, and the thickness of the second aluminum oxide dielectric layer is between 2 nm and 100 nm.

Optionally, after the first aluminum oxide dielectric layer and the second aluminum oxide dielectric layer are bonded, the method further includes bonding the single crystal III-V compound semiconductor substrate and/or the heterogeneous supporting substrate. Thinning is performed.

Optionally, the heterogeneous support substrate comprises a single crystal heterogeneous support substrate.

Optionally, before forming the first aluminum oxide dielectric layer on the first bonding surface, the method further includes performing ion implantation on the single crystal III-V compound semiconductor substrate from the first bonding surface, so as to forming a defect layer at a predetermined depth in the single-crystal III-V compound semiconductor substrate; after bonding the first aluminum oxide dielectric layer and the second aluminum oxide dielectric layer, further comprising along the defect The layer peels off a portion of the single crystal III-V compound semiconductor substrate to form a thin layer structure on the hetero support substrate.

Further, the method for peeling off a portion of the single crystal group III-V compound semiconductor substrate along the defect layer includes annealing the single crystal group III-V compound semiconductor substrate on which the defect layer is formed.

Optionally, a device structure is formed in the single crystal III-V compound semiconductor substrate, and the material of the first bonding interface is a single crystal III-V compound.

As described above, the preparation method of the III-V group compound semiconductor heterobonded structure of the present invention includes: providing a single-crystal III-V group compound semiconductor substrate and a heterogeneous supporting substrate, and the single-crystal III-V group compound semiconductor substrate is provided. The compound semiconductor substrate has a first bonding surface, and the heterogeneous supporting substrate has a second bonding surface; a first aluminum oxide dielectric layer is formed on the first bonding surface, and a first aluminum oxide dielectric layer is formed on the second bonding surface forming a second aluminum oxide dielectric layer; bonding the first aluminum oxide dielectric layer and the second aluminum oxide dielectric layer. Due to the high surface energy of the aluminum oxide film, high bonding quality can be obtained under low temperature bonding conditions, and the aluminum oxide film is an amorphous material, which has good absorption and permeability for water molecules, and can effectively Therefore, the present invention realizes the single crystal III-V compound semiconductor by forming an alumina dielectric layer on the single crystal III-V compound semiconductor substrate and the heterogeneous support substrate. Bonding with a heterogeneous substrate can achieve high bonding strength and a high-quality bonding interface with no bubbles at the bonding interface.

Description of drawings

FIG. 1 is a schematic flow chart of the preparation method of the III-V compound semiconductor hetero-bonded structure of the present invention.

2 to 5 are schematic structural diagrams corresponding to each step in the preparation method of the III-V group compound semiconductor hetero-bonded structure according to the first embodiment.

6 to 9 are schematic diagrams showing the structures corresponding to each step in the preparation method of the III-V group compound semiconductor hetero-bonded structure according to the second embodiment.

10 to 13 are schematic diagrams showing the structures corresponding to each step in the preparation method of the III-V group compound semiconductor hetero-bonded structure of the third embodiment.

Component label description

11 Single crystal III-V compound semiconductor substrate

110 Partial single crystal III-V compound semiconductor substrates

111 Remaining single crystal III-V compound semiconductor substrate

12 Heterogeneous support substrate

13 The first bonding surface

14 Second bonding surface

15 The first aluminum oxide dielectric layer

16 The second aluminum oxide dielectric layer

17 Defective layer

18 Device Structure

D1 Thickness of the first aluminum oxide dielectric layer

D2 Thickness of the second aluminum oxide dielectric layer

S1～S3 steps

Detailed ways

The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

Please refer to Figure 1 to Figure 13. It should be noted that the diagrams provided in this embodiment are only to illustrate the basic concept of the present invention in a schematic way, so the diagrams only show the components related to the present invention rather than the number, shape and the number of components in the actual implementation. For dimension drawing, the type, quantity and proportion of each component can be changed at will in actual implementation, and the component layout may also be more complicated.

As shown in FIG. 1 , the present invention provides a method for preparing a III-V compound semiconductor hetero-bonded structure, the preparation method at least comprising the steps of:

Step S1: providing a single crystal III-V compound semiconductor substrate and a heterogeneous supporting substrate, wherein the single crystal III-V compound semiconductor substrate has a first bonding surface, and the heterogeneous supporting substrate has a second bonding face;

Step S2: forming a first aluminum oxide dielectric layer on the first bonding surface, and forming a second aluminum oxide dielectric layer on the second bonding surface;

Step S3: bonding the first aluminum oxide dielectric layer and the second aluminum oxide dielectric layer.

Due to the high surface energy of the aluminum oxide film, high bonding quality can be obtained under low temperature bonding conditions, and the aluminum oxide film is an amorphous material, which has good absorption and permeability for water molecules, and can effectively Therefore, the present invention realizes the single crystal III-V compound semiconductor by forming an alumina dielectric layer on the single crystal III-V compound semiconductor substrate and the heterogeneous support substrate. Bonding with a heterogeneous substrate can achieve high bonding strength and a high-quality bonding interface with no bubbles at the bonding interface.

As an example, the material of the single crystal group III-V compound semiconductor substrate may be any of the known single crystal group III-V compound semiconductors, such as indium phosphide, gallium arsenide, gallium antimonide , indium antimonide, indium arsenide or gallium nitride, etc.

As an example, the heterogeneous supporting substrate is used as a supporting substrate for the single crystal III-V compound semiconductor substrate after subsequent bonding, and the material of the heterogeneous supporting substrate can be any known material suitable for use as Any material of the support substrate, for example, silicon, silicon oxide, germanium, silicon carbide, or gallium arsenide. The hetero support substrate may also be a single crystal hetero support substrate.

As an example, the first aluminum oxide dielectric layer can be formed by deposition methods such as atomic layer deposition, magnetron sputtering deposition, or chemical vapor deposition; it can be formed by deposition methods such as atomic layer deposition, magnetron sputtering deposition, or chemical vapor deposition. the second aluminum oxide dielectric layer.

As an example, the thickness of the first aluminum oxide dielectric layer is between 2 nm and 100 nm, for example, may be 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm or 90 nm. The thickness of the second aluminum oxide dielectric layer is between 2 nm and 100 nm, for example, may be 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm or 90 nm.

It should be noted here that after bonding the first aluminum oxide dielectric layer and the second aluminum oxide dielectric layer, it may be necessary to perform some subsequent processing on the formed structure, for example, according to different product requirements, The single crystal III-V compound semiconductor substrate or the heterogeneous supporting substrate may be subjected to a thinning process, and the single crystal III-V compound semiconductor substrate and the heterogeneous supporting substrate may also be required to be thinned All are thinned.

The preparation method of the III-V group compound semiconductor hetero-bonded structure of the present invention is further described below with reference to specific embodiments.

Example 1

As shown in FIG. 1 and FIG. 2 , step S1 is first performed to provide a single crystal III-V compound semiconductor substrate 11 and a heterogeneous support substrate 12, and the single crystal III-V compound semiconductor substrate 11 has a first bond A bonding surface 13 is provided, and the heterogeneous support substrate 12 has a second bonding surface 14 .

It should be noted here that the single crystal III-V compound semiconductor substrate 11 is a single crystal substrate sheet, and no other device structure is formed therein.

As shown in FIG. 1 and FIG. 3 , step S2 is performed next, and a first aluminum oxide dielectric layer 15 is formed on the first bonding surface 13 by atomic layer deposition, magnetron sputtering deposition or chemical vapor deposition. A second aluminum oxide dielectric layer 16 is formed on the second bonding surface 14 by layer deposition, magnetron sputtering deposition or chemical vapor deposition.

As an example, the thickness D1 of the first aluminum oxide dielectric layer is between 20 nm and 40 nm, and the thickness D2 of the second aluminum oxide dielectric layer is between 20 nm and 40 nm.

It should be noted here that the formation of the first aluminum oxide dielectric layer 15 and the second aluminum oxide dielectric layer 16 is not limited in sequence, and can be formed simultaneously or sequentially, and the selection is based on actual process conditions.

As shown in FIG. 1 and FIG. 4 , step S3 is performed to bond the first aluminum oxide dielectric layer 15 and the second aluminum oxide dielectric layer 16 .

As shown in FIG. 5 , after the first aluminum oxide dielectric layer 15 and the second aluminum oxide dielectric layer 16 are bonded, the single crystal III-V compound semiconductor substrate 11 and the heterogenous The supporting substrate 12 is thinned by grinding, polishing and other processes.

Embodiment 2

As shown in FIG. 1 and FIG. 2 , step S1 is first performed to provide a single crystal III-V compound semiconductor substrate 11 and a heterogeneous support substrate 12, and the single crystal III-V compound semiconductor substrate 11 has a first bond A bonding surface 13 is provided, and the heterogeneous support substrate 12 has a second bonding surface 14 .

As shown in FIG. 6 , the first bonding surface 13 is used as the implantation surface, and the arrow indicates the direction of ion implantation, and ion implantation is performed in the single crystal III-V compound semiconductor substrate 11, so that the single crystal III-V compound semiconductor substrate 11 is implanted with ions. - A defect layer 17 is formed at a predetermined depth of the group V compound semiconductor substrate 11, and the defect layer 17 separates the single crystal group III-V compound semiconductor substrate 11 into the remaining single crystal group III-V on the upper and lower sides of the single crystal group III-V compound semiconductor substrate 11 The compound semiconductor substrate 111 and a part of the single crystal Group III-V compound semiconductor substrate 110 .

As shown in FIG. 1 and FIG. 7 , step S2 is performed next, and a first aluminum oxide dielectric layer 15 is formed on the first bonding surface 13 by atomic layer deposition, magnetron sputtering deposition or chemical vapor deposition. A second aluminum oxide dielectric layer 16 is formed on the second bonding surface 14 by layer deposition, magnetron sputtering deposition or chemical vapor deposition.

As an example, the thickness D1 of the first aluminum oxide dielectric layer is between 50 nm and 70 nm, and the thickness D2 of the second aluminum oxide dielectric layer is between 50 nm and 70 nm.

As shown in FIG. 1 and FIG. 8 , step S3 is performed to bond the first aluminum oxide dielectric layer 15 and the second aluminum oxide dielectric layer 16 .

As shown in FIG. 9 , a portion of the single crystal Group III-V compound semiconductor substrate 110 is peeled off along the defect layer 17 to leave the remaining single crystal Group III-V compound semiconductor on the heterogeneous supporting substrate The substrate 111 is formed to form a thin-layer structure, and the single-crystal III-V compound semiconductor thin-layer structure is transferred onto the heterogeneous support substrate 12 by using the ion beam lift-off technique.

As an example, the method of peeling off the part of the single crystal group III-V compound semiconductor substrate 110 along the defect layer 17 is: annealing the single crystal group III-V compound semiconductor substrate 11 on which the defect layer 17 is formed processing, so as to realize that the part of the single crystal III-V compound semiconductor substrate 110 is peeled off along the defect layer 17 .

Embodiment 3

As shown in FIG. 1 and FIG. 10 , step S1 is first performed to provide a single crystal III-V compound semiconductor substrate 11 and a heterogeneous support substrate 12, and the single crystal III-V compound semiconductor substrate 11 has a first bond A bonding surface 13 is provided, and the heterogeneous support substrate 12 has a second bonding surface 14 . It should be noted here that a device structure 18 is formed in the single crystal III-V compound semiconductor substrate 11 , and the material of the first bonding interface 13 is a single crystal III-V compound.

As shown in FIG. 1 and FIG. 11 , step S2 is performed next, and a first aluminum oxide dielectric layer 15 is formed on the first bonding surface 13 by atomic layer deposition, magnetron sputtering deposition or chemical vapor deposition. A second aluminum oxide dielectric layer 16 is formed on the second bonding surface 14 by layer deposition, magnetron sputtering deposition or chemical vapor deposition.

As an example, the thickness D1 of the first aluminum oxide dielectric layer is between 80 nm and 100 nm, and the thickness D2 of the second aluminum oxide dielectric layer is between 80 nm and 100 nm.

As shown in FIG. 1 and FIG. 12 , step S3 is performed to bond the first aluminum oxide dielectric layer 15 and the second aluminum oxide dielectric layer 16 .

As shown in FIG. 13 , after the first aluminum oxide dielectric layer 15 and the second aluminum oxide dielectric layer 16 are bonded, the single crystal III-V compound semiconductor substrate 11 and the heterogenous The supporting substrate 12 is thinned by grinding, polishing and other processes.

To sum up, the present invention provides a method for preparing a III-V group compound semiconductor hetero-bonded structure, including: providing a single crystal III-V group compound semiconductor substrate and a heterogeneous support substrate, and the single crystal III-V compound semiconductor substrate is provided. - The Group V compound semiconductor substrate has a first bonding surface, and the heterogeneous support substrate has a second bonding surface; a first aluminum oxide dielectric layer is formed on the first bonding surface, and a first aluminum oxide dielectric layer is formed on the second bonding surface A second aluminum oxide dielectric layer is formed on the joint surface; the first aluminum oxide dielectric layer and the second aluminum oxide dielectric layer are bonded. Due to the high surface energy of the aluminum oxide film, high bonding quality can be obtained under low temperature bonding conditions, and the aluminum oxide film is an amorphous material, which has good absorption and permeability for water molecules, and can effectively Therefore, the present invention realizes the single crystal III-V compound semiconductor by forming an alumina dielectric layer on the single crystal III-V compound semiconductor substrate and the heterogeneous support substrate. Bonding with a heterogeneous substrate can achieve high bonding strength and a high-quality bonding interface with no bubbles at the bonding interface. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments merely illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can make modifications or changes to the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed in the present invention should still be covered by the claims of the present invention.

Claims (10)

1. A method of fabricating a group iii-v compound semiconductor heterojunction structure, the method comprising at least the steps of:

providing a single crystalline group iii-v compound semiconductor base having a first bonding face and a foreign support substrate having a second bonding face;

forming a first aluminum oxide dielectric layer on the first bonding surface, and forming a second aluminum oxide dielectric layer on the second bonding surface;

and bonding the first aluminum oxide dielectric layer and the second aluminum oxide dielectric layer.

2. The method of fabricating a group iii-v compound semiconductor heterojunction structure of claim 1, wherein: the material of the single-crystal group iii-v compound semiconductor substrate includes one of the group consisting of indium phosphide, gallium arsenide, gallium antimonide, indium arsenide, and gallium nitride.

3. The method of fabricating a group iii-v compound semiconductor heterojunction structure of claim 1, wherein: the material of the heterogeneous support substrate comprises one of the group consisting of silicon, silicon oxide, germanium, silicon carbide, gallium arsenide.

4. The method of fabricating a group iii-v compound semiconductor heterojunction structure of claim 1, wherein: and the first aluminum oxide dielectric layer is formed by adopting an atomic layer deposition, magnetron sputtering deposition or chemical vapor deposition method, and the second aluminum oxide dielectric layer is formed by adopting an atomic layer deposition, magnetron sputtering deposition or chemical vapor deposition method.

5. The method of fabricating a group iii-v compound semiconductor heterojunction structure of claim 1, wherein: the thickness of the first aluminum oxide dielectric layer is between 2nm and 100nm, and the thickness of the second aluminum oxide dielectric layer is between 2nm and 100 nm.

6. The method of fabricating a group iii-v compound semiconductor heterojunction structure of claim 1, wherein: and thinning the monocrystalline III-V group compound semiconductor base and/or the heterogeneous support substrate after bonding the first aluminum oxide dielectric layer and the second aluminum oxide dielectric layer.

7. The method of fabricating a group iii-v compound semiconductor heterojunction structure of claim 1, wherein: the heterogeneous support substrate comprises a single crystal heterogeneous support substrate.

8. The method of fabricating a group iii-v compound semiconductor heterojunction structure of claim 1, wherein: before forming the first alumina dielectric layer on the first bonding surface, performing ion implantation on the monocrystalline III-V group compound semiconductor substrate from the first bonding surface to form a defect layer at a preset depth in the monocrystalline III-V group compound semiconductor substrate; and after the first aluminum oxide dielectric layer and the second aluminum oxide dielectric layer are bonded, stripping a part of the single crystal III-V group compound semiconductor base along the defect layer so as to form a thin layer structure on the heterogeneous support substrate.

9. The method of fabricating a group iii-v compound semiconductor heterojunction structure of claim 8, wherein: the method of peeling a portion of the single-crystalline group iii-v compound semiconductor substrate along the defect layer includes annealing the single-crystalline group iii-v compound semiconductor substrate on which the defect layer is formed.

10. The method of fabricating a group iii-v compound semiconductor heterojunction structure of claim 1, wherein: a device structure is formed in the single-crystal iii-v group compound semiconductor substrate, and the material of the first bonding interface is a single-crystal iii-v group compound.

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