CN111933521A - Method for manufacturing semiconductor device - Google Patents

Abstract

The present invention provides a method for manufacturing a semiconductor device, comprising: providing a substrate, the substrate including a first region and a second region, the first region including at least one first region to be implanted; forming a crystalline silicon layer on the substrate; At least one first crystalline silicon opening is formed in a part of the silicon layer corresponding to the first region, while at least one second crystalline silicon opening is formed in a part of the crystalline silicon layer corresponding to the second region; a first light is formed on the crystalline silicon layer A photoresist layer; patterning the first photoresist layer to form at least one first photoresist opening in a portion of the first photoresist layer corresponding to the first region, to form the patterned first photoresist layer For mask etching of the crystalline silicon layer, at least one third crystalline silicon opening is formed in the crystalline silicon layer; and an ion implantation process is performed using the remaining first photoresist layer and the crystalline silicon layer as masks. Using the semiconductor device manufacturing method provided by the present invention can ensure the yield of the finally fabricated semiconductor device, and has high efficiency.

Description

A method of manufacturing a semiconductor device

technical field

The present invention relates to the technical field of integrated circuit manufacturing, in particular to a method for manufacturing a semiconductor device.

Background technique

With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing in the direction of higher component density and higher integration, and the thickness of the film layers in semiconductor devices is also getting thinner and thinner. When the ion implantation process is performed as a mask layer, the mask layer is more likely to be broken down by ions, so that ions are implanted into the non-ion implantation region. For example, FIG. 1 is a schematic diagram of the semiconductor structure after the ion implantation process is performed. Referring to FIG. 1, when the thickness of the mask layer 3a is relatively thin, after the ion implantation process is performed, ions will penetrate the mask layer 3a and be implanted into the Non-ion implantation into the region a, thereby affecting the electrical properties of the final semiconductor structure. Therefore, before performing the ion implantation process, it is usually necessary to cover the photoresist layer over the mask layer 3a, and the photoresist layer and the mask layer 3a together serve as the ion implantation mask layer.

In detail, FIGS. 2-5 are schematic diagrams of semiconductor structures in the process of forming an ion implantation mask layer in the related art. As shown in FIG. 2 , a substrate 1 is provided first, and a dielectric layer 2 and a polysilicon layer 3 are formed on the substrate 1 . Referring to FIG. 3, the dielectric layer 2 and the polysilicon layer 3 on the substrate are etched to form a patterned dielectric layer 2a and a patterned polysilicon layer 3a and expose an ion implantation region, wherein, in particular, the polysilicon layer can be A photoresist layer 1 (not shown in the figure) is formed on 3a, the photoresist layer 1 is patterned by an exposure and development process, and the polysilicon is etched using the patterned photoresist layer 1 as a mask Layer 3 and dielectric layer 2, and then remove the photoresist layer 1 to obtain a patterned polysilicon layer 3a and a patterned dielectric layer 2a. After that, referring to FIG. 4 again, a photoresist layer 4 is formed on the substrate 1 . Further, referring to FIG. 5 , the photoresist layer 4 is patterned by exposure and development process to obtain a patterned photoresist layer 4a, and the patterned polysilicon layer 3a and the patterned photoresist layer are combined 4a is used together as an ion implantation mask layer to ensure that the ion implantation mask layer can have a sufficient thickness to prevent the occurrence of the phenomenon of ion breakdown through the mask layer.

However, when the patterned photoresist layer 4a is formed, it is difficult to ensure that the position of the mask when exposing the photoresist layer 4 is the same as the position of the mask when exposing the photoresist layer, so that It is difficult to ensure that the patterned photoresist layer 4a is completely aligned with the patterned polysilicon layer 3a, so that part of the patterned polysilicon layer 3a cannot be covered by the photoresist (for example, A1 of the polysilicon layer 3a in FIG. 5 ) area and A2 area), and part of the to-be-implanted area of the substrate 1 is covered with photoresist (for example, the B1 area and the B2 area of the substrate in FIG. 5 ). At this time, when the ion implantation process is performed using the patterned photoresist layer 4a and the patterned polysilicon layer 3a shown in FIG. 5 together as the ion implantation mask layer, part of the non-ion implantation region (for example, The parts of the substrate corresponding to the A1 region and the A2 region) are implanted with ions, and part of the ion implantation region of the substrate 1 (such as the B1 region and the B2 region of the substrate) cannot be implanted with ions. Specifically, Figure 6 is a comparison diagram The structure shown in 5 is a schematic diagram of the semiconductor structure after the ion implantation process is performed. Referring to FIG. 6, the morphology of the ion implantation region in the fabricated semiconductor structure will eventually be unsatisfactory, which will affect the final fabricated semiconductor structure. Electrical properties of semiconductor devices.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a method for manufacturing a semiconductor device, so as to solve the problem that the morphology of the ion implantation region in the prior art is not ideal, which affects the electrical properties of the final semiconductor device, resulting in a low yield of the semiconductor device. question.

In order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device, the method comprising:

providing a substrate, the substrate includes a first region and a second region, the first region includes at least one first region to be implanted;

forming a crystalline silicon layer on the substrate, the crystalline silicon layer covering the first region and the second region;

performing a first etching process to etch the crystalline silicon layer to form at least one first crystalline silicon opening in a portion of the crystalline silicon layer corresponding to the first region, and corresponding to the crystalline silicon layer At least one second crystalline silicon opening is formed in a part of the second region; wherein, the first crystalline silicon opening corresponds to the first to-be-implanted region one-to-one, and the first crystalline silicon opening is perpendicular to the The projection in the direction of the substrate surface falls into the corresponding first to-be-implanted region, and the opening size of the first crystalline silicon opening is smaller than the corresponding width of the first to-be-implanted region;

forming a first photoresist layer on the crystalline silicon layer, the first photoresist layer filling the at least one first crystalline silicon opening and the at least one second crystalline silicon opening;

patterning the first photoresist layer to form at least one first photoresist opening in a portion of the first photoresist layer corresponding to the first region, the first photoresist opening and The first to-be-implanted regions are in one-to-one correspondence, and the edges of the first photoresist openings are aligned with the corresponding edges of the first to-be-implanted regions;

performing a second etching process to etch the crystalline silicon layer using the patterned first photoresist layer as a mask to form at least one third crystalline silicon opening in the crystalline silicon layer;

An ion implantation process is performed to implant ions into the first region to be implanted.

Optionally, after the second etching process is performed, the sum of the thicknesses of the first photoresist layer and the crystalline silicon layer is greater than or equal to 0.4 μm.

Optionally, the second region includes at least one second region to be implanted, the second crystalline silicon opening corresponds to the second region to be implanted, and the edge of the second crystalline silicon opening corresponds to the corresponding region. The edges of the second to-be-implanted region are aligned.

Optionally, at least one first crystalline silicon opening is formed in a portion of the crystalline silicon layer corresponding to the first region, and at least one first crystalline silicon opening is formed in a portion of the crystalline silicon layer corresponding to the second region. The method of opening the two crystal silicon includes:

forming a second photoresist layer on the crystalline silicon layer, the second photoresist layer covering the first region and the second region;

patterning the second photoresist layer to form at least one second photoresist opening in a portion of the second photoresist layer corresponding to the first region, and forming at least one second photoresist opening in the second photoresist layer A portion of the layer corresponding to the second region forms at least one third photoresist opening; wherein the second photoresist opening corresponds to the first to-be-implanted region one-to-one, and the second photoresist opening corresponds to the first to-be-implanted region. The projection of the opening in the direction perpendicular to the surface of the substrate falls into the corresponding first to-be-implanted region, and the opening size of the second photoresist opening is smaller than the width of the corresponding first to-be-implanted region; the The third photoresist openings correspond to the second to-be-implanted regions one-to-one, and the edges of the third photoresist openings are aligned with the corresponding edges of the second to-be-implanted regions;

etching the crystalline silicon layer using the patterned second photoresist layer as a mask to form the at least one first crystalline silicon opening and the at least one second crystalline silicon opening in the crystalline silicon layer .

Optionally, a width dimension of the first region in a direction parallel to the substrate surface is greater than a width dimension of the second region in a direction parallel to the substrate surface;

And, the thickness of the first photoresist layer is greater than the thickness of the second photoresist layer.

Optionally, the first region includes two first regions to be implanted, and the second region includes two regions to be implanted.

Optionally, the material of the crystalline silicon layer includes polysilicon.

Optionally, before forming the crystalline silicon layer on the substrate, the method further includes: forming a dielectric layer on the substrate, the dielectric layer covering the first region and the second region.

Optionally, the first etching process further includes: etching a portion of the dielectric layer corresponding to the first crystalline silicon opening and the second crystalline silicon opening.

Optionally, after etching the crystalline silicon layer using the patterned first photoresist layer as a mask and before performing the ion implantation process, the method further includes:

The dielectric layer is etched using the patterned first photoresist layer as a mask.

Optionally, after performing the ion implantation process, the method further includes:

The remaining first photoresist layer is removed.

To sum up, in the semiconductor device manufacturing method provided by the present invention, after the first etching process is performed on the crystalline silicon layer on the substrate, at least a portion of the crystalline silicon layer corresponding to the first region is formed at least A first crystalline silicon opening, wherein the projection of the first crystalline silicon opening in the direction perpendicular to the surface of the substrate falls into the corresponding first to-be-implanted region, and the opening size of the first crystalline silicon opening is smaller than the corresponding The width dimension of the first to-be-implanted region. After that, a first photoresist layer is formed on the crystalline silicon layer, and the first photoresist layer is patterned to form at least a portion of the first photoresist layer corresponding to the first region. A first photoresist opening, and then using the patterned first photoresist layer as a mask to etch the crystalline silicon layer to form at least one third crystalline silicon opening in the crystalline silicon layer, the third The edge of the opening of the crystalline silicon layer is aligned with the edge of the first to-be-implanted region, and finally, the remaining first photoresist layer and the remaining crystalline silicon layer are used together as an ion implantation mask layer to inject into the first to-be-implanted region. The implantation region implants ions.

Wherein, based on the fact that the third crystalline silicon opening is formed by etching the patterned photoresist layer as a mask, the first photoresist opening and the third crystalline silicon opening are aligned with each other to achieve self-alignment Therefore, the phenomenon that the first photoresist opening and the third crystalline silicon opening are staggered will not occur. Therefore, when the ion implantation process is subsequently performed, the ions can be accurately implanted into the first to-be-implanted region, so as to ensure the accurate execution of the ion implantation process, and to form an ion implantation region with an ideal morphology, thereby ensuring the final The electrical properties of the fabricated semiconductor device improve the fabrication yield of the semiconductor device.

In addition, in the present invention, when the at least one first crystalline silicon opening is formed by etching, a portion of the crystalline silicon layer corresponding to the second region is also etched simultaneously, so as to correspond to the second region in the crystalline silicon layer At least one second crystalline silicon opening is formed on the part of the second crystalline silicon opening, and the second crystalline silicon opening will expose the second to-be-implanted region of the second region, so as to subsequently perform ion implantation on the second to-be-implanted region. Therefore, the present invention can also save process steps, simplify the process flow, and improve efficiency.

Description of drawings

1 is a schematic diagram of a semiconductor structure after an ion implantation process is performed in the related art;

2-5 are schematic diagrams of semiconductor structures in the process of forming an ion implantation mask layer in the related art;

6 is a schematic diagram of a semiconductor structure after an ion implantation process is performed on the structure shown in FIG. 5;

7 is a schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

8 is a schematic structural diagram of a substrate provided by an embodiment of the present invention;

FIG. 9 is a schematic diagram of a semiconductor structure after a crystalline silicon layer is formed on the structure shown in FIG. 8 according to an embodiment of the present invention;

10 is a schematic diagram of a semiconductor structure after a second photoresist layer is formed on the structure shown in FIG. 9 according to an embodiment of the present invention;

11 is a schematic diagram of a semiconductor structure after at least one second photoresist opening and at least one third photoresist opening are formed on the structure shown in FIG. 10 according to an embodiment of the present invention;

FIG. 12 is a top view of the structure shown in FIG. 11 according to an embodiment of the present invention;

13 is a schematic diagram of a semiconductor structure after at least one first crystalline silicon opening and at least one second crystalline silicon opening are formed on the structure shown in FIG. 11 according to an embodiment of the present invention;

14 is a schematic diagram of a semiconductor structure after removing the remaining second photoresist layer in the structure shown in FIG. 13 according to an embodiment of the present invention;

15 is a schematic diagram of a semiconductor structure after forming a first photoresist layer on the structure shown in FIG. 14 according to an embodiment of the present invention;

16 is a schematic diagram of a semiconductor structure after at least one first photoresist opening is formed in the structure shown in FIG. 15 according to an embodiment of the present invention;

17 is a schematic diagram of a semiconductor structure after at least one third crystalline silicon opening is formed in the structure shown in FIG. 16 according to an embodiment of the present invention;

FIG. 18 is a schematic diagram of a semiconductor structure after an ion implantation process is performed on the structure shown in FIG. 17 according to an embodiment of the present invention.

Reference number:

1-6 mentioned in the background art: a-non-ion implanted region; 1-substrate; 2-dielectric layer; 2a-patterned dielectric layer; 3-polysilicon layer; 3a-patterned 4 - photoresist layer; 4a - patterned photoresist layer; A1, A2 - the area not covered by photoresist in the patterned polysilicon layer 3a; B1, B2 - the area to be implanted in the substrate area covered by photoresist.

7-18 in the embodiments of the present invention: 10-substrate; 20-dielectric layer; C-first region; C1-first region to be implanted; C2-first ion implantation region; D-th two regions; D1-the second region to be implanted; 30-crystalline silicon layer; 31a-the first crystalline silicon opening; 31b-the second crystalline silicon opening; 31c-the third crystalline silicon opening; 40-the second photoresist layer; 41a—the second photoresist opening; 41b—the third photoresist opening; N—the opening size of the second photoresist opening in the direction parallel to the substrate surface; M—the first area to be implanted in the direction parallel to the substrate surface Width dimension; 50-first photoresist layer; 51-first photoresist opening.

Detailed ways

The manufacturing method of the semiconductor device proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that, the accompanying drawings are all in a very simplified form and in inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

FIG. 7 is a schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. As shown in FIG. 7 , the method may include:

Step 100 , providing a substrate, the substrate includes a first region and a second region, and the first region includes at least one first region to be implanted.

8 is a schematic structural diagram of a substrate provided by an embodiment of the present invention. As shown in FIG. 8 , the substrate 10 includes a first region C and a second region D, wherein the first region C may be a medium-voltage region or a high-voltage region, and the first region C may include at least one first region A to-be-implanted region C1 , for example, may include two first to-be-implanted regions C1 , and the two first to-be-implanted regions C1 may be used to form a source electrode and a lightly doped drain region (LDD region), respectively. And, the second region D may be a low pressure region, and the second region D may also include at least one second region to be implanted D1, for example, may include two second regions D1 to be implanted, the two second regions D1 The to-be-implanted regions D1 may be used to form the source and drain, respectively.

In this embodiment, the width dimension of the first region C in the direction parallel to the substrate surface is much larger than the width dimension of the second region D in the direction parallel to the substrate surface. Specifically, the first region C The width dimension in the direction parallel to the substrate surface may be 8 to 12 times (for example, 10 times) the width dimension of the second region D in the direction parallel to the substrate surface.

And, in this embodiment, the shape of the cross section of the first to-be-implanted region C1 and the second to-be-implanted region D1 may be rectangular, and the first to-be-implanted region C1 and the second to-be-implanted region D1 are parallel to each other. The width dimension in the direction of the surface of the substrate 10 may be equal.

Step 200 , forming a dielectric layer on the substrate, the dielectric layer covering the first region C and the second region D.

8 , a dielectric layer 20 covering the first region C and the second region D is formed on the substrate 10 , and the material of the dielectric layer 20 may be, for example, silicon oxide or silicon oxynitride , which can be formed using a chemical vapor deposition (CVD) process.

Step 300 , forming a crystalline silicon layer on the substrate, the crystalline silicon layer covering the first region and the second region.

FIG. 9 is a schematic diagram of a semiconductor structure after a crystalline silicon layer is formed on the structure shown in FIG. 8 according to an embodiment of the present invention. As shown in FIG. 9 , a crystalline silicon layer 30 is formed on the substrate 10 , and the crystalline silicon layer 30 covers the first region C and the second region D. As shown in FIG. The material of the crystalline silicon layer 30 may include polysilicon, and a crystalline silicon layer may be grown on the dielectric layer by means of epitaxial growth.

The method of this embodiment is especially suitable for application in the case where the thickness of the crystalline silicon layer is small. For example, when the thickness of the crystalline silicon layer is less than or equal to 1500 angstroms (for example, 1000 angstroms), the method provided by the embodiments of the present invention is adopted. The semiconductor device manufacturing method is more effective. Of course, even when the thickness of the crystalline silicon layer is greater than 1500 angstroms, the method of this embodiment can also be applied.

Step 400: Perform a first etching process to etch the crystalline silicon layer, so as to form at least one first crystalline silicon opening in a portion of the crystalline silicon layer corresponding to the first region, and in the crystalline silicon layer At least one second crystalline silicon opening is formed in a portion corresponding to the second region.

Wherein, in this embodiment, the method for the first etching process may specifically include the following steps:

The first step: forming a second photoresist layer on the crystalline silicon layer 30, the second photoresist layer covering the first area C and the second area D.

10 is a schematic diagram of a semiconductor structure after a second photoresist layer is formed on the structure shown in FIG. 9 according to an embodiment of the present invention. As shown in FIG. 10 , a second photoresist layer 40 is formed on the crystalline silicon layer 30 , and the second photoresist layer 40 covers the first region C and the second region D. The second photoresist layer 40 is formed by, for example, a spin coating process.

The second step: patterning the second photoresist layer 40 to form at least one second photoresist opening in a portion of the second photoresist layer 40 corresponding to the first region C, A portion of the second photoresist layer 40 corresponding to the second region D forms at least one third photoresist opening. During specific implementation, the second photoresist layer 40 may be patterned through exposure and development processes.

11 is a schematic diagram of a semiconductor structure provided by an embodiment of the present invention after at least one second photoresist opening and at least one third photoresist opening are formed on the structure shown in FIG. The formation of two second photoresist openings and two third photoresist openings is described as an example), FIG. 12 is a top view of FIG. 11 according to an embodiment of the present invention.

As shown in FIG. 11 , after the crystalline silicon layer 30 is patterned, two second photoresist openings 41 a are formed in a portion of the patterned second photoresist layer 40 corresponding to the first region C , two third photoresist openings 41b are formed in a portion corresponding to the second region D. 11 , the opening shapes of the second photoresist opening 41 a and the third photoresist opening 41 b in this embodiment may be rectangular.

And, it should be noted that the at least one second photoresist opening 41a corresponds to the first to-be-implanted region C1 one-to-one, which may specifically include: the number of the second photoresist openings 41a and the first to-be-implanted region C1 The number of the regions C1 is the same, and the projection of each of the second photoresist openings 41a in the direction perpendicular to the plane of the substrate falls into a first region C1 to be implanted, and the second photoresist The opening dimension N (refer to FIG. 11 ) of the opening 41 a in the direction parallel to the surface of the substrate 10 is smaller than the width dimension M of the corresponding first to-be-implanted region C1 in the direction parallel to the surface of the substrate 10 .

And, the third photoresist openings 41b are in one-to-one correspondence with the second to-be-implanted regions D1, which may specifically include: the number of the third photoresist openings 41b and the second to-be-implanted regions D1 and the edges of the third photoresist openings 41b are aligned with the edges of the second to-be-implanted region D1, that is, the projection of each of the third photoresist openings 41b in the direction perpendicular to the substrate plane They all fall into a second to-be-implanted region D1 , and the opening size of the third photoresist opening 41 b in a direction parallel to the surface of the substrate 10 is equal to the width of the second to-be-implanted region D1 in a direction parallel to the substrate 10 surface.

The third step: etching the crystalline silicon layer 30 using the patterned second photoresist layer 40 as a mask to form at least one first crystalline silicon opening and at least one second crystalline silicon opening. For example, the crystalline silicon layer 30 may be etched by a dry etching process.

13 is a schematic diagram of a semiconductor structure after at least one first crystalline silicon opening and at least one second crystalline silicon opening are formed on the structure shown in FIG. 11 according to an embodiment of the present invention. As shown in FIG. 13 , at least one first crystalline silicon opening 31 a and at least one second crystalline silicon opening 31 b are formed in the semiconductor structure. Wherein, the first crystalline silicon opening 31a and the second photoresist opening 41a communicate with each other, and the opening shape of the first crystalline silicon opening 31a is consistent with the opening shape of the second photoresist opening 41a, Both can be rectangular, and the width dimension of the first crystalline silicon opening 31a and the width dimension of the second photoresist opening 41a are also equal. In addition, the projection of each first crystalline silicon opening 31a in the direction perpendicular to the surface of the substrate also falls into a first to-be-implanted region C1, and the opening size of the first crystalline silicon opening 31a is smaller than the corresponding The width dimension of the first to-be-implanted region C1.

The second crystalline silicon opening 31b is communicated with the third photoresist opening 41b, and the opening shape of the second crystalline silicon opening 31b is the same as the opening shape of the third photoresist opening 41b, and both can be rectangular . In addition, the second crystalline silicon openings 31b and the second to-be-implanted regions D1 are also in one-to-one correspondence, and the edges of the second crystalline silicon openings 31b are aligned with the edges of the second to-be-implanted regions D1, including The numbers of the second crystalline silicon openings 31b and the second to-be-implanted regions D1 are equal, and the projection of each of the second crystalline silicon openings 31b in the direction perpendicular to the substrate surface will fall into one of the second to-be-implanted regions correspondingly In D1, the opening size of the second crystalline silicon opening 31b is equal to the corresponding width size of the second to-be-implanted region D1.

It should be noted that, in this embodiment, when performing the first etching process to etch the crystalline silicon layer 30, the dielectric layer 20 will also be etched simultaneously corresponding to the first crystalline silicon openings 31a and 31a. A portion of the second crystalline silicon opening 31b to expose the substrate 10 .

Step 4: Remove the remaining second photoresist layer. For example, the remaining second photoresist layer may be removed using an oxygen plasma ashing process.

14 is a schematic diagram of a semiconductor structure after removing the remaining second photoresist layer in the structure shown in FIG. 13 according to an embodiment of the present invention. As shown in FIG. 14, after the remaining second photoresist layer is removed, the remaining crystalline silicon layer 30 defines at least one first crystalline silicon opening 31a in the first region C, and in the second At least one second crystalline silicon opening 31b is defined in the region D (two are taken as examples in the figures for illustration). The first crystalline silicon opening 31a exposes part of the first to-be-implanted region C1. And, the second crystalline silicon opening 31b completely exposes the second to-be-implanted region D1.

In addition, it should be noted that in this step 400 , the portion of the crystalline silicon layer 30 corresponding to the second region D needs to be etched to form a second crystalline silicon opening that fully exposes the second to-be-implanted region D1 31b. Wherein, in view of the small width dimension of the second region D in the direction parallel to the substrate surface, it is necessary to make the thickness of the second photoresist layer 40 small, so as to prevent the thickness of the second photoresist layer 40 is larger, which leads to a degumming phenomenon when the crystalline silicon layer 30 on the second region D is etched. The thickness of the second photoresist layer 40 may be 3 to 5 times (for example, 5 times) the width of the second region D in the substrate 10 in a direction parallel to the surface of the substrate. For example, if the The width dimension of the second region in the direction parallel to the surface of the substrate is 60 nm, and the thickness of the second photoresist layer 40 may be 300 nm.

Step 500: A first photoresist layer is formed on the crystalline silicon layer, and the first photoresist layer fills the at least one first crystalline silicon opening and the at least one second crystalline silicon opening. The first photoresist layer is formed by, for example, a spin coating process.

15 is a schematic diagram of a semiconductor structure after forming a first photoresist layer on the structure shown in FIG. 14 according to an embodiment of the present invention. As shown in FIG. 15 , a first photoresist layer is formed on the substrate 10 A glue layer 50, the first photoresist layer 50 fills the at least one first crystalline silicon opening 31a and the at least one second crystalline silicon opening 31b.

Step 600 , patterning the first photoresist layer 50 using an exposure and development process to form at least one first photoresist in a portion of the first photoresist layer 50 corresponding to the first region C The first photoresist opening corresponds to the first to-be-implanted region C1 one-to-one, and the edge of the first photoresist opening is aligned with the edge of the first to-be-implanted region C1.

16 is a schematic diagram of a semiconductor structure after at least one first photoresist opening is formed in the structure shown in FIG. 15 according to an embodiment of the present invention, as shown in FIG. After the photoresist layer 50 is patterned, the patterned first photoresist layer 50 defines at least one first photoresist opening 51 in the first region C (in the figure, two first photoresist openings are used. The opening 51 is taken as an example for illustration), and the first photoresist opening 51 corresponds to the first to-be-implanted region C1 one-to-one, and the edge of the first photoresist opening 51 corresponds to the first to-be-implanted region C1. Aligning the edges of the implanted regions C1 specifically includes: the number of the first photoresist openings 51 and the first to-be-implanted regions C1 are the same, and each of the first photoresist openings 51 is perpendicular to the substrate The projections on the surface direction all fall into a first to-be-implanted region C1, and the opening size of the first photoresist opening 51 in the direction parallel to the substrate surface is parallel to the corresponding first to-be-implanted region C1. The width dimension in the direction of the substrate surface is equal.

Step 700 , performing a second etching process, etching the crystalline silicon layer 30 with the patterned first photoresist layer 50 as a mask, and forming at least one third crystalline silicon layer in the crystalline silicon layer 30 Open your mouth.

FIG. 17 is a schematic diagram of a semiconductor structure after at least one third crystalline silicon opening is formed in the structure shown in FIG. 16 according to an embodiment of the present invention. As shown in FIG. 17 , after the patterned first photolithography After the adhesive layer 50 is used as a mask to etch the crystalline silicon layer 30, at least one third crystalline silicon opening 31c will be formed in the crystalline silicon layer 30 (in the figure, two third crystalline silicon openings 31c are used as an example to perform the process. illustrate). Wherein, since in this embodiment, the patterned first photoresist layer 50 is used as a mask to etch the crystalline silicon layer 30, the crystalline silicon layer 30 is etched in the second etching process The etched part in the crystalline silicon layer 30 should be the part corresponding to the first photoresist opening 51. Based on this, the third crystalline silicon opening 31c formed in the crystalline silicon layer 30 should be the same as that of the first photoresist opening 51. The first photoresist openings 51 are aligned.

And further, in this embodiment, when the crystalline silicon layer 30 is etched with the patterned first photoresist layer 50 , part of the first photoresist layer 50 will be consumed, so that the first photoresist layer 50 will be consumed. The thickness of the resist layer 50 is reduced, wherein the ratio between the thickness of the consumed first photoresist layer 50 and the thickness of the crystalline silicon layer 30 to be etched is 1:1.

However, it should be emphasized that in this embodiment, it should be ensured that after the second etching process is performed, the thickness of the remaining second photoresist layer 50 is relatively thick, for example, greater than or equal to 0.3 μm, so that the final remaining second photoresist layer 50 has a thicker thickness. The total thickness of the second photoresist layer 50 and the remaining crystalline silicon layer 30 is relatively thick, for example, greater than or equal to 0.4 μm, so that in the subsequent ion implantation process, the remaining first photoresist layer and the remaining crystalline silicon layer can be combined together When used as an ion implantation mask layer, it can be ensured that the ion implantation mask layer can have a sufficient thickness to prevent ion breakdown. Therefore, in this embodiment, the thickness of the first photoresist layer 50 formed in step 500 should be thicker, and should be at least greater than the sum of the thickness of the crystalline silicon layer 30 and 0.3 μm. For example, the thickness of the first photoresist layer 50 formed in step 500 The thickness of a photoresist layer 50 may be 0.5 microns.

In addition, it should be noted that in this step, after the third crystalline silicon opening 31c is formed, the patterned first photoresist layer 50 will be used as a mask to etch the dielectric layer 20 to expose the The substrate 10 is described.

Step 800 , performing an ion implantation process to implant ions into the first to-be-implanted region to form a first ion-implanted region.

Wherein, it can be known from the content in the above step 600 that the final remaining first photoresist layer and the remaining crystalline silicon layer are aligned, and the first to-be-implanted region C1 will be completely exposed, and no As in the related art, the two are staggered, so that part of the crystalline silicon layer is not covered by the first photoresist layer and is exposed to the outside world, and part of the to-be-implanted area is covered by the first photoresist layer (for example, compare Fig. 5 and Figure 17). Based on this, when the ion implantation process is performed, ions will not break down the exposed crystalline silicon layer and be mistakenly implanted into the non-to-be-implanted area or the ions cannot be implanted into the first to-be-implanted area due to the blocking of the first photoresist layer If the phenomenon occurs, it can ensure that ions can be accurately implanted into the first to-be-implanted region C1, so that an accurate ion implantation profile can be formed, and, based on the remaining first photoresist layer and the remaining crystalline silicon layer With sufficient thickness, the phenomenon of ion breakdown of the ion implantation mask layer can also be prevented during the ion implantation process, which can further ensure the formation of accurate and ideal ion implantation topography.

18 is a schematic diagram of a semiconductor structure after an ion implantation process is performed on the structure shown in FIG. 17 according to an embodiment of the present invention. Compared with FIG. 6 and FIG. In the semiconductor structure manufactured by the manufacturing method, ions can be accurately implanted into the first to-be-implanted region C1 to form the first ion-implanted region C2 with accurate topography.

In this embodiment, after step 700 is performed, the method may further include: removing the remaining first photoresist layer to perform subsequent steps.

And, it should be noted that the manufacturing method of the semiconductor device in this embodiment is mainly used to manufacture a semiconductor device including an LDD region (for example, a liquid crystal driver).

To sum up, by using the semiconductor device manufacturing method provided by the present invention, an ion implantation region with accurate topography can be formed, thereby ensuring the electrical performance and yield of the finally fabricated semiconductor device.

And, it should be noted that, in the present invention, when the at least one first crystalline silicon opening is formed by etching, the part corresponding to the second region in the crystalline silicon layer is also etched synchronously, so that the crystalline silicon layer is etched simultaneously. At least one second crystalline silicon opening is formed in the part corresponding to the second region, and the second crystalline silicon opening will expose the second to-be-implanted region of the second region, so that the second to-be-implanted region can be subsequently implanted. Ion Implantation. Therefore, the present invention can also save process steps, simplify the process flow, and improve efficiency.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant part can be referred to the description of the method.

The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure all belong to the protection scope of the claims.

Claims (11)

1. A method for manufacturing a semiconductor device, wherein the method comprises: providing a substrate, the substrate includes a first region and a second region, the first region includes at least one first region to be implanted; forming a crystalline silicon layer on the substrate, the crystalline silicon layer covering the first region and the second region; performing a first etching process to etch the crystalline silicon layer to form at least one first crystalline silicon opening in a portion of the crystalline silicon layer corresponding to the first region, and corresponding to the crystalline silicon layer At least one second crystalline silicon opening is formed in a part of the second region; wherein, the first crystalline silicon opening corresponds to the first to-be-implanted region one-to-one, and the first crystalline silicon opening is perpendicular to the The projection in the direction of the substrate surface falls into the corresponding first to-be-implanted region, and the opening size of the first crystalline silicon opening is smaller than the corresponding width of the first to-be-implanted region; forming a first photoresist layer on the crystalline silicon layer, the first photoresist layer filling the at least one first crystalline silicon opening and the at least one second crystalline silicon opening; patterning the first photoresist layer to form at least one first photoresist opening in a portion of the first photoresist layer corresponding to the first region, the first photoresist opening and The first to-be-implanted regions are in one-to-one correspondence, and the edges of the first photoresist openings are aligned with the corresponding edges of the first to-be-implanted regions; performing a second etching process to etch the crystalline silicon layer using the patterned first photoresist layer as a mask to form at least one third crystalline silicon opening in the crystalline silicon layer; An ion implantation process is performed to implant ions into the first region to be implanted. 2 . The method for manufacturing a semiconductor device according to claim 1 , wherein after the second etching process is performed, the sum of the thicknesses of the first photoresist layer and the crystalline silicon layer is greater than or is equal to 0.4 microns. 3 . The method for manufacturing a semiconductor device according to claim 1 , wherein the second region comprises at least one second region to be implanted, and the second crystalline silicon opening corresponds to the second region to be implanted one-to-one. 4 . , and the edge of the second crystalline silicon opening is aligned with the edge of the corresponding second to-be-implanted region. 4. The method of manufacturing a semiconductor device according to claim 3, wherein at least one first crystalline silicon opening is formed in a portion of the crystalline silicon layer corresponding to the first region, and in the crystalline silicon layer The method for forming at least one second crystalline silicon opening in a portion corresponding to the second region includes: forming a second photoresist layer on the crystalline silicon layer, the second photoresist layer covering the first region and the second region; patterning the second photoresist layer to form at least one second photoresist opening in a portion of the second photoresist layer corresponding to the first region, and forming at least one second photoresist opening in the second photoresist layer A portion of the layer corresponding to the second region forms at least one third photoresist opening; wherein the second photoresist opening corresponds to the first to-be-implanted region one-to-one, and the second photoresist opening corresponds to the first to-be-implanted region. The projection of the opening in the direction perpendicular to the surface of the substrate falls into the corresponding first to-be-implanted region, and the opening size of the second photoresist opening is smaller than the width of the corresponding first to-be-implanted region; the The third photoresist openings correspond to the second to-be-implanted regions one-to-one, and the edges of the third photoresist openings are aligned with the corresponding edges of the second to-be-implanted regions; etching the crystalline silicon layer using the patterned second photoresist layer as a mask to form the at least one first crystalline silicon opening and the at least one second crystalline silicon opening in the crystalline silicon layer . 5. The method for manufacturing a semiconductor device according to claim 4, wherein a width dimension of the first region in a direction parallel to the substrate surface is larger than that of the second region in a direction parallel to the substrate surface width dimension; And, the thickness of the first photoresist layer is greater than the thickness of the second photoresist layer. 6 . The method for manufacturing a semiconductor device according to claim 4 , wherein the first region includes two first regions to be implanted, and the second region includes two regions to be implanted. 7 . 7 . The method of claim 1 , wherein the material of the crystalline silicon layer comprises polysilicon. 8 . 8. The method for manufacturing a semiconductor device according to claim 1, wherein before forming the crystalline silicon layer on the substrate, the method further comprises: forming a dielectric layer on the substrate, the dielectric layer covering the first area and the second area. 9 . The method for manufacturing a semiconductor device according to claim 8 , wherein the first etching process further comprises: etching the openings corresponding to the first crystalline silicon and the second openings in the dielectric layer. 10 . Part of the crystalline silicon opening. 10 . The method for manufacturing a semiconductor device according to claim 8 , wherein after the crystalline silicon layer is etched using the patterned first photoresist layer as a mask and before the ion implantation process is performed, the The method also includes: The dielectric layer is etched using the patterned first photoresist layer as a mask. 11. The method for manufacturing a semiconductor device according to claim 1, wherein after the ion implantation process is performed, the method further comprises: The remaining first photoresist layer is removed.

Images