CN111916539B - Front-mounted integrated unit diode chip - Google Patents

Abstract

The present invention provides a front-mounted integrated unit diode chip, comprising a first conductivity type electrode, a second conductivity type electrode, and a diode mesa structure located between the first conductivity type electrode and the second conductivity type electrode; the diode mesa structure includes n diode units, where n≥2. The n diode cells include a quantum well active region on the first conductivity type layer, a second conductivity type layer on the quantum well active region, insulation on the first conductivity type layer and partially covering the second conductivity type layer The dielectric layer is located on the second conductive type layer and partially covers the transparent electrode of the insulating dielectric layer, wherein the second conductive type electrode is located on the insulating dielectric layer and partially covers the transparent electrode. The invention solves the problems existing in the prior art that the thickness of the transparent electrode limits the lateral diffusion of the current and the light extraction efficiency of the LED, improves the lumen output of the unit diode chip per unit area, and reduces the lumen cost.

Description

A front-mounted integrated unit diode chip

technical field

The present invention relates to the field of semiconductor materials and device technology, in particular to semiconductor optoelectronic devices.

Background technique

The conventional front-mounted integrated unit diode chip has uneven current diffusion, which leads to the loss of luminous efficiency. The diode unit diode chip in the existing structure is dissipated through a sapphire substrate, which has poor heat dissipation, thus affecting the efficiency and stability of the unit diode chip. Therefore, the main application field of LED unit diode chips is usually the market of small and medium power unit diode chips below 0.5 watts, and products with high lumen output per unit area cannot be provided. Uneven current spreading, uneven heat spreading, and uneven light extraction lead to great limitations in three important parameters: lumen efficiency, lumen density output, and lumen cost. Unable to provide a valid solution.

The first prior art is the US patent application with the patent publication number US6614056B1. As shown in FIG. 1 , 21/23 are N-type electrodes, and 19/20ab are P-type electrodes. The mechanism of current diffusion is as follows: after ITO (indium tin oxide) forms ohmic contact with p-GaN, 19/20ab metal is deposited on ITO, and holes are diffused to p-GaN through electrode lines, reaching quantum wells. In the source region, the electrons diffused from the quantum well active region and the 21/22N-type electrode emit light through radiation recombination to obtain a light-emitting LED device. The ITO transparent conductive ohmic contact and the current spreading method with metal leads are used. Due to the high resistivity of ITO and the poor electrical conductivity of p-type GaN materials, the overall current spreading is very uneven. And considering the absorption of light by ITO, the thickness of the ITO layer should not be too large, which also limits the overall current diffusion. In addition, since the current diffusion length of the LED unit diode chip is inversely proportional to the square root of the current density, under the injection of a large current, the current diffusion length is shorter, resulting in more uneven current diffusion of the unit diode chip, lower efficiency, and heat dissipation. more difficult.

The non-uniform current spreading of the front mounted integrated cell diode chip leads to the loss of luminous efficiency. The diode unit diode chip in the existing structure is dissipated by the sapphire substrate, and the heat dissipation is poor, which affects the efficiency and stability of the unit diode chip. Therefore, the main application field of the diode unit diode chip with positive light emitting diodes is usually small and medium-sized below 0.5 watts. The power cell diode chip market cannot provide products with high lumen output per unit area. Uneven current spreading, uneven heat spreading, and uneven light extraction lead to great limitations in three important parameters: lumen efficiency, lumen density output, and lumen cost. Unable to provide a valid solution.

The second prior art is the conference paper of Proc.of SPIE Vol.10021 100210X-1 2016. As shown in Figure 2, the near-field analysis diagram of the LED chip (top) and the normalized current distribution diagram on the neutral line (bottom) , the size of the chip is 1.2mm × 1.2mm. The light intensity distribution in the near-field analysis graph is proportional to the distribution of the current spread. It can be seen from the figure that at a small current of 7A/ ^cm2 , the current density in some areas of the edge is less than 80% of that in the middle area. When the current increases by 70A/ ^cm2 , the current density in some areas of the edge is even less than 50% of the middle area. Therefore, LED light efficiency, heat dissipation and stability under high current are severely limited.

At present, the thickness of the transparent conductive film ITO (transparent electrode) in LED design is generally about 60-120 nanometers. The thicker the ITO, the greater the absorption of light, thereby reducing the efficiency of LED light extraction. The thinner the ITO thickness, the greater the sheet resistance, resulting in a worse lateral current spreading efficiency. Therefore, the thickness of ITO in existing LED designs is usually limited to a process window of 60-120 nm.

SUMMARY OF THE INVENTION

In order to solve the problem that the thickness of the transparent electrode in the prior art has too great influence on the light extraction efficiency and current diffusion of the LED chip, the present invention proposes a front-mounted integrated unit diode chip with small unit size and thin transparent electrode.

In order to achieve the above object, the present invention provides a front-mounted integrated unit diode chip, comprising: a first conductivity type electrode, a second conductivity type electrode, and a diode mesa located between the first conductivity type electrode and the second conductivity type electrode structure; the diode mesa structure includes n diode units, and the n diode units are arranged in a geometric shape, wherein, n≥2, the area of the mesa structure is determined according to the current diffusion length;

The n diode units include an insulating medium layer, a transparent electrode, a first conductivity type layer, a first conductivity type electrode, a second conductivity type layer, a second conductivity type electrode, and the second conductivity type electrode and the quantum well active region are located in the on the first conductivity type layer, the second conductivity type layer is located on the quantum well active region, the insulating medium layer is located on the first conductivity type layer and partially covers the second conductivity type layer, and the transparent electrode is located on the The second conductive type layer is located on and partially covers the insulating medium layer, and the second conductive type electrode is located on the insulating medium layer and partially covers the transparent electrode.

Preferably, the second conductive type electrode, the transparent electrode and the second conductive type layer are not connected in a vertical direction; the insulating medium layer partially covering the second conductive type layer is a current blocking layer.

Preferably, the diode mesa structure includes a trench structure, and the trench structure is located between the diode cells.

Preferably, the thickness of the transparent electrode is 60 nanometers to 120 nanometers, or 1 nanometer to 60 nanometers.

Preferably, the diode mesa structure includes a first conductivity type pad and a second conductivity type pad, the first conductivity type electrode is connected to the first conductivity type pad, and the second conductivity type electrode is connected to the second conductivity type pad .

Preferably, the insulating medium layer partially covers the second conductive type layer to form a first contact surface; the transparent electrode covers the insulating medium layer to form a second contact surface; the second conductive type electrode partially covers the transparent electrode to form a third contact noodle.

Preferably, the area of the first contact surface is larger than the area of the third contact surface.

Preferably, the area of the first contact surface is 0.001 μm×0.001 μm˜200 μm×200 μm; the area of the second contact surface is 0.001 μm×0.001 μm˜200 μm×200 μm; the area of the third contact surface is It is 0.001 μm × 0.001 μm to 200 μm × 200 μm.

Preferably, the longitudinal length of the first contact surface is greater than the longitudinal length of the third contact surface.

Preferably, the longitudinal length of the first contact surface is 0.001 micrometers to 200 micrometers; the longitudinal length of the second contact surface is 0.001 micrometers to 200 micrometers; the longitudinal length of the third contact surface is 0.001 micrometers to 200 micrometers.

Preferably, the diode mesa structure includes linear electrode lines; the linear electrode lines include electrode lines of a first conductivity type and electrode lines of a second conductivity type.

Preferably, the first conductivity type electrode is connected to the first conductivity type pad by a first conductivity type electrode wire, and the second conductivity type electrode and the second conductivity type pad are connected by a second conductivity type electrode wire.

Preferably, the linear electrode lines are electrode connecting lines between diode cells.

Preferably, the material of the insulating medium layer is silicon dioxide, aluminum oxide, and silicon nitride.

Preferably, the connection mode of the diode units is: parallel, series or a combination of series and parallel in a set ratio.

Preferably, the shape of the diode unit is: triangle, square, rectangle, pentagon, hexagon, circle, any custom shape.

Preferably, the number of the diode units ranges from 2 to 100 billion.

Preferably, the length of the diode unit along the Y-axis direction is 0.001 micrometers to 200 micrometers.

Preferably, the linear electrode lines have a width of 0.001 micrometers to 20 micrometers, and the linear electrode lines have a thickness of 0.001 micrometers to 10 micrometers.

Preferably, the line-type electrode line layout is: a layout in which more than one electrode line of the first conductivity type surrounds the mesa; or a layout in which more than one electrode line of the second conductivity type surrounds the mesa; or an electrode line of the first conductivity type and a second conductivity type electrode line. The number of type electrode lines is equal; or the first type electrode lines and the second type electrode lines are parallel, and the layout is insulated and overlapped in the vertical space, and there is an insulating medium material between the overlapping parts of the electrode lines of different conductivity types; or the electrodes of the first conductivity type The lines and the second conductive type electrode lines are insulated vertically and crossed, and the intersecting parts of the different conductive type electrode lines are separated by insulating dielectric materials; or part or all of the first conductive type electrode lines and the second conductive type electrode lines are designed using non-linear layout;

Preferably, the non-linear layout includes a polyline layout and a curved layout.

Preferably, the strip-shaped electrode wire adopts strip-shaped metal and/or indium tin oxide material; the strip-shaped metal material is aluminum, silver, titanium, nickel, gold, platinum, chromium, or any two or more of the above metals alloy.

Preferably, the diode mesa structure includes a hole structure.

Preferably, there is an intrinsic gallium nitride layer between the diode mesa structure and the substrate.

Preferably, the substrate is located on the mirror.

Preferably, the reflector material is silver, aluminum or distributed Bragg reflector. Preferably, the cross-sectional shapes of the trenches in the diode mesa structure are triangles, quadrilaterals, arcs, and other arbitrary defined shapes.

The front-mounted integrated unit diode chip adopted in the present invention breaks through the limitations of the existing front-mounted LED technology at the three levels of light, electricity and heat through the effect of nano-micron size structure. The area of the first contact surface is greater than the area of the third contact surface and the longitudinal length of the first contact surface is greater than the longitudinal length of the third contact surface, so that the current blocking layer spatially blocks the current of the second conductive type electrode and the second conductive type layer in the vertical direction diffusion. The reduction of the chip size of the integrated unit diode leads to a larger heat dissipation area on the side wall, which has better heat dissipation performance, and can allow the injection of ultra-high current density without affecting its stability. The thickness of the transparent electrode is less than 60 nanometers, and the light absorbing ability is weak, thereby improving the efficiency of light emitting of the LED, and solving the bottleneck of the thickness of the transparent electrode existing in the prior art. The size design of the unit diode chip is controlled within the current diffusion length, and its geometric optimization design method with high degree of freedom can simultaneously solve the problem of uneven current diffusion of the n-electrode and p-electrode that plagues the design of the LED unit diode chip. Higher photoelectric conversion efficiency/lumen efficiency; the nano-micro structure of each diode unit and the hole structure inside the mesa can increase the light-extraction area of the sidewall, thereby improving the light extraction efficiency.

Description of drawings

FIG. 1 is a structural diagram of a diode unit in the prior art.

FIG. 2 is a structural diagram of a diode unit in the prior art.

FIG. 3 is a top view of the front-mounted integrated unit diode chip provided in the first embodiment of the present invention.

FIG. 4 is a top view of the front-mounted integrated unit diode chip provided in the second embodiment of the present invention.

FIG. 5 is a top view of a front-mounted integrated unit diode chip provided in Embodiment 3 of the present invention.

6 is a schematic diagram of a diode unit in a mesa structure of a front-mounted integrated unit diode chip provided by the present invention.

FIG. 7 is a partial three-dimensional view of a mesa structure of a front-mounted integrated unit diode chip provided by the present invention.

First conductivity type electrode 1, second conductivity type electrode 2, transparent electrode 3, insulating medium layer 4, second conductivity type layer 5, quantum well active region (MQWs) 6, first conductivity type layer 7, intrinsic nitrogen Gallium oxide layer 8, substrate 9, mirror 10, first conductivity type pad 11, second conductivity type pad 12, first conductivity type electrode line 13, second conductivity type electrode line 14, mesa structure 15, diode Cell 16, trench structure 17.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

In view of the great limitations of the three important parameters of the existing diode structure, lumen efficiency, lumen density output, and lumen cost, the embodiment of the present invention provides a front-mounted integrated unit diode with high lumen efficiency and high lumen density output. The following The present invention will be described in detail with reference to the accompanying drawings.

A front-mounted integrated unit diode chip includes: a first conductivity type electrode, a second conductivity type electrode, and a diode mesa structure located between the first conductivity type electrode and the second conductivity type electrode; the diode mesa structure includes n diode units , the n diode units are arranged in a geometric shape, where n≥2, and the area of the mesa structure is determined according to the current spreading length.

The n diode units include an insulating medium layer, a transparent electrode, a first conductivity type layer, a first conductivity type electrode, a second conductivity type layer, a second conductivity type electrode, the second conductivity type electrode and the quantum well active region located in the first on the conductive type layer, the second conductive type layer is located on the quantum well active region, the insulating medium layer is located on the first conductive type layer and partially covers the second conductive type layer, and the transparent electrode is located on the second conductive type layer and partially covers the insulating layer A dielectric layer, the second conductive type electrode is located on the insulating dielectric layer and partially covers the transparent electrode. The second conductive type electrode, the transparent electrode and the second conductive type layer are not connected in the vertical direction; the insulating medium layer partially covering the second conductive type layer is a current blocking layer.

The diode mesa structure includes a trench structure, the trench structure is located between the diode units, the diode mesa structure further includes a first conductivity type pad and a second conductivity type pad, and the first conductivity type electrode is connected to the first conductivity type pad, The second conductivity type electrode is connected to the second conductivity type pad. The diode mesa structure further includes linear electrode lines, the width of the linear electrode lines is 0.001 micrometers to 20 micrometers, and the thickness of the linear electrode lines is 0.001 micrometers to 10 micrometers. The line type electrode line includes a first conductivity type electrode line and a second conductivity type electrode line, the first conductivity type electrode is connected with the first conductivity type pad, the first conductivity type electrode line is connected, and the second conductivity type electrode is connected with the second conductivity type electrode. The discs are connected by electrode lines of the second conductivity type. The linear electrode lines are electrode connecting lines between diode cells. The first conductivity type electrode is an n-type electrode, the second conductivity type electrode is a p-type electrode, the first conductivity type pad is an n-type pad, the second conductivity type is a p-type pad, and the first conductivity type electrode line is The n-type electrode lines, the second conductive type electrode lines are p-type electrode lines, the first conductive type layer is an n-GaN layer, and the second conductive type layer is a p-GaN layer.

The line-type electrode line layout is: a layout in which more than one first-conductivity-type electrode line surrounds the mesa; or one or more second-conductivity-type electrode lines surround the mesa; or a first-conductivity-type electrode line and a second-conductivity-type electrode line The layout is equal in number; or the electrode lines of the first type and the electrode lines of the second type are parallel, insulated and overlapped in the vertical space, and there are insulating dielectric materials between the overlapping parts of the electrode lines of different conductivity types; or the electrode lines of the first conductivity type and the Two conductive types of electrode lines are insulated and vertically crossed, and insulating dielectric materials are spaced between the intersecting parts of different conductive types of electrode lines; or part or all of the first conductive type electrode lines and the second conductive type electrode lines are designed in a non-linear layout; Linear layout includes polyline layout and curved layout. The wire-shaped electrode wire adopts wire-shaped metal and/or indium tin oxide material; the wire-shaped metal material is aluminum, silver, titanium, nickel, gold, platinum, chromium, or an alloy of any two or more of the above metals.

The insulating medium layer partially covers the second conductive type layer to form the first contact surface. The transparent electrode covers the insulating medium layer to form a second contact surface. The second conductive type electrode partially covers the transparent electrode to form a third contact surface. The area of the first contact surface, the area of the second contact surface, and the area of the third contact surface are unequal or partially equal, and the area of the first contact surface is larger than the area of the third contact surface. The area of the first contact surface is 0.001 μm×0.001 μm～200 μm×200 μm, the area of the second contact surface is 0.001 μm×0.001 μm～200 μm×200 μm, and the area of the third contact surface is 0.001 μm×0.001 μm～ 200 microns x 200 microns. The longitudinal length of the first contact surface, the longitudinal length of the second contact surface, and the longitudinal length of the third contact surface are unequal or partially equal, and the longitudinal length of the first contact surface is greater than the longitudinal length of the third contact surface. The longitudinal length of the first contact surface is 0.001 to 200 microns, the longitudinal length of the second contact surface is 0.001 to 200 microns, and the longitudinal length of the third contact surface is 0.001 to 200 microns.

The thickness of the transparent electrode is 60 nanometers to 120 nanometers, or 1 nanometer to 60 nanometers, and the material of the insulating medium layer is silicon dioxide, aluminum oxide, and silicon nitride.

The connection mode of the diode unit is: parallel, series or a combination of series and parallel in a set ratio. The shape of the diode unit is: triangle, square, rectangle, pentagon, hexagon, circle, any custom shape. The number of diode cells ranges from 2 to 100 billion. The length of the diode unit along the Y-axis direction is 0.001 micrometers to 200 micrometers.

The diode mesa structure includes a hole structure, an intrinsic gallium nitride layer is arranged between the diode mesa structure and a substrate, the substrate is located on a reflector, and the reflector material is silver, aluminum or a distributed Bragg reflector.

Example 1

This embodiment provides a front-mounted integrated unit diode chip, as shown in FIG. 3 , including: an n-type electrode 1 , an n-type pad 11 , a p-type pad 12 , an n-type electrode line 13 , a p-type electrode line 14 , a diode Mesa 15 , diode cell 16 and trench 17 . The diode mesa structure includes a total of 52 square diode units 16 in 6 rows that are evenly distributed in size, and the length of the diode units along the Y-axis direction is 40 microns. The diode mesa structure adopts a square arrangement, and the size of the mesa structure is smaller than the diffusion length of the current injection. The shape of the diode unit is a regular rectangle, which is distributed in a uniform and symmetrical arrangement.

In some preferred embodiments, the length of the diode unit along the Y-axis direction is 100 nanometers; in other preferred embodiments, the length of the diode unit along the Y-axis direction is 10 nanometers.

The first conductive type electrode lines 13 and the second conductive type electrode lines 14 are line-type electrode lines, the line-type electrode lines have a width of 0.001 micrometers to 20 micrometers, and a thickness of 0.001 micrometers to 10 micrometers. layout design. The first conductive type pad 11 and the second conductive type pad 12 are in the shape of an arc-shaped irregular polygon, the number of pads is 1, and they are located at the edge of the mesa structure. The shape of the grooves 17 is a cross, the cross-sectional shape is a rectangle, and the grooves 17 are evenly distributed in the horizontal direction.

As shown in FIG. 6 , the n diode units in the diode mesa structure include n-type pads 11 , p-type electrodes 2 , transparent electrodes 3 , insulating dielectric layers 4 , n-GaN layers 7 , p-GaN layers 5 , and quantum wells Active area 6. The p-type electrode 2 and the quantum well active region 6 are located on the n-GaN layer 7 , the p-GaN layer 5 is located on the quantum well active region 6 , and the insulating dielectric layer 4 is located on the n-GaN layer 7 and partially covers the p-GaN layer Layer 5, the transparent electrode 3 is located on the p-GaN layer 5 and partially covers the insulating dielectric layer 4, and the p-type electrode 2 is located on the insulating dielectric layer 4 and partially covers the transparent electrode 3.

As shown in FIG. 7 , the insulating dielectric layer 4 partially covers the p-GaN layer 5 to form the first contact surface, the transparent electrode 3 covers the insulating dielectric layer 4 to form the second contact surface, and the p-type electrode 2 partially covers the transparent electrode 3 to form the third contact surface noodle. The insulating dielectric layer partially covering the p-GaN layer is a current blocking layer. Since the area of the first contact surface is larger than that of the third contact surface and the longitudinal length of the first contact surface is greater than the longitudinal length of the third contact surface, the current blocking layer is completely spatially The current diffusion in the vertical direction of the p-type electrode 2, the transparent electrode 3 and the p-GaN layer is blocked.

In some preferred embodiments, the area of the first contact surface is 20 micrometers×20 micrometers, and the longitudinal length of the first contact surface is 20 micrometers; the area of the second contact surface is 15 micrometers×15 micrometers, and the longitudinal length of the second contact surface is 15 micrometers. micrometer; the area of the third contact surface is 10 micrometers×10 micrometers, and the longitudinal length of the third contact surface is 10 micrometers.

In some other preferred embodiments, the area of the first contact surface is 10 micrometers×10 micrometers, and the longitudinal length of the first contact surface is 10 micrometers; the area of the second contact surface is 8 micrometers×8 micrometers, and the longitudinal length of the second contact surface is 8 micrometers. micrometer; the area of the third contact surface is 5 micrometers×5 micrometers, and the longitudinal length of the third contact surface is 5 micrometers.

Example 2

This embodiment provides a front-mounted integrated unit diode chip, as shown in FIG. 4 , including: a first conductivity type electrode 1 , a first conductivity type pad 11 , a second conductivity type pad 12 , and a first conductivity type electrode line 13 , second conductivity type electrode lines 14 , diode mesa structures 15 , diode cells 16 and trenches 17 . The diode mesa structure includes 6 rows of 102 triangular diode units 16 uniformly distributed in size, and the length of the diode units along the Y-axis direction is 80 microns. The diode mesa structure adopts a triangular arrangement, and the size of the mesa structure is smaller than the diffusion length of the current injection. The diode cells are triangular in shape and distributed in a uniform symmetrical arrangement.

In some preferred embodiments, the length of the diode unit along the Y-axis direction is 100 microns; in other preferred embodiments, the length of the diode unit along the Y-axis direction is 10 microns; in other preferred embodiments, the length of the diode unit along the Y-axis direction is 10 microns The axial length is 1 μm.

The first conductive type electrode lines 13 and the second conductive type electrode lines 14 are line-type electrode lines, the line-type electrode lines have a width of 0.001 micrometers to 20 micrometers, and a thickness of 0.001 micrometers to 10 micrometers. layout design. The first conductive type pad 11 and the second conductive type pad 12 are in the shape of an arc-shaped irregular polygon, the number of pads is 1, and they are located at the edge of the mesa structure. The shape of the grooves 17 is a cross, the cross-sectional shape is a rectangle, and the grooves 17 are evenly distributed in the horizontal direction. As shown in FIG. 4 , a hole structure is added to each diode unit, the hole structure includes one hole unit, and the hole unit is a circular hole unit with a diameter of 1 nm to 20 microns. Pore cells are arranged symmetrically, asymmetrically, periodically, aperiodically or randomly. The shape of the hole unit can also be a triangle, a square, a rectangle, a pentagon, a hexagon, a circle, and any other defined shape, and is not limited to the shape shown in FIG. 4 .

As shown in FIG. 6 , the n diode units in the diode mesa structure include a first conductive type pad 11 , a second conductive type electrode 2 , a transparent electrode 3 , an insulating medium layer 4 , a first conductive type layer 7 , and a second conductive type layer 7 . Type layer 5, quantum well active region 6. The second conductive type electrode 2 and the quantum well active region 6 are located on the first conductive type layer 7 , the second conductive type layer 5 is located on the quantum well active region 6 , and the insulating medium layer 4 is located on the first conductive type layer 7 and The second conductive type layer 5 is partially covered, the transparent electrode 3 is located on the second conductive type layer 5 and partially covers the insulating medium layer 4 , and the second conductive type electrode 2 is located on the insulating medium layer 4 and partially covers the transparent electrode 3 . The first conductive type layer is an n-GaN layer, the second conductive type layer is a p-GaN layer, and the trench depth of the diode unit reaches the n-GaN layer. The insulating medium layer 4 partially covers the second conductive type layer 5 to form the first contact surface, the transparent electrode 3 covers the insulating medium layer 4 to form the second contact surface, and the second conductive type electrode 2 partially covers the transparent electrode 3 to form the third contact surface. The area of the first contact surface is 0.006 μm×0.006 μm, the area of the second contact surface is 0.004 μm×0.004 μm, and the area of the third contact surface is 0.002 μm×0.002 μm. The longitudinal length of the first contact surface is 0.006 microns, the longitudinal length of the second contact surface is 0.004 microns, and the longitudinal length of the third contact surface is 0.002 microns.

In some preferred embodiments, the area of the first contact surface is 0.1 μm×0.1 μm, and the longitudinal length of the first contact surface is 0.1 μm; the area of the second contact surface is 0.08 μm×0.08 μm, and the longitudinal length of the second contact surface is 0.08 μm μm; the area of the third contact surface is 0.05 μm×0.05 μm, and the longitudinal length of the third contact surface is 0.05 μm.

In other preferred embodiments, the area of the first contact surface is 1 μm×1 μm, and the longitudinal length of the first contact surface is 1 μm; the area of the second contact surface is 0.8 μm×0.8 μm, and the longitudinal length of the second contact surface is 0.8 μm micrometer; the area of the third contact surface is 0.5 micrometers×0.5 micrometers, and the longitudinal length of the third contact surface is 0.5 micrometers.

Example 3

This embodiment provides a front-mounted integrated unit diode chip, as shown in FIG. 5 , including: a first conductivity type electrode 1 , a first conductivity type pad 11 , a second conductivity type pad 12 , and a first conductivity type electrode line 13 , second conductivity type electrode lines 14 , diode mesa structures 15 , diode cells 16 and trenches 17 . The diode mesa structure includes a total of 52 square diode units 16 in 6 rows that are evenly distributed in size, and the length of the diode units along the Y-axis direction is 40 microns. The diode mesa structure adopts a square arrangement, and the size of the mesa structure is smaller than the diffusion length of the current injection. The shape of the diode unit is a regular rectangle, which is distributed in a uniform and symmetrical arrangement. A hole structure is added to each diode unit, the hole structure includes two hole units, and the hole unit is a circular hole unit with a diameter of 1 nm to 20 microns. Pore cells are arranged symmetrically, asymmetrically, periodically, aperiodically or randomly. The shape of the hole unit can also be a triangle, a square, a rectangle, a pentagon, a hexagon, a circle, and any other defined shape, and is not limited to the shape shown in FIG. 5 .

The first conductive type electrode lines 13 and the second conductive type electrode lines 14 are line-type electrode lines, the line-type electrode lines have a width of 0.001 micrometers to 20 micrometers, and a thickness of 0.001 micrometers to 10 micrometers. layout design. The first conductive type pad 11 and the second conductive type pad 12 are in the shape of an arc-shaped irregular polygon, the number of pads is 1, and they are located at the edge of the mesa structure. The shape of the grooves 17 is a cross, the cross-sectional shape is a rectangle, and the grooves 17 are evenly distributed in the horizontal direction.

As shown in FIG. 6 , the n diode units in the diode mesa structure include a first conductive type pad 11 , a second conductive type electrode 2 , a transparent electrode 3 , an insulating medium layer 4 , a first conductive type layer 7 , and a second conductive type layer 7 . Type layer 5, quantum well active region 6. The second conductive type electrode 2 and the quantum well active region 6 are located on the first conductive type layer 7 , the second conductive type layer 5 is located on the quantum well active region 6 , and the insulating medium layer 4 is located on the first conductive type layer 7 and The second conductive type layer 5 is partially covered, the transparent electrode 3 is located on the second conductive type layer 5 and partially covers the insulating medium layer 4 , and the second conductive type electrode 2 is located on the insulating medium layer 4 and partially covers the transparent electrode 3 . The first conductive type layer is an n-GaN layer, the second conductive type layer is a p-GaN layer, and the trench depth of the diode unit reaches the n-GaN layer.

The insulating medium layer 4 partially covers the second conductive type layer 5 to form the first contact surface, the transparent electrode 3 covers the insulating medium layer 4 to form the second contact surface, and the second conductive type electrode 2 partially covers the transparent electrode 3 to form the third contact surface. The area of the first contact surface is 0.03 μm×0.03 μm, the area of the second contact surface is 0.02 μm×0.02 μm, and the area of the third contact surface is 0.01 μm×0.01 μm. The longitudinal length of the first contact surface is 0.03 microns, the longitudinal length of the second contact surface is 0.02 microns, and the longitudinal length of the third contact surface is 0.01 microns.

In some preferred embodiments, the area of the first contact surface is 0.06 μm×0.06 μm, the longitudinal length of the first contact surface is 0.06 μm, the area of the second contact surface is 0.04 μm×0.04 μm; the longitudinal length of the second contact surface is 0.04 μm microns; the area of the third contact surface is 0.02 micrometers×0.02 micrometers, and the longitudinal length of the third contact surface is 0.02 micrometers.

In other preferred embodiments, the area of the first contact surface is 0.8 μm×0.8 μm, the longitudinal length of the first contact surface is 0.8 μm, the area of the second contact surface is 0.5 μm×0.5 μm; the longitudinal length of the second contact surface is 0.5 μm; the area of the third contact surface is 0.3 μm×0.3 μm, and the longitudinal length of the third contact surface is 0.3 μm.

For 0.5W conventional front-mounted integrated unit light-emitting diode products, the driving current is usually 150mA, and the driving current density is about 70A/cm ² . In the present invention, since the size of each unit is smaller than the current diffusion length, and through the ultra-uniform current distribution design, the driving current of the 0.5W front-mounted integrated unit light-emitting diode can be more than 150A/cm ² . The current density that can be tolerated is more than 2 times that of conventional positive-mounted LED products. For example, for a typical 0.5W front-mounted LED chip, when the driving current exceeds 150mA, due to the uneven current diffusion, the voltage VF of the front-mounted LED chip rises sharply, and the thermal effect is very significant, so the chip cannot withstand high current driving; and the corresponding integrated unit The driving current of the light-emitting diode chip can be increased to more than 600mA, while the increase of the contrast voltage VF is small. Therefore, the current density that the integrated unit light-emitting diode can withstand is several times that of the front-mounted LED, which brings huge advantages of lumen density and lumen cost.

Here, the 0.5W LED chip is used as an example to illustrate the advantages of the huge lumen density and lumen cost of the integrated unit light-emitting diode chip. Another point that needs to be emphasized is that due to the difficulty of current diffusion and heat dissipation, the LED chip can only be used as a product with an output of 0.5W. However, the integrated unit light-emitting diode product of the same size can actually drive a current of more than 600mA, and has actually reached a driving power of 2W, so the lumen output of the chip can be more than 4 times that of the full-scale product, realizing the full-scale medium and small power LED. Ultra high lumen density output that the product does not have.

The front-mounted integrated unit diode chip provided by the embodiment of the present invention has the following beneficial effects:

(1) The length design of the diode unit of the present invention is controlled within the current diffusion length, and the optimized geometric design with a certain degree of freedom can further improve the light extraction efficiency, and can simultaneously solve the problems of n-type electrodes and p-type electrodes that trouble the design of LED unit diode chips The problem of non-uniform current diffusion of type electrodes can be solved, so that higher photoelectric conversion efficiency/lumen efficiency can be obtained.

(2) The length of the diode unit of the present invention can be designed to be much smaller than the current diffusion length, so the thickness of the transparent electrode can be greatly reduced, thereby greatly reducing the absorption of light by the transparent electrode, thereby increasing the light extraction efficiency of the chip.

(3) The design of the current blocking layer structure can reduce the current accumulation and light absorption effects, and improve the light extraction efficiency of the chip.

(4) The micro-nano structure of each diode unit of the present invention increases the light emitting area of the sidewall, thereby improving the light extraction efficiency.

(5) The optimization of the chip size of the integrated unit diode of the present invention brings a larger heat dissipation area of the side wall, has better heat dissipation performance, allows the injection of a large current density without affecting its stability, and greatly improves the unit area. The lumen output of the unit diode chip reduces the lumen cost.

(6) The design of the integrated unit diode chip of the present invention can realize ultra-uniform current injection, thereby obtaining higher efficiency, better wavelength uniformity, narrower half-width of the emission spectrum, and better heat dissipation uniformity. and better device stability, the current injection uniformity far exceeds the current injection uniformity of about 50% of the normal device.

(7) The integrated unit diode chip of the present invention is suitable for LED products of various color systems such as UVC, UVA, UVB, purple light, blue light, green light, yellow light, red light, infrared light, etc., and can be used for LED lighting, backlight, display, plant Lighting, medical and other semiconductor light-emitting device applications.

The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above-mentioned specific embodiments are only specific embodiments of the present invention, and are not intended to limit the protection of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (13)

1. A forward mounted integrated cell diode chip, comprising:

a first conductivity type electrode, a second conductivity type electrode, and a diode mesa structure between the first conductivity type electrode and the second conductivity type electrode; the diode mesa structure comprises n diode units, wherein the n diode units are arranged in a geometric shape, n is more than or equal to 2, and the mesa structure area is determined according to the current diffusion length;

the n diode units comprise an insulating medium layer, a transparent electrode, a first conduction type layer, a first conduction type electrode, a second conduction type layer and a second conduction type electrode, wherein the second conduction type electrode and the quantum well active region are positioned on the first conduction type layer;

the diode mesa structure comprises trench structures, the trench structures being located between the diode cells;

the second conductive type electrode, the transparent electrode and the second conductive type layer are not communicated in the vertical direction; the insulating medium layer partially covering the second conductive type layer is a current blocking layer;

the thickness of the transparent electrode is 60-120 nm, or 1-60 nm;

the diode mesa structure comprises a first conduction type bonding pad and a second conduction type bonding pad, wherein a first conduction type electrode is connected with the first conduction type bonding pad, and a second conduction type electrode is connected with the second conduction type bonding pad; the insulating medium layer partially covers the second conductive type layer to form a first contact surface; the transparent electrode partially covers the insulating medium layer to form a second contact surface; the second conductive type electrode partially covers the transparent electrode to form a third contact surface;

the area of the first contact surface is larger than that of the third contact surface;

the area of the first contact surface is 0.001 micrometer multiplied by 0.001 micrometer to 200 micrometer multiplied by 200 micrometer; the area of the second contact surface is 0.001 micrometer multiplied by 0.001 micrometer to 200 micrometer multiplied by 200 micrometer; the area of the third contact surface is 0.001 micrometer multiplied by 0.001 micrometer to 200 micrometer multiplied by 200 micrometer;

the first contact surface longitudinal length is greater than the third contact surface longitudinal length;

the first contact longitudinal length is between 0.001 and 200 microns; the longitudinal length of the second contact surface is 0.001-200 microns; the longitudinal length of the third contact surface is 0.001-200 microns;

the diode mesa structure comprises a line-type electrode line; the line-type electrode wires comprise a first conductive type electrode wire and a second conductive type electrode wire;

the width of the linear electrode wire is 0.001-20 microns, and the thickness of the linear electrode wire is 0.001-10 microns;

the first conductive type electrode is connected with the first conductive type bonding pad and the first conductive type electrode wire, and the second conductive type electrode is connected with the second conductive type bonding pad through the second conductive type electrode wire;

the line-type electrode wire is an electrode connecting wire between diode units.

2. The forward-mounted integrated cell diode chip of claim 1, wherein the insulating dielectric layer is made of silicon dioxide, aluminum oxide, or silicon nitride.

3. A forward mounted integrated cell diode chip as claimed in claim 1, wherein said diode cells are connected in a manner such that: parallel connection, series connection or series-parallel connection mixing with set proportion.

4. The forward integrated cell diode chip of claim 1, wherein the diode cell is shaped as: triangle, square, rectangle, pentagon, hexagon, circle.

5. A forward mounted integrated cell diode chip as claimed in claim 1, wherein said diode cells are 2 to 1000 hundred million in number.

6. The forward integrated cell diode chip of claim 1, wherein the diode cell has a length along the Y-axis of 0.001 microns to 200 microns.

7. The forward-mounted integrated cell diode chip of claim 1, wherein the line-type electrode lines are arranged in a manner that: more than 1 first conductive type electrode wires surround the layout of the table top; or more than 1 second conductive type electrode wires surround the mesa layout; or the first conductive type electrode wires and the second conductive type electrode wires are distributed in equal quantity; or the first type electrode wires and the second type electrode wires are parallel and are in insulated overlapping layout in a vertical space, and insulating medium materials are arranged between the overlapping parts of the electrode wires with different conductive types; or the first conductive type electrode wires and the second conductive type electrode wires are in insulated vertical crossing layout, and insulating medium materials are arranged between crossing parts of the different conductive type electrode wires; or the first conductive type electrode wires and the second conductive type electrode wires are partially or completely designed in a non-linear layout.

8. The forward-mounted integrated cell diode chip of claim 7, wherein the non-linear layout comprises a meander-line layout, a curved layout.

9. The forward-mounted integrated cell diode chip of claim 1, wherein the linear electrode wires are made of linear metal and/or indium tin oxide material; the wire-shaped metal material is aluminum, silver, titanium, nickel, gold, platinum, chromium or an alloy of any two or more of the above metals.

10. The forward-mounted integrated cell diode chip of claim 1, wherein the diode mesa structure comprises a hole structure.

11. The forward-mounted integrated cell diode chip of claim 1, wherein the diode mesa and the substrate have an intrinsic gallium nitride layer therebetween.

12. A face-mounted integrated cell diode chip as claimed in claim 10 wherein the substrate is located on the mirror.

13. The forward integrated cell diode chip of claim 12, wherein the mirror material is silver, aluminum, or a distributed bragg mirror.

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