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CN113036009B - A thin film vertically integrated unit diode chip - Google Patents

A thin film vertically integrated unit diode chip Download PDF

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CN113036009B
CN113036009B CN201911354891.XA CN201911354891A CN113036009B CN 113036009 B CN113036009 B CN 113036009B CN 201911354891 A CN201911354891 A CN 201911354891A CN 113036009 B CN113036009 B CN 113036009B
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CN113036009A (en
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闫春辉
蒋振宇
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Naweilang Technology Shenzhen Co ltd
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Shenzhen Third Generation Semiconductor Research Institute
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/81Bodies
    • H10H20/819Bodies characterised by their shape, e.g. curved or truncated substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/81Bodies
    • H10H20/816Bodies having carrier transport control structures, e.g. highly-doped semiconductor layers or current-blocking structures
    • H10H20/8162Current-blocking structures
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
    • H10H20/83Electrodes
    • H10H20/831Electrodes characterised by their shape
    • H10H20/8312Electrodes characterised by their shape extending at least partially through the bodies
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10HINORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80Constructional details
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Abstract

本发明提供一种薄膜垂直集成单元二极管芯片,包括:保护金属层,反射镜,第二导电类型层,第二导电类型电极,量子阱有源区,第一导电类型层,绝缘介质层,第一导电类型电极,及远离第一导电类型电极的一侧形成n个二极管台面结构和沟槽结构,沟槽结构位于二极管单元之间;相邻二极管单元在垂直于所述第二导电类型电极线延伸方向上的距离根据电流扩散长度确定。本发明提供的薄膜二极管芯片大大降低了二极管芯片厚度,提高了二极管芯片散热性能的同时解决了现有技术存在的二极管结构在流明效率、流明密度输出、流明成本三个重要的参数上极大局限性的技术问题,提高了单位面积芯片的流明输出,降低了流明成本。

Figure 201911354891

The invention provides a thin-film vertically integrated unit diode chip, comprising: a protective metal layer, a mirror, a second conductivity type layer, a second conductivity type electrode, a quantum well active region, a first conductivity type layer, an insulating medium layer, a A conductivity type electrode, and n diode mesa structures and trench structures are formed on the side away from the first conductivity type electrode, and the trench structures are located between the diode units; the adjacent diode units are perpendicular to the second conductivity type electrode line The distance in the extension direction is determined according to the current spreading length. The thin film diode chip provided by the invention greatly reduces the thickness of the diode chip, improves the heat dissipation performance of the diode chip, and solves the great limitation of the diode structure in the prior art on three important parameters of lumen efficiency, lumen density output and lumen cost Due to the technical problems, the lumen output per unit area of the chip is improved, and the lumen cost is reduced.

Figure 201911354891

Description

一种薄膜垂直集成单元二极管芯片A thin film vertically integrated unit diode chip

技术领域technical field

本发明涉及半导体材料和器件工艺领域,特别是半导体光电器件,更具体地,本发明涉及一种薄膜垂直集成单元二极管芯片。The present invention relates to the field of semiconductor materials and device technology, in particular to semiconductor optoelectronic devices, and more particularly, to a thin-film vertically integrated unit diode chip.

背景技术Background technique

常规的垂直结构LED芯片中,电流扩散主要依靠n电极侧,有电极引线型引线或钻孔型的引线,但总体电流扩散仍不均匀,导致发光效率的损失,散热也不均匀,从而影响单元二极管芯片的效率和稳定性。从而限制了垂直大功率LED芯片提供单位面积流明输出更高的产品。电流扩散的不均匀、热扩散的不均匀和光提取的不均匀,导致其在流明效率、流明密度输出、流明成本三个重要的参数上有极大的局限性,目前市场上的垂直LED芯片技术无法提供有效的解决方案。In conventional vertical structure LED chips, the current diffusion mainly depends on the n-electrode side, and there are electrode lead-type leads or drilled-type leads, but the overall current diffusion is still uneven, resulting in loss of luminous efficiency and uneven heat dissipation, thus affecting the unit. Efficiency and stability of diode chips. This limits the vertical high-power LED chips to provide products with higher lumen output per unit area. Uneven current spreading, uneven heat spreading, and uneven light extraction lead to great limitations in three important parameters: lumen efficiency, lumen density output, and lumen cost. The vertical LED chip technology currently on the market Unable to provide a valid solution.

现有技术一为Proc.of SPIE Vol.10021 100210X-1 2016会议论文,如图1-3所示,其中,图1为垂直LED芯片的结构图,其中P型电极与背面的电极相连(back metal Au),黑色部分边缘的方框与中间3根手指型引线代表了N型电极,通过下方的两个大的N型焊盘打线引出。因此整个芯片的电流扩散,主要为N型金属线所限制。The first prior art is the Proc.of SPIE Vol.10021 100210X-1 2016 conference paper, as shown in Figure 1-3, wherein Figure 1 is a structural diagram of a vertical LED chip, wherein the P-type electrode is connected to the back electrode (back metal Au), the box on the edge of the black part and the three finger-shaped leads in the middle represent the N-type electrodes, which are led out through the two large N-type pads below. Therefore, the current spreading of the entire chip is mainly limited by the N-type metal wires.

图2展示了现有技术一的垂直芯片的近场分析图和中线上归一化的电流分布图,芯片的尺寸为1.2mm×1.2mm。近场图中可见,芯片的电流分布仍然十分不均匀,靠近n电极线的区域光强很大,电流密度大,而远离N电极线的区域光强较小,电流密度小。归一化的分布图显示,电流密度较小的区域不到较大区域的70%。因此,大电流下的LED光效、散热和稳定性都会受到严重的限制。FIG. 2 shows the near-field analysis diagram and the normalized current distribution diagram on the center line of the vertical chip of the prior art, and the size of the chip is 1.2 mm×1.2 mm. It can be seen from the near-field image that the current distribution of the chip is still very uneven. The area close to the n-electrode line has high light intensity and high current density, while the area far from the n-electrode line has low light intensity and low current density. The normalized profile shows that the regions with smaller current density are less than 70% of the larger regions. Therefore, LED light efficiency, heat dissipation and stability under high current are severely limited.

发明内容SUMMARY OF THE INVENTION

本发明为解决现有技术存在的二极管结构流明效率、流明密度输出、流明成本三个重要的参数上有极大局限性的技术问题,提出一种流明效率高、流明密度输出大的集成单元二极管。The present invention proposes an integrated unit diode with high lumen efficiency and high lumen density output in order to solve the technical problem that the three important parameters of diode structure lumen efficiency, lumen density output and lumen cost existing in the prior art have great limitations. .

为实现上述目的,本发明提供一种薄膜垂直集成单元二极管芯片,包括:保护金属层,反射镜,第二导电类型层,第二导电类型电极,量子阱有源区,第一导电类型层,绝缘介质层,第一导电类型电极,及远离第一导电类型电极的一侧形成n个二极管台面结构和沟槽,第二导电类型电极线沿所述第二导电类型层之上的沟槽延伸,所述延伸的第二导电类型电极线之间形成n个二极管单元台面结构,其中,n≥2;沟槽位于二极管单元之间;其中,相邻二极管单元的N型导电电极在垂直于电极线延伸方向上的距离小于横向临界电流扩散长度,所述横向临界电流扩散长度为与二极管单元的“工作电压(VF)-单元尺寸”曲线上的拐点所对应的电流扩散长度。In order to achieve the above object, the present invention provides a thin film vertically integrated unit diode chip, comprising: a protective metal layer, a mirror, a second conductivity type layer, a second conductivity type electrode, a quantum well active region, a first conductivity type layer, The insulating dielectric layer, the first conductivity type electrode, and the side away from the first conductivity type electrode form n diode mesa structures and trenches, and the second conductivity type electrode lines extend along the trenches above the second conductivity type layer , n diode unit mesa structures are formed between the extended electrode lines of the second conductivity type, where n≥2; the trenches are located between the diode units; wherein, the N-type conductive electrodes of adjacent diode units are perpendicular to the electrodes The distance in the direction of line extension is less than the lateral critical current spreading length, which is the current spreading length corresponding to the inflection point on the "operating voltage (VF) - cell size" curve of the diode cell.

优选的,所述横向临界电流扩散长度小于70微米。Preferably, the lateral critical current diffusion length is less than 70 microns.

优选的,采用激光剥离或化学蚀刻的方式移除芯片的生长衬底。Preferably, the growth substrate of the chip is removed by means of laser lift-off or chemical etching.

优选的,所述二极管单元之间的沟槽横截面形状为三角形、四边形、弧形、同心圆环、十字形。Preferably, the cross-sectional shapes of the grooves between the diode units are triangles, quadrilaterals, arcs, concentric rings, and crosses.

优选的,所述沟槽宽度为0.5纳米-10微米,深度为0.5纳米-10微米。Preferably, the width of the groove is 0.5 nanometers to 10 micrometers, and the depth is 0.5 nanometers to 10 micrometers.

优选的,所述二极管台面结构内的n个二极管单元沿沟槽底部向上的垂直方向上,并垂直于所述第二导电类型电极延伸方向上的截面面积不变或逐渐缩小。Preferably, the cross-sectional areas of the n diode units in the diode mesa structure along the vertical direction upward from the bottom of the trench and perpendicular to the extending direction of the electrode of the second conductivity type remain unchanged or gradually decrease.

优选的,所述二极管单元均匀或非均匀排布在芯片上。Preferably, the diode units are uniformly or non-uniformly arranged on the chip.

优选的,第二导电类型电极线从n个二极管单元第一端面延伸至第二端面,或所述第二导电类型电极线从部分二极管单元第一端面延伸至第二端面。Preferably, the electrode lines of the second conductivity type extend from the first end faces to the second end faces of the n diode units, or the second conductivity type electrode wires extend from the first end faces to the second end faces of some of the diode units.

优选的,所述第二导电类型电极线与n个二极管单元顶部欧姆接触。Preferably, the electrode lines of the second conductivity type are in ohmic contact with the tops of the n diode units.

优选的,第二导电类型焊盘与第二导电类型电极线连接;所述第二导电类型电极线为线条形电极线。Preferably, the second conductive type pad is connected to the second conductive type electrode line; the second conductive type electrode line is a strip-shaped electrode line.

优选的,所述线条形电极线布局方式为部分或全部设计采用直线布局。Preferably, the linear electrode line layout is partially or completely designed using a linear layout.

优选的,所述线条形电极线布局方式为部分或全部设计采用非直线布局,所述非直线布局包括折线布局,曲线布局。Preferably, the linear electrode line layout is partially or completely designed to adopt a non-linear layout, and the non-linear layout includes a broken line layout and a curved layout.

优选的,还包括第一导电类型焊盘、第二导电类型焊盘,其中第一导电类型焊盘与第二导电类型焊盘在芯片同一侧,第一导电类型电极与第一导电类型焊盘连接,第二导电类型电极与第二导电类型焊盘连接,所述第一导电类型焊盘个数及所述第二导电类型焊盘个数大于或等于1。Preferably, it also includes a first conductivity type pad and a second conductivity type pad, wherein the first conductivity type pad and the second conductivity type pad are on the same side of the chip, and the first conductivity type electrode and the first conductivity type pad The second conductive type electrode is connected to the second conductive type pad, and the number of the first conductive type pad and the number of the second conductive type pad is greater than or equal to 1.

优选的,所述第一导电类型焊盘及所述第二导电类型焊盘形状为:半圆形,圆形,矩形,三角形。Preferably, the shapes of the first conductive type pad and the second conductive type pad are: semicircle, circle, rectangle, triangle.

优选的,所述第一导电类型焊盘及所述第二导电类型焊盘厚度为0.001微米~20微米;所述第一导电类型焊盘宽度为:10微米~100微米。Preferably, the thickness of the first conductive type pad and the second conductive type pad is 0.001 micrometers to 20 micrometers; the width of the first conductive type pads is 10 micrometers to 100 micrometers.

优选的,所述第一导电类型焊盘及所述第二导电类型焊盘位于所述芯片平面任意边沿、芯片平面顶点、芯片平面中间或芯片其它任意位置。Preferably, the first conductive type pad and the second conductive type pad are located at any edge of the chip plane, at the apex of the chip plane, in the middle of the chip plane, or at any other position on the chip.

优选的,所述n个二极管单元包括电流阻挡层和保护金属层,所述保护金属层内设置反射镜,所述电流阻挡层嵌置于保护金属层与反射镜内。Preferably, the n diode units include a current blocking layer and a protective metal layer, a mirror is arranged in the protective metal layer, and the current blocking layer is embedded in the protective metal layer and the mirror.

优选的,所述第二导电类型电极与第二导电类型层接触长度小于电流阻挡层长度;所述第二导电类型电极与第二导电类型层接触长度为0.001微米-30微米;所述电流阻挡层长度为0.001微米-30微米。Preferably, the contact length between the second conductivity type electrode and the second conductivity type layer is less than the length of the current blocking layer; the contact length between the second conductivity type electrode and the second conductivity type layer is 0.001 μm-30 μm; the current blocking layer Layer lengths range from 0.001 microns to 30 microns.

优选的,所述绝缘介质层和电流阻挡层材料为二氧化硅、氧化铝、氮化硅中任一种或三种绝缘材料的组合。Preferably, the materials of the insulating dielectric layer and the current blocking layer are any one of silicon dioxide, aluminum oxide, and silicon nitride, or a combination of three insulating materials.

优选的,所述二极管单元形状为:三角形、正方形、长方形、五边形、六边形、圆形、其他任意自定义形状。Preferably, the diode unit shapes are: triangles, squares, rectangles, pentagons, hexagons, circles, and any other custom shapes.

优选的,所述n个二极管单元沿平行于所述第二导电类型电极线延伸方向长度为L0,L1,L2,…Lx,…Ln;所述L0≥L1≥L2≥…Lx…≥Ln;所述n个二极管单元沿垂直于所述第二导电类型电极线延伸方向从中间往两边宽度为W0,W1,W2,…Wy,…Wn,其中W0≥W1≥W2≥…Wy…≥Wn。本发明所采用的薄膜垂直集成单元二极管芯片,通过纳微米尺寸结构效应,在光、电、热三个层面突破现有垂直LED技术的局限性。单元二极管芯片的尺寸设计控制在电流扩散长度以内,其较高自由度的几何优化设计方式,可同时解决困扰LED单元二极管芯片设计的n-电极和p-电极电流扩散不均匀的问题,从而得到更高的光电转换效率/流明效率;每个二极管单元的纳米微结构、及台面内部的孔结构以及沟槽结构可增加有效出光面积,从而提升光提取效率;采用激光剥离或化学蚀刻的方式削薄或移除衬底,极大的减小了芯片厚度。集成单元二极管芯片的薄膜衬底、尺寸的缩小和台面内部的孔结构,带来更大的散热面积,具备更佳的散热性能,可以允许超大电流密度的注入而不影响其稳定性,从而提高单位面积集成单元二极管芯片的流明输出,降低流明成本。Preferably, the lengths of the n diode units along the extending direction parallel to the electrode lines of the second conductivity type are L 0 , L 1 , L 2 ,...L x ,...L n ; the L 0 ≥L 1 ≥L 2 ≥...L x ...≥L n ; the widths of the n diode units are W 0 , W 1 , W 2 ,...W y ,... W from the middle to the two sides along the extending direction perpendicular to the second conductive type electrode lines n , where W 0 ≥W 1 ≥W 2 ≥...Wy... ≥Wn . The thin film vertically integrated unit diode chip used in the present invention breaks through the limitations of the existing vertical LED technology at the three levels of light, electricity and heat through the effect of nano-micron size structure. The size design of the unit diode chip is controlled within the current diffusion length, and the geometric optimization design method with high degree of freedom can simultaneously solve the problem of uneven current diffusion of the n-electrode and p-electrode that plagues the design of the LED unit diode chip. Higher photoelectric conversion efficiency/lumen efficiency; the nano-microstructure of each diode unit, as well as the hole structure and trench structure inside the mesa can increase the effective light extraction area, thereby improving the light extraction efficiency; laser lift-off or chemical etching is used to cut Thinning or removing the substrate greatly reduces the chip thickness. The thin film substrate of the integrated unit diode chip, the reduction in size and the hole structure inside the mesa bring a larger heat dissipation area and better heat dissipation performance, which can allow the injection of ultra-large current density without affecting its stability, thereby improving the The lumen output of the integrated unit diode chip per unit area reduces the lumen cost.

附图说明Description of drawings

图1是现有技术的二极管单元结构图。FIG. 1 is a structural diagram of a diode unit in the prior art.

图2是现有技术的二极管单元结构图。FIG. 2 is a structural diagram of a diode unit in the prior art.

图3是本发明实施例1提供的二极管台面结构的俯视图。3 is a top view of the diode mesa structure provided in Embodiment 1 of the present invention.

图4是本发明实施例1提供的二极管台面结构的俯视图。4 is a top view of the diode mesa structure provided in Embodiment 1 of the present invention.

图5是本发明实施例2提供的二极管台面结构的剖视图。5 is a cross-sectional view of a diode mesa structure provided in Embodiment 2 of the present invention.

图6是本发明实施例3提供的薄膜垂直集成单元二极管芯片的三维图。FIG. 6 is a three-dimensional diagram of a thin-film vertically integrated unit diode chip provided in Embodiment 3 of the present invention.

图7是本发明实施例3提供的二极管单元侧壁示意图。FIG. 7 is a schematic diagram of a sidewall of a diode unit provided in Embodiment 3 of the present invention.

图8是本发明实施例3提供的二极管单元俯视图。FIG. 8 is a top view of the diode unit provided in Embodiment 3 of the present invention.

图9是本发明实施例4提供的二极管台面结构的俯视图。FIG. 9 is a top view of the diode mesa structure provided in Embodiment 4 of the present invention.

图10是本发明实施例4提供的二极管台面结构的俯视图。FIG. 10 is a top view of the diode mesa structure provided in Embodiment 4 of the present invention.

图11是本发明实施例5提供的二极管台面结构的俯视图。11 is a top view of the diode mesa structure provided in Embodiment 5 of the present invention.

图12是本发明实施例5提供的二极管台面结构的俯视图。FIG. 12 is a top view of the diode mesa structure provided in Embodiment 5 of the present invention.

图13是本发明实施例6提供的二极管台面结构的俯视图。FIG. 13 is a top view of the diode mesa structure provided in Embodiment 6 of the present invention.

图14是本发明实施例6提供的二极管台面结构的俯视图。FIG. 14 is a top view of the diode mesa structure provided in Embodiment 6 of the present invention.

图15是本发明实施例6提供的二极管台面结构的俯视图。FIG. 15 is a top view of the diode mesa structure provided in Embodiment 6 of the present invention.

图16是本发明实施例7提供的二极管单元侧视图。FIG. 16 is a side view of the diode unit provided in Embodiment 7 of the present invention.

图17是本发明实施例7提供的二极管单元示意图。FIG. 17 is a schematic diagram of a diode unit provided in Embodiment 7 of the present invention.

图18是工作电压VF-单元尺寸关系曲线示意图Fig. 18 is a schematic diagram showing the relationship between working voltage VF and cell size

图19是本发明所实现的VF降低效果示意图19 is a schematic diagram of the VF reduction effect achieved by the present invention

第二导电类型电极1,绝缘介质层2,第二导电类型层3,量子阱有源区(MQWs)4,第一导电类型层5,二极管台面结构6,沟槽结构7,二极管单元8,第二导电类型电极线9,孔结构10,保护金属层11,反射镜12。Second conductivity type electrode 1, insulating dielectric layer 2, second conductivity type layer 3, quantum well active region (MQWs) 4, first conductivity type layer 5, diode mesa structure 6, trench structure 7, diode cell 8, The second conductivity type electrode line 9 , the hole structure 10 , the protective metal layer 11 , and the mirror 12 .

具体实施方式Detailed ways

下面结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例,都属于本发明保护范围。The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

在一优选实施方式中,电流扩散的长度具体为横向临界电流扩散长度;In a preferred embodiment, the length of the current spreading is specifically the lateral critical current spreading length;

其中,所述横向临界电流扩散长度为与发光二极管单元的“工作电压(VF)-单元尺寸”曲线上的拐点所对应的电流扩散长度。当小于这个临界值时,芯片的性能开始有巨大的提升。Wherein, the lateral critical current spreading length is the current spreading length corresponding to the inflection point on the "operating voltage (VF) - cell size" curve of the light emitting diode unit. When it is less than this critical value, the performance of the chip begins to have a huge improvement.

可以定义芯片及各二极管单元的包括的尺寸,芯片的长宽高分别为XYZ,单元尺寸则以abc表示。具体原理如图18所示,cell size100μm指的是市场上常规的LED芯片结构,cell size指的是N-P电极的间距分别为:X=72,60,50,40,30μm。不同颜色的曲线代表不同驱动电流。因为通常市场对于LED芯片的工作电压要求为VF<3.3V,因此目前的常规LED芯片只有在150mA下的驱动电流下可以满足条件。而随着横向电流扩散长度的缩小,小于72μm时,VF开始快速减少,因此我们可以定义72微米为设计中的临界横向电流扩散长度,当小于这个临界值时,芯片的性能开始有巨大的提升。比如到50微米的尺寸时,驱动电流在300mA下VF<3.3V,因此新的设计可以允许超过目前常规芯片的驱动电流(超驱100%),从而极大的提升芯片的流明密度。The included dimensions of the chip and each diode unit can be defined. The length, width and height of the chip are XYZ respectively, and the unit size is represented by abc. The specific principle is shown in Figure 18. The cell size of 100 μm refers to the conventional LED chip structure on the market, and the cell size refers to the spacing of the N-P electrodes: X=72, 60, 50, 40, and 30 μm. Curves with different colors represent different drive currents. Because the working voltage of LED chips is usually required by the market to be VF<3.3V, the current conventional LED chips can only meet the conditions under the driving current of 150mA. With the shrinking of the lateral current diffusion length, when it is less than 72μm, the VF begins to decrease rapidly, so we can define 72 μm as the critical lateral current diffusion length in the design. When it is less than this critical value, the performance of the chip begins to have a huge improvement. . For example, when the size is 50 microns, the driving current is VF<3.3V at 300mA, so the new design can allow the driving current to exceed the current conventional chip (overdrive 100%), thereby greatly improving the lumen density of the chip.

图19则示出了上述设置方式对VF的改善效果,由此定义一个临界电流扩散长度,L<72μm,在这样的设计下,由于VF的降低,可以获得能量效率更高的LED芯片;由于VF的降低,能量转换效率的提升,同时热效应也会随之降低,从而获得稳定性更佳的芯片;并且由于电流扩散均匀性的改善,芯片可以承受更高的驱动电流,从而极大的提升芯片的流明密度。Figure 19 shows the improvement effect of the above setting on VF, which defines a critical current diffusion length, L<72μm, under such a design, due to the reduction of VF, LED chips with higher energy efficiency can be obtained; The reduction of VF, the improvement of energy conversion efficiency, and the reduction of thermal effect will also result in a chip with better stability; and due to the improvement of the uniformity of current spreading, the chip can withstand higher driving current, which greatly improves the The lumen density of the chip.

一种薄膜垂直集成单元二极管芯片,包括:A thin film vertically integrated unit diode chip, comprising:

第一导电类型电极,第二导电类型电极,及远离第一导电类型电极的一侧形成n个二极管台面结构和沟槽结构,所述第二导电类型电极线沿所述第二导电类型层之上的沟槽延伸,所述延伸的第二导电类型电极线之间形成n个二极管单元台面结构,其中,n≥2;沟槽结构位于二极管单元之间。The first conductivity type electrode, the second conductivity type electrode, and the side away from the first conductivity type electrode form n diode mesa structures and trench structures, and the second conductivity type electrode line is along the second conductivity type layer. The trenches are extended, and n diode unit mesa structures are formed between the extended electrode lines of the second conductivity type, where n≧2; the trench structures are located between the diode units.

二极管台面结构还包括第一导电类型层,第二导电类型层,及位于所述第一导电类型层上的量子阱有源区,其中所述沟槽结构深度小于或等于第二导电类型层厚度;相邻二极管单元的垂直于所述第二导电类型电极线延伸方向上的距离小于横向临界电流扩散长度。The diode mesa structure further includes a first conductivity type layer, a second conductivity type layer, and a quantum well active region on the first conductivity type layer, wherein the depth of the trench structure is less than or equal to the thickness of the second conductivity type layer ; The distance between adjacent diode units perpendicular to the extending direction of the electrode lines of the second conductivity type is less than the lateral critical current diffusion length.

n个二极管单元沿沟槽底部向上的垂直方向上,并垂直于所述第二导电类型电极延伸方向上的截面面积逐渐缩小。The cross-sectional area of the n diode units is gradually reduced along the vertical direction upward from the bottom of the trench and perpendicular to the extending direction of the second conductive type electrode.

二极管单元之间的沟槽形状为四边形、同心圆环、十字形及其它任意曲线形状,沟槽横截面形状为三角形、四边形、弧形以及其它任意定义形状,沟槽水平方向不均匀分布或均匀分布,水平方向不均匀分布包括等距和非等距周期性分布,或等距和非等距非周期性分布。The shape of the groove between the diode units is quadrilateral, concentric ring, cross and other arbitrary curved shapes, the cross-sectional shape of the groove is triangle, quadrilateral, arc and other arbitrarily defined shapes, and the horizontal direction of the groove is unevenly distributed or uniform. Distribution, horizontally uneven distribution includes equidistant and non-equidistant periodic distribution, or equidistant and non-equidistant non-periodic distribution.

二极管单元的侧壁与水平面夹角α大于0度且小于等于90度,侧壁形状为梯形、四边形、曲面以及其它任意定义形状。二极管单元至少有一个侧壁面从芯片底部到顶部方向上有沟槽分布,沟槽截面形状为三角形、四边形、弧形以及其它任意定义形状,沟槽水平方向不均匀分布或均匀分布,沟槽水平方向不均匀分布分布包括等距和非等距周期性分布,或等距和非等距非周期性分布,沟槽宽度为0.5纳米-1微米,深度为0.5纳米-1微米。The angle α between the side wall of the diode unit and the horizontal plane is greater than 0 degree and less than or equal to 90 degrees, and the shape of the side wall is a trapezoid, a quadrilateral, a curved surface and other arbitrary defined shapes. The diode unit has at least one sidewall surface with grooves distributed from the bottom to the top of the chip. The cross-sectional shape of the grooves is triangle, quadrilateral, arc and other arbitrary defined shapes. The horizontal direction of the grooves is unevenly distributed or evenly distributed, and the grooves are horizontal The directional non-uniform distribution distribution includes equidistant and non-equidistant periodic distribution, or equidistant and non-equidistant non-periodic distribution, and the groove width is 0.5 nanometers to 1 micrometer and the depth is 0.5 nanometers to 1 micrometer.

一种薄膜垂直集成单元二极管芯片包括电极线;所述电极线为二极管单元间电极连接线;所述电极连接线为线条型电极线。二极管台面结构包括孔结构。A thin film vertically integrated unit diode chip includes electrode lines; the electrode lines are electrode connecting lines between diode units; and the electrode connecting lines are line-shaped electrode lines. The diode mesa structure includes a hole structure.

所述二极管单元形状为:三角形、正方形、长方形、五边形、六边形、圆形、任意自定义形状,所述二极管台面结构内的二极管单元数量为2个~1000亿个,二极管单元沿第二导电类型电极线延伸方向长度为0.001微米~1微米,二极管台面结构内的二极管单元按照均匀的对称排列分布,二极管单元大小不等,不均匀分布设置。The shape of the diode unit is: triangle, square, rectangle, pentagon, hexagon, circle, and any custom shape. The number of diode units in the diode mesa structure is 2 to 100 billion. The extension direction length of the electrode lines of the second conductivity type is 0.001 micrometers to 1 micrometers. The diode units in the diode mesa structure are arranged and distributed uniformly and symmetrically.

实施例1Example 1

本实施例提供一种薄膜垂直集成单元二极管芯片,包括:第二导电类型电极1,二极管单元台面组成的整体台面结构,沟槽和二极管单元8和第二导电类型电极线9。This embodiment provides a thin film vertically integrated unit diode chip, including: a second conductivity type electrode 1 , an integral mesa structure composed of a diode unit mesa, a trench and a diode unit 8 and a second conductivity type electrode line 9 .

如图3所示,整体台面结构包括6排共102个相等大小,均匀分布的三角形二极管单元,二极管单元沿第二导电类型电极线延伸方向长度为0.1微米。二极管单元台面结构采用三角形排列,相邻单元第二导电类型电极线9间距小于横向临界电流扩散长度。二极管单元形状为三角形,按照均匀的对称排列分布。电极线为二极管单元间电极连接线,电极线的宽度为0.001-2微米,厚度为0.001-1微米。As shown in FIG. 3 , the overall mesa structure includes 6 rows of 102 triangular diode units of equal size and uniform distribution, and the length of the diode units along the extending direction of the electrode lines of the second conductivity type is 0.1 μm. The diode unit mesa structure adopts a triangular arrangement, and the distance between the electrode lines 9 of the second conductivity type of adjacent units is smaller than the lateral critical current diffusion length. The diode cells are triangular in shape and distributed in a uniform symmetrical arrangement. The electrode lines are electrode connecting lines between diode units, the width of the electrode lines is 0.001-2 micrometers, and the thickness is 0.001-1 micrometers.

如图4所示,整体台面结构包括6排共52个等大小均匀分布的正方形二极管单元,二极管单元沿第二导电类型电极线延伸方向长度为0.5微米。二极管单元台面结构采用长方形排列,相邻单元第二导电类型电极线9间距小于横向临界电流扩散长度。二极管单元形状为正方形,按照均匀的对称排列分布。电极线为二极管单元间电极连接线,电极线的宽度为0.001-20微米,厚度为0.001-10微米。As shown in FIG. 4 , the overall mesa structure includes 6 rows of 52 square diode units of equal size and uniform distribution, and the length of the diode units along the extending direction of the electrode lines of the second conductivity type is 0.5 μm. The diode unit mesa structure is arranged in a rectangular shape, and the distance between the electrode lines 9 of the second conductivity type of adjacent units is smaller than the lateral critical current diffusion length. The diode cells are square in shape and distributed in a uniform symmetrical arrangement. The electrode lines are electrode connecting lines between diode units, the width of the electrode lines is 0.001-20 microns, and the thickness is 0.001-10 microns.

如图4所示每个二极管单元增设孔结构10,孔结构包括一个孔单元,孔单元为圆形孔单元直径为1nm~0.2微米。孔单元对称排列,非对称排列,周期性排列,非周期性排列或随机排列。孔单元形状还可以为三角形、正方形、长方形、五边形、六边形、圆形、以及其它任意定义形状,并不局限于图4中展示的形状。As shown in FIG. 4 , a hole structure 10 is added to each diode unit. The hole structure includes one hole unit, and the hole unit is a circular hole unit with a diameter of 1 nm˜0.2 μm. Pore cells are arranged symmetrically, asymmetrically, periodically, aperiodically or randomly. The shape of the hole unit can also be a triangle, a square, a rectangle, a pentagon, a hexagon, a circle, and any other defined shape, and is not limited to the shape shown in FIG. 4 .

本实施例提供三种薄膜垂直集成单元发光二极管台面结构设计,通过灵活地改变二极管台面结构的尺寸、形状,可以获得指定工作电流下最佳的电流扩散和散热性能,并极大的提升芯片的注入电流密度,从而提升单位面积的流明输出。This embodiment provides three designs of thin-film vertical integrated unit light-emitting diode mesa structures. By flexibly changing the size and shape of the diode mesa structure, the best current diffusion and heat dissipation performance under a specified operating current can be obtained, and the chip performance can be greatly improved. The current density is injected, thereby increasing the lumen output per unit area.

实施例2Example 2

本实施例提供一种薄膜垂直集成单元二极管芯片,如图5所示,第一导电类型层5,第二导电类型层3,位于所述第一导电类型层上的量子阱有源区4,第二导电类型电极1,绝缘介质层2,金属保护层11和反射镜12。在一种应用中,第一导电类型层为P型氮化镓层,第二导电类型层为N型氮化镓层,第二导电类型电极为n电极,沟槽深度刻蚀至保护金属层11上。沟槽深度也可刻蚀至N型氮化镓层、量子阱有源区或P型氮化镓层内,并不局限于图5所示。This embodiment provides a thin-film vertically integrated unit diode chip. As shown in FIG. 5 , a first conductivity type layer 5 , a second conductivity type layer 3 , a quantum well active region 4 located on the first conductivity type layer, The second conductive type electrode 1 , the insulating medium layer 2 , the metal protection layer 11 and the mirror 12 . In one application, the first conductivity type layer is a p-type gallium nitride layer, the second conductivity type layer is an n-type gallium nitride layer, the second conductivity type electrode is an n-electrode, and the trench is etched to a depth of the protective metal layer 11 on. The depth of the trench can also be etched into the N-type gallium nitride layer, the quantum well active region or the P-type gallium nitride layer, which is not limited to that shown in FIG. 5 .

所述薄膜垂直集成单元二极管芯片的生长衬底通过激光剥离或化学蚀刻的方式移除,所述移除衬底的薄膜垂直集成单元二极管芯片厚度为8微米。The growth substrate of the thin film vertically integrated unit diode chip is removed by means of laser lift-off or chemical etching, and the thickness of the thin film vertically integrated unit diode chip of the removed substrate is 8 microns.

实施例3Example 3

本实施例提供一种薄膜垂直集成单元二极管芯片,如图6所示,芯片包括4排共30个等大小均匀分布的梯形二极管单元,二极管单元沿第二导电类型电极线延伸方向长度为0.01微米。相邻单元第二导电类型电极线间距小于电流注入的扩散长度。二极管单元形状为梯形,按照均匀的对称排列分布。二极管单元侧壁与水平面夹角角度大于0度且小于等于90度,二极管单元的侧壁形状为梯形。This embodiment provides a thin-film vertically integrated unit diode chip. As shown in FIG. 6 , the chip includes 4 rows of 30 trapezoidal diode units of equal size and uniform distribution, and the length of the diode units along the extension direction of the second conductivity type electrode line is 0.01 μm . The second conductive type electrode line spacing of adjacent cells is smaller than the diffusion length of the current injection. The diode cells are trapezoidal in shape and distributed in a uniform symmetrical arrangement. The angle between the side wall of the diode unit and the horizontal plane is greater than 0 degrees and less than or equal to 90 degrees, and the shape of the side wall of the diode unit is a trapezoid.

如图7所示,二极管单元有一个侧壁面从台面底部到顶部方向上有沟槽分布。二极管单元侧壁上的沟槽截面形状为三角形,侧壁上的沟槽宽度为0.5纳米-1微米,深度为0.5纳米-1微米。As shown in FIG. 7, the diode cell has a sidewall surface with trenches extending from the bottom to the top of the mesa. The cross-sectional shape of the trench on the sidewall of the diode unit is a triangle, the width of the trench on the sidewall is 0.5 nanometer-1 micrometer, and the depth is 0.5 nanometer-1 micrometer.

如图8所示,二极管单元四个侧壁上面台面底部到顶部方向上有沟槽分布,沟槽横截面形状为三角形时,侧壁沟槽宽度为0.5纳米-1微米,深度为0.5纳米-1微米。As shown in Figure 8, there are trenches distributed from the bottom to the top of the mesa on the four sidewalls of the diode unit. When the cross-sectional shape of the trench is a triangle, the width of the sidewall trench is 0.5nm-1µm, and the depth is 0.5nm- 1 micron.

实施例4Example 4

本实施例提供一种薄膜垂直集成单元二极管芯片,如图9所示,所述二极管台面结构包括6行共56个正方形二极管单元和沟槽结构7,沟槽结构位于二极管单元之间。所述二极管单元均匀分布在芯片平面内,二极管单元沿第二导电类型电极线延伸方向长度为10纳米-100纳米。每行二极管单元从靠近第二导电类型焊盘开始沿第二导电类型电极线延伸方向长度大小不等或相等。当不等时,定义其长度分别为L0,L1,L2,L3…Ln,其中二极管单元宽度满足L0>L1>L2>L3>…>LnThis embodiment provides a thin-film vertically integrated unit diode chip. As shown in FIG. 9 , the diode mesa structure includes 56 square diode units in 6 rows and a trench structure 7 , and the trench structure is located between the diode units. The diode units are uniformly distributed in the chip plane, and the length of the diode units along the extending direction of the electrode lines of the second conductivity type is 10 nanometers to 100 nanometers. The lengths of the diode units in each row along the extending direction of the electrode lines of the second conductivity type from close to the second conductivity type pad are different or equal in size. When they are not equal , their lengths are defined as L 0 , L 1 , L 2 , L 3 .

在一些优选的实施例中,二极管单元沿第二导电类型电极线延伸方向长度为2000微米;二极管单元沿第二导电类型电极线延伸方向长度为100微米;在另一些优选实施例中,二极管单元沿第二导电类型电极线延伸方向长度10微米;在另一些优选实施例中,二极管沿第二导电类型电极线延伸方向长度为1微米。In some preferred embodiments, the length of the diode unit along the extending direction of the electrode line of the second conductivity type is 2000 microns; the length of the diode unit along the extending direction of the electrode line of the second conductivity type is 100 microns; The length along the extending direction of the electrode line of the second conductivity type is 10 micrometers; in other preferred embodiments, the length of the diode along the extending direction of the electrode line of the second conductivity type is 1 micrometer.

如图10所示,芯片包括6行共16个大小相等的正方形以及40个长度相等宽度不等的两种长方形二极管单元和沟槽结构7,沟槽结构位于二极管单元之间。每一行的二极管单元大小相等,所述二极管单元均分布,每个二极管单元沿y轴方向宽度为10纳米-100纳米。二极管单元从中间位置开始,沿y轴方向宽度大小不等或相等。当不等时,定义其宽度从中间向两侧分别为W0,W1,W2,W3…Wm;其中二极管单元宽度满足W0>W1>W2>W3>…>WmAs shown in FIG. 10 , the chip includes 6 rows of 16 squares of equal size, 40 two kinds of rectangular diode cells with equal lengths and different widths, and trench structures 7 , and the trench structures are located between the diode cells. The diode units in each row are of equal size, the diode units are evenly distributed, and the width of each diode unit along the y-axis direction is 10 nanometers to 100 nanometers. The diode cells start from the middle and have unequal or equal widths along the y-axis. When they are not equal, the widths from the middle to the two sides are defined as W 0 , W 1 , W 2 , W 3 . m .

实施例5Example 5

本实施例提供一种薄膜垂直集成单元二极管芯片,如图11所示,括19列共22个大小部分相等的长方形二极管单元,呈均匀的对称排列分布,二极管单元沿第二导电类型电极线延伸方向的长度为50微米。二极管台面结构采用长方形排列,相邻单元n电极间距小于电流的扩散长度。第二导电类型电极线1与22个二极管单元顶部接触,接触面形状为矩形。第二导电类型电极线与每一列内的二极管单元之间的沟槽交叉垂直。第二导电类型焊盘个数为1,形状为一条边为弧形的不规则多边形,位于芯片平面短边边沿。第二导电类型焊盘厚度为1微米,宽度为50微米。This embodiment provides a thin-film vertically integrated unit diode chip. As shown in FIG. 11 , it includes 19 columns and a total of 22 rectangular diode units of equal size and part, which are uniformly symmetrically arranged and distributed. The diode units extend along the second conductivity type electrode line. The length of the direction is 50 microns. The diode mesa structure is arranged in a rectangular shape, and the distance between the n electrodes of adjacent units is smaller than the current diffusion length. The electrode line 1 of the second conductivity type is in contact with the top of the 22 diode units, and the shape of the contact surface is rectangular. The electrode lines of the second conductivity type are perpendicular to the trenches between the diode cells in each column. The number of the second conductive type pads is 1, and the shape is an irregular polygon with an arc-shaped side, which is located at the edge of the short side of the chip plane. The second conductive type pad has a thickness of 1 micrometer and a width of 50 micrometers.

如图12所示,包括7行85个大小相等,均匀排列的正方形二极管单元,二极管单元沿第二导电类型电极线延伸方向的长度为10微米。二极管台面结构采用长方形排列,台面结构的尺寸小于电流的扩散长度。第二导电类型电极线1与85个二极管单元顶部欧姆接触,接触面形状为矩形。第二导电类型电极线与每一行内的二极管单元之间的沟槽垂直。第二导电类型焊盘个数为1,形状为六边形,位于台面结构短边边沿。第二导电类型焊盘厚度为2微米,宽度为100微米。As shown in FIG. 12 , it includes 7 rows of 85 square diode units with equal size and uniform arrangement, and the length of the diode units along the extending direction of the electrode lines of the second conductivity type is 10 μm. The diode mesa structure is arranged in a rectangular shape, and the size of the mesa structure is smaller than the diffusion length of the current. The electrode line 1 of the second conductivity type is in ohmic contact with the top of the 85 diode units, and the shape of the contact surface is rectangular. The electrode lines of the second conductivity type are perpendicular to the trenches between the diode cells in each row. The number of the second conductive type pads is 1, the shape is hexagonal, and the pads are located at the short edge of the mesa structure. The second conductive type pad has a thickness of 2 microns and a width of 100 microns.

实施例6Example 6

本实施例提供一种薄膜垂直集成单元二极管芯片,包括:第二导电类型电极1,第二导电类型焊盘,第一导电类型焊盘,线条型电极线,二极管台面结构,二极管单元和沟槽。二极管台面结构包括6排共52个相等大小,均匀分布的正方形二极管单元,二极管单元沿第二导电类型电极线延伸方向长度为40微米。二极管台面结构采用正方形排列,二极管单元的连接方式为并联,台面结构的尺寸小于电流注入的扩散长度。二极管单元形状为长方形,按照均匀的对称排列分布。其中第二导电类型电极为n电极,第一导电类型焊盘为p焊盘,第二导电类型焊盘为n焊盘。This embodiment provides a thin film vertically integrated unit diode chip, including: a second conductivity type electrode 1, a second conductivity type pad, a first conductivity type pad, a line-type electrode line, a diode mesa structure, a diode cell and a trench . The diode mesa structure includes 6 rows of 52 square diode units of equal size and uniform distribution, and the length of the diode units along the extension direction of the electrode lines of the second conductivity type is 40 microns. The diode mesa structure adopts a square arrangement, the diode units are connected in parallel, and the size of the mesa structure is smaller than the diffusion length of the current injection. The diode unit is rectangular in shape and distributed in a uniform and symmetrical arrangement. The second conductivity type electrode is an n electrode, the first conductivity type pad is a p pad, and the second conductivity type pad is an n pad.

在一些优选的实施例中,二极管单元沿第二导电类型电极线延伸方向长度为100微米;在另一些优选实施例中,二极管单元沿第二导电类型电极线延伸方向长度10微米;在另一些优选实施例中,二极管沿第二导电类型电极线延伸方向长度为1微米。In some preferred embodiments, the length of the diode unit along the extension direction of the second conductivity type electrode line is 100 microns; in other preferred embodiments, the length of the diode unit along the extension direction of the second conductivity type electrode line is 10 microns; In a preferred embodiment, the length of the diode along the extending direction of the electrode line of the second conductivity type is 1 micrometer.

第一导电类型焊盘与第二导电类型焊盘在台面结构同一侧,第二导电类型电极1与第二导电类型焊盘由线条型电极线连接。The first conductive type pad and the second conductive type pad are on the same side of the mesa structure, and the second conductive type electrode 1 and the second conductive type pad are connected by line-shaped electrode lines.

如图13所示,第二导电类型焊盘和第一导电类型焊盘形状均为一条边为弧形的不规则多边形,第二导电类型焊盘和第一导电类型焊盘个数均为1,位于台面结构短边边沿。As shown in FIG. 13 , the shapes of the second conductivity type pads and the first conductivity type pads are both irregular polygons with an arc-shaped side, and the number of the second conductivity type pads and the first conductivity type pads are both 1 , located on the short edge of the mesa structure.

如图14所示,第二导电类型焊盘和第一导电类型焊盘形状均为一条边为弧形的不规则多边形,焊盘形状还可以为半圆形,圆形,矩形,三角形,不规则直线多边形,或其它一条或多条边为弧形的不规则多边形,并不局限于图14的展示。第二导电类型焊盘和第一导电类型焊盘个数均为1,第二导电类型焊盘位于台面结构短边边沿,第一导电类型焊盘位于台面结构长边边沿。As shown in FIG. 14 , the shape of the second conductivity type pad and the first conductivity type pad are both irregular polygons with an arc-shaped side, and the shape of the pads can also be semicircle, circle, rectangle, triangle, etc. Regular rectilinear polygons, or other irregular polygons whose one or more sides are arc-shaped, are not limited to those shown in FIG. 14 . The number of the second conductive type pad and the first conductive type pad is 1, the second conductive type pad is located on the short edge of the mesa structure, and the first conductive type pad is located on the long edge of the mesa structure.

如图15所示,第二导电类型焊盘为一条边为弧形的不规则多边形,位于台面结构短边边沿,第一导电类型焊盘形状为正六边形,位于台面顶点处。第二导电类型焊盘和第一导电类型焊盘个数均为1。As shown in FIG. 15 , the pad of the second conductivity type is an irregular polygon with an arc-shaped side, located at the short edge of the mesa structure, and the pad of the first conductivity type is a regular hexagon and is located at the vertex of the mesa. The numbers of the second conductive type pads and the first conductive type pads are both 1.

焊盘厚度为0.001微米~20微米,宽度为:10微米~100微米。电极线的宽度为0.001-20微米,厚度为0.001-10微米,电极线采用氧化铟锡材料,直线布局设计。沟槽的形状为十字形,横截面形状为长方形,水平方向均匀分布。The thickness of the pad is 0.001 micrometers to 20 micrometers, and the width is: 10 micrometers to 100 micrometers. The width of the electrode lines is 0.001-20 micrometers, and the thickness is 0.001-10 micrometers, the electrode lines are made of indium tin oxide material, and the linear layout is designed. The shape of the grooves is cross-shaped, the cross-sectional shape is rectangular, and the horizontal direction is evenly distributed.

实施例7Example 7

如图16和17所示,n个二极管单元包括第一导电类型层5,第二导电类型层3,位于所述第一导电类型层5与第二导电类型层3之间的量子阱有源区4,绝缘介质层2,电流阻挡层,反射镜,保护金属层,和背面电极16。其中第一导电类型层5为P型氮化镓层,第二导电类型层3为N型氮化镓层。保护金属层内设置反射镜,电流阻挡层一部分嵌置于反射镜内,另一部分嵌置于保护金属层内,电流阻挡层和反射镜上表面与P型氮化镓层接触。绝缘介质层2位于保护金属层上并与N型氮化镓层接触,n电极位于绝缘介质层2上,并与N型氮化镓层接触。电流阻挡层长度为1微米,n电极与N型氮化镓层接触长度为0.1微米,小于电流阻挡层长度。绝缘介质层和电流阻挡层材料为二氧化硅、氧化铝、氮化硅中任一种。反射镜材料为银、铝或分布式布拉格反射镜。保护金属层材料为铝、银、钛、镍、金、铂、铬、锡、钨。背面电极材料为铝、银、钛、镍、金、铂、铬、锡,或以上任意两种及以上的金属的合金。As shown in FIGS. 16 and 17 , the n diode units include a first conductivity type layer 5 , a second conductivity type layer 3 , and a quantum well active between the first conductivity type layer 5 and the second conductivity type layer 3 . Region 4, insulating dielectric layer 2, current blocking layer, mirror, protective metal layer, and back electrode 16. The first conductive type layer 5 is a P-type gallium nitride layer, and the second conductive type layer 3 is an N-type gallium nitride layer. A mirror is arranged in the protective metal layer, a part of the current blocking layer is embedded in the mirror, and the other part is embedded in the protective metal layer, and the current blocking layer and the upper surface of the mirror are in contact with the P-type gallium nitride layer. The insulating dielectric layer 2 is located on the protective metal layer and is in contact with the N-type gallium nitride layer, and the n-electrode is located on the insulating dielectric layer 2 and is in contact with the N-type gallium nitride layer. The length of the current blocking layer is 1 micrometer, and the contact length between the n electrode and the N-type gallium nitride layer is 0.1 micrometer, which is less than the length of the current blocking layer. The material of the insulating medium layer and the current blocking layer is any one of silicon dioxide, aluminum oxide, and silicon nitride. Mirror materials are silver, aluminum or distributed Bragg reflectors. The protective metal layer material is aluminum, silver, titanium, nickel, gold, platinum, chromium, tin, tungsten. The back electrode material is aluminum, silver, titanium, nickel, gold, platinum, chromium, tin, or an alloy of any two or more of the above metals.

由于二极管芯片的电流扩散长度与电流密度的平方根成反比,因此在大电流的注入下,电流的扩散长度更短,导致芯片的电流扩散更加的不均匀,效率更低,散热更加困难。采用薄膜垂直集成单元发光二极管结构设计,可以灵活的改变二极管台面结构的尺寸、形状,可以获得指定工作电流下最佳的电流扩散和散热性能,并极大的提升芯片的注入电流密度,从而提升单位面积的流明输出。Since the current diffusion length of the diode chip is inversely proportional to the square root of the current density, under the injection of a large current, the current diffusion length is shorter, resulting in more uneven current diffusion of the chip, lower efficiency, and more difficult heat dissipation. Using thin-film vertical integrated unit light-emitting diode structure design, the size and shape of the diode mesa structure can be flexibly changed, the best current diffusion and heat dissipation performance under the specified operating current can be obtained, and the injection current density of the chip can be greatly improved. Lumen output per unit area.

本发明的实施例提供的薄膜垂直集成单元发光二极管,具有以下有益效果:The thin-film vertically integrated unit light-emitting diode provided by the embodiment of the present invention has the following beneficial effects:

(1)本发明的相邻二极管单元n电极间距设计控制在电流扩散长度以内,优化的具备一定自由度的几何设计可以更进一步的提升出光效率,可同时解决困扰LED单元二极管芯片设计的第二导电类型电极和第一导电类型电极电流扩散不均匀的问题,从而得到更高的光电转换效率/流明效率;(1) The design of the n-electrode spacing of adjacent diode units in the present invention is controlled within the current diffusion length, and the optimized geometric design with a certain degree of freedom can further improve the light extraction efficiency, and can simultaneously solve the second problem that plagues the LED unit diode chip design. The problem of uneven current diffusion between the conductive type electrode and the first conductive type electrode, so as to obtain higher photoelectric conversion efficiency/lumen efficiency;

(2)本发明的每个二极管单元的微纳结构增加侧壁的出光面积,从而提升光萃取效率;(2) The micro-nano structure of each diode unit of the present invention increases the light emitting area of the sidewall, thereby improving the light extraction efficiency;

(3)本发明的集成单元二极管芯片尺寸的优化,带来更大的侧壁散热面积,具备更佳的散热性能,允许超大电流密度的注入而不影响其稳定性,极大的提高单位面积单元二极管芯片的流明输出,降低流明成本;(3) The optimization of the chip size of the integrated unit diode of the present invention brings a larger heat dissipation area of the sidewall, has better heat dissipation performance, allows the injection of a large current density without affecting its stability, and greatly improves the unit area. The lumen output of the unit diode chip reduces the lumen cost;

(4)本发明的集成单元二极管芯片的设计,可以实现超均匀的电流注入,因此而获得更高的效率、更好的波长均匀性、发光谱更窄的半高宽、更好的散热均匀性和更好的器件稳定性。(4) The design of the integrated unit diode chip of the present invention can realize ultra-uniform current injection, thereby obtaining higher efficiency, better wavelength uniformity, narrower half-width of the emission spectrum, and better heat dissipation uniformity. performance and better device stability.

(5)本发明的集成单元二极管芯片适于UVC、UVA、UVB、紫光、蓝光、绿光、黄光、红光、红外光等各色系的LED产品,可用于LED照明,背光,显示,植物照明,医疗和其它半导体发光器件应用领域。以上所述的具体实施例,对本发明的目的,技术方案和有益效果进行了进一步详细说明,所应理解的是,以上所述仅为本发明的具体实施例,并不用于限定本发明的保护范围,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。(5) The integrated unit diode chip of the present invention is suitable for LED products of various color systems such as UVC, UVA, UVB, purple light, blue light, green light, yellow light, red light, infrared light, etc., and can be used for LED lighting, backlight, display, plant Lighting, medical and other semiconductor light-emitting device applications. The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above-mentioned specific embodiments are only specific embodiments of the present invention, and are not intended to limit the protection of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (21)

1.一种薄膜垂直集成单元二极管芯片,其特征在于,所述二极管芯片依次包括:保护金属层、反射镜、第一导电类型层、量子阱有源区、第二导电类型层电极,所述二极管芯片还包括绝缘介质层、第一导电类型电极、第二导电类型电极及远离第一导电类型电极的一侧形成n个二极管台面结构和沟槽,第二导电类型电极线沿所述第一导电类型层之上的沟槽延伸,所述延伸的第二导电类型电极线之间形成n个二极管单元台面结构,其中,n≥2;沟槽位于二极管单元之间;1. a thin-film vertically integrated unit diode chip, characterized in that, the diode chip sequentially comprises: a protective metal layer, a mirror, a first conductivity type layer, a quantum well active region, a second conductivity type layer electrode, the The diode chip further includes an insulating medium layer, a first conductivity type electrode, a second conductivity type electrode, and a side away from the first conductivity type electrode to form n diode mesa structures and trenches, and the second conductivity type electrode line runs along the first conductivity type electrode. The trenches on the conductive type layer are extended, and n diode unit mesa structures are formed between the extended electrode lines of the second conductivity type, where n≥2; the trenches are located between the diode units; 其中,相邻二极管单元在垂直于所述第二导电类型电极线延伸方向上的距离小于横向临界电流扩散长度,所述横向临界电流扩散长度为与二极管单元的“工作电压(VF)-单元尺寸”曲线上的拐点所对应的电流扩散长度。Wherein, the distance between adjacent diode units in the direction perpendicular to the extension direction of the second conductivity type electrode line is less than the lateral critical current diffusion length, and the lateral critical current diffusion length is equal to the “operating voltage (VF) of the diode unit-cell size. ” is the current spreading length corresponding to the inflection point on the curve. 2.如权利要求1所述的薄膜垂直集成单元二极管芯片,其特征在于,所述横向临界电流扩散长度小于70微米。2 . The thin film vertically integrated unit diode chip of claim 1 , wherein the lateral critical current diffusion length is less than 70 μm. 3 . 3.一种如权利要求1所述的薄膜垂直集成单元二极管芯片,其特征在于,采用激光剥离或化学蚀刻的方式移除芯片的生长衬底。3 . The thin-film vertically integrated unit diode chip according to claim 1 , wherein the growth substrate of the chip is removed by means of laser lift-off or chemical etching. 4 . 4.一种如权利要求1所述的薄膜垂直集成单元二极管芯片,其特征在于,所述二极管单元之间的沟槽横截面形状为三角形、四边形、弧形、同心圆环、十字形。4 . The thin-film vertically integrated unit diode chip according to claim 1 , wherein the cross-sectional shapes of the trenches between the diode units are triangles, quadrilaterals, arcs, concentric rings, and crosses. 5 . 5.一种如权利要求1所述的薄膜垂直集成单元二极管芯片,其特征在于,所述沟槽宽度为0.5纳米-10微米,深度为0.5纳米-10微米。5 . The thin-film vertically integrated unit diode chip according to claim 1 , wherein the trench has a width of 0.5 nanometers to 10 micrometers and a depth of 0.5 nanometers to 10 micrometers. 6 . 6.一种如权利要求1所述的薄膜垂直集成单元二极管芯片,其特征在于,所述二极管台面结构内的n个二极管单元沿沟槽底部向上的垂直方向上,并垂直于所述第二导电类型电极延伸方向上的截面面积不变或逐渐缩小。6 . The thin-film vertically integrated unit diode chip according to claim 1 , wherein the n diode units in the diode mesa structure are in a vertical direction up from the bottom of the trench and perpendicular to the second The cross-sectional area in the extending direction of the conductive type electrode is unchanged or gradually reduced. 7.一种如权利要求1所述的薄膜垂直集成单元二极管芯片,其特征在于,所述二极管单元均匀或非均匀排布在芯片上。7 . The thin-film vertically integrated unit diode chip of claim 1 , wherein the diode units are uniformly or non-uniformly arranged on the chip. 8 . 8.一种如权利要求1所述的薄膜垂直集成单元二极管芯片,其特征在于,第二导电类型电极线从n个二极管单元第一端面延伸至第二端面,或所述第二导电类型电极线从部分二极管单元第一端面延伸至第二端面。8 . The thin-film vertically integrated unit diode chip according to claim 1 , wherein the electrode lines of the second conductivity type extend from the first end face of the n diode units to the second end face, or the second conductivity type electrode. 9 . A line extends from the first end face to the second end face of the portion of the diode cell. 9.一种如权利要求8所述的薄膜垂直集成单元二极管芯片,其特征在于,所述第二导电类型电极线与n个二极管单元顶部欧姆接触。9 . The thin-film vertically integrated unit diode chip of claim 8 , wherein the electrode lines of the second conductivity type are in ohmic contact with the tops of the n diode units. 10 . 10.一种如权利要求9所述的薄膜垂直集成单元二极管芯片,其特征在于,第二导电类型焊盘与第二导电类型电极线连接;所述第二导电类型电极线为线条形电极线。10 . The thin-film vertically integrated unit diode chip according to claim 9 , wherein the second conductive type pad is connected to the second conductive type electrode line; the second conductive type electrode line is a linear electrode line. 11 . . 11.一种如权利要求10所述的薄膜垂直集成单元二极管芯片,其特征在于,所述线条形电极线布局方式为部分或全部设计采用直线布局。11 . The thin-film vertically integrated unit diode chip according to claim 10 , wherein the linear electrode line layout is partially or completely designed using a linear layout. 12 . 12.一种如权利要求10所述的薄膜垂直集成单元二极管芯片,其特征在于,所述线条形电极线布局方式为部分或全部设计采用非直线布局,所述非直线布局包括折线布局,曲线布局。12 . The thin-film vertically integrated unit diode chip according to claim 10 , wherein the linear electrode line layout is partially or completely designed using a non-linear layout, and the non-linear layout includes a broken line layout, a curved line layout, and a curved line layout. layout. 13.一种如权利要求1所述的薄膜垂直集成单元二极管芯片,其特征在于,还包括第一导电类型焊盘、第二导电类型焊盘,其中第一导电类型焊盘与第二导电类型焊盘在芯片同一侧,第一导电类型电极与第一导电类型焊盘连接,第二导电类型电极与第二导电类型焊盘连接,所述第一导电类型焊盘个数及所述第二导电类型焊盘个数大于或等于1。13. A thin film vertically integrated unit diode chip as claimed in claim 1, further comprising a first conductivity type pad and a second conductivity type pad, wherein the first conductivity type pad and the second conductivity type pad The pads are on the same side of the chip, the first conductivity type electrodes are connected to the first conductivity type pads, the second conductivity type electrodes are connected to the second conductivity type pads, the number of the first conductivity type pads and the second conductivity type pads are The number of conductive type pads is greater than or equal to 1. 14.一种如权利要求13所述的薄膜垂直集成单元二极管芯片,其特征在于,所述第一导电类型焊盘及所述第二导电类型焊盘形状为:半圆形,圆形,矩形,三角形。14. A thin-film vertically integrated unit diode chip according to claim 13, wherein the shape of the first conductive type pad and the second conductive type pad is: semicircle, circle, rectangle ,triangle. 15.一种如权利要求13所述的薄膜垂直集成单元二极管芯片,其特征在于,所述第一导电类型焊盘及所述第二导电类型焊盘厚度为0.001微米~20微米;所述第一导电类型焊盘宽度为:10微米~100微米。15 . The thin-film vertically integrated unit diode chip according to claim 13 , wherein the first conductive type pad and the second conductive type pad have a thickness of 0.001 μm˜20 μm; The width of a conductive type pad is: 10 microns to 100 microns. 16.一种如权利要求13所述的薄膜垂直集成单元二极管芯片,其特征在于,所述第一导电类型焊盘及所述第二导电类型焊盘位于所述芯片平面任意边沿、芯片平面顶点、芯片平面中间或芯片其它任意位置。16 . The thin-film vertically integrated unit diode chip of claim 13 , wherein the first conductive type pad and the second conductive type pad are located at any edge of the chip plane or at the apex of the chip plane. 17 . , the middle of the chip plane or any other position on the chip. 17.一种如权利要求1所述的薄膜垂直集成单元二极管芯片,其特征在于,所述n个二极管单元包括电流阻挡层和保护金属层,所述保护金属层内设置反射镜,所述电流阻挡层嵌置于保护金属层与反射镜内。17 . The thin-film vertically integrated unit diode chip according to claim 1 , wherein the n diode units comprise a current blocking layer and a protective metal layer, wherein a mirror is arranged in the protective metal layer, and the current The blocking layer is embedded in the protective metal layer and the mirror. 18.一种如权利要求17所述的薄膜垂直集成单元二极管芯片,其特征在于,所述第二导电类型电极与第二导电类型层接触长度小于电流阻挡层长度;所述第二导电类型电极与第二导电类型层接触长度为0.001微米-30微米;所述电流阻挡层长度为0.001微米-30微米。18 . The thin-film vertically integrated unit diode chip according to claim 17 , wherein the contact length between the second conductivity type electrode and the second conductivity type layer is less than the length of the current blocking layer; the second conductivity type electrode The length of the contact with the second conductive type layer is 0.001 micrometers to 30 micrometers; the length of the current blocking layer is 0.001 micrometers to 30 micrometers. 19.一种如权利要求17所述的薄膜垂直集成单元二极管芯片,其特征在于,所述绝缘介质层和电流阻挡层材料为二氧化硅、氧化铝、氮化硅中任一种或三种绝缘材料的组合。19. A thin-film vertically integrated unit diode chip according to claim 17, wherein the insulating dielectric layer and the current blocking layer are made of any one or three of silicon dioxide, aluminum oxide, and silicon nitride. A combination of insulating materials. 20.一种如权利要求17所述的薄膜垂直集成单元二极管芯片,其特征在于,所述二极管单元形状为:三角形、长方形、五边形、六边形、圆形、其他任意自定义形状。20 . The thin-film vertically integrated unit diode chip of claim 17 , wherein the diode unit shape is: triangle, rectangle, pentagon, hexagon, circle, or any other custom shape. 21 . 21.一种如权利要求7所述的薄膜垂直集成单元二极管芯片,其特征在于,所述n个二极管单元沿平行于所述第二导电类型电极线延伸方向长度为L0,L1,L2,…Lx,…Ln;所述L0≥L1≥L2≥…Lx…≥Ln;所述n个二极管单元沿垂直于所述第二导电类型电极线延伸方向从中间往两边宽度为W0,W1,W2,…Wy,…Wn,其中W0≥W1≥W2≥…Wy…≥Wn21 . The thin-film vertically integrated unit diode chip according to claim 7 , wherein the lengths of the n diode units along the extending direction parallel to the second conductive type electrode lines are L 0 , L 1 , and L 21 . 2 ,...L x ,...L n ; the L 0 ≥L 1 ≥L 2 ≥...L x ...≥L n ; the n diode units extend from the middle along the extending direction perpendicular to the second conductive type electrode line The widths to both sides are W 0 , W 1 , W 2 ,...W y ,...W n , where W 0 ≥W 1 ≥W 2 ≥...W y ...≥W n .
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