CN111864026B - LED chip and LED chip manufacturing method - Google Patents
LED chip and LED chip manufacturing method Download PDFInfo
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- CN111864026B CN111864026B CN202010892949.2A CN202010892949A CN111864026B CN 111864026 B CN111864026 B CN 111864026B CN 202010892949 A CN202010892949 A CN 202010892949A CN 111864026 B CN111864026 B CN 111864026B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 80
- 229910052751 metal Inorganic materials 0.000 claims abstract description 60
- 239000002184 metal Substances 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 14
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 14
- 235000012239 silicon dioxide Nutrition 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 8
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical group [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 7
- 239000000956 alloy Substances 0.000 claims description 7
- 229910052804 chromium Inorganic materials 0.000 claims description 7
- 239000011651 chromium Substances 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 7
- 229910052759 nickel Inorganic materials 0.000 claims description 7
- 229910052697 platinum Inorganic materials 0.000 claims description 7
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- 239000010936 titanium Substances 0.000 claims description 7
- 229910045601 alloy Inorganic materials 0.000 claims description 6
- 150000002739 metals Chemical class 0.000 claims description 6
- 238000002834 transmittance Methods 0.000 abstract description 2
- 230000006872 improvement Effects 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 230000000903 blocking effect Effects 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 229910002601 GaN Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- -1 or the like Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/83—Electrodes
- H10H20/831—Electrodes characterised by their shape
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/84—Coatings, e.g. passivation layers or antireflective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
- H10H20/032—Manufacture or treatment of electrodes
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- Led Devices (AREA)
Abstract
The invention provides an LED chip and a manufacturing method of the LED chip, wherein the LED chip comprises a substrate, an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, a transparent conducting layer, an N electrode and a P electrode, wherein the N-type semiconductor layer, the light-emitting layer, the P-type semiconductor layer, the transparent conducting layer, the N electrode and the P electrode are arranged on the substrate, the transparent conducting layer is provided with a first window area, the first window area is arranged above the P-type semiconductor layer and exposes the N-type semiconductor layer, a metal layer with the thickness ranging from 0.5 nm to 10nm and excellent adhesiveness is arranged on the P-type semiconductor layer in the first window area, an insulating layer is arranged above the metal layer and is electrically connected with the transparent conducting layer, the N electrode comprises an N electrode pad part and an N electrode expansion part, the N electrode pad part is arranged above the insulating layer, and the N electrode expansion part is electrically connected to the N-type semiconductor layer. The luminescent layer below the N electrode is reserved, the transparent conductive layer is replaced by the metal layer in the area below the insulating layer, the insulating layer and the semiconductor layer are firmly adhered by the metal layer with excellent adhesion, and the metal layer with nanoscale thickness is transparent and has light transmittance, so that the luminescent area below the N electrode is effectively utilized.
Description
Technical Field
The invention relates to the field of semiconductor light emitting devices, in particular to an LED chip and an LED chip manufacturing method.
Background
The light-emitting Diode (LED for short) is used as a novel energy-saving and environment-friendly solid-state lighting source, has the advantages of high energy efficiency, small volume, light weight, high response speed, long service life and the like, and is widely applied to a plurality of fields.
In a conventional LED epitaxial structure, a P-type semiconductor layer is arranged on an upper layer, an N-type semiconductor layer is arranged on a lower layer, a PN junction of a main reflecting layer is arranged between the P-type semiconductor layer and the N-type semiconductor layer, the N-type semiconductor layer needs to be exposed through an etching process in chip manufacturing, and the P-type semiconductor layer and a light-emitting layer are etched, so that the utilization rate of the main light-emitting layer is low. In order to solve the problem, a silicon dioxide passivation insulating layer is manufactured on a P-type semiconductor layer, then a small-area etching is performed on a specific area, an N-type semiconductor layer is exposed, an N-cathode bonding pad is manufactured on the insulating layer, and a metal electrode wire is used for connecting the small-area exposed area with the N-cathode bonding pad.
However, in the above technical solution, although the light emitting layer is reserved, the adhesion between the transparent conductive layer and the silicon dioxide, and between the transparent conductive layer and the metal electrode is poor, so that the transparent conductive layer cannot be arranged under the silicon dioxide layer below the N negative electrode pad for current expansion, and the light emitting efficiency of the area without the transparent conductive layer is extremely low, so that the light emitting area remains, but almost light emission is invalid, and the utilization rate of the light emitting layer is low, so that the effective area is wasted.
Disclosure of Invention
The invention aims to provide an LED chip and an LED chip manufacturing method.
The invention provides an LED chip, which comprises a substrate, an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, a transparent conducting layer, an N electrode and a P electrode, wherein the N-type semiconductor layer, the light-emitting layer, the P-type semiconductor layer, the transparent conducting layer, the N electrode and the P electrode are arranged on the substrate;
A metal layer is arranged on the N-type semiconductor layer in the first window area, an insulating layer is arranged above the metal layer, and the metal layer is electrically connected with the transparent conductive layer;
The N electrode comprises an N electrode pad part and an N electrode expansion part, wherein the N electrode pad part is arranged above the insulating layer, and the N electrode expansion part is electrically connected to the N-type semiconductor layer.
As a further improvement of the present invention, the P-type semiconductor layer and the light emitting layer are formed with a through N-electrode connection region exposing the N-type semiconductor layer, and the transparent conductive layer is provided with a second window region exposing the N-electrode connection region.
As a further improvement of the present invention, the N electrode further includes an N electrode extension portion connected to the N electrode pad portion, the N electrode extension portion extending into the N electrode connection region and electrically connected to the N-type semiconductor layer.
As a further improvement of the present invention, the insulating layer also covers a portion of the sidewall surface of the N-type semiconductor layer and the N-electrode connection region under the N-electrode extension.
As a further improvement of the invention, the material of the metal layer is chromium, titanium, aluminum, nickel, platinum, gold or alloy formed by the metals, and the thickness of the metal layer is in the range of 0.5-10nm.
As a further improvement of the present invention, the insulating layer is made of silicon dioxide.
The invention also provides a manufacturing method of the LED chip, which is characterized by comprising the following steps:
Providing a substrate, growing an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer on the substrate, and etching part of the light-emitting layer and the P-type semiconductor layer to form an N electrode connection region, so as to expose the N-type semiconductor layer;
forming a metal layer on the P-type semiconductor layer;
Forming a transparent conductive layer on the P-type semiconductor layer, and forming a first window region exposing the metal layer and a second window region exposing the N-electrode connection region in the transparent conductive layer;
forming an insulating layer on the metal layer;
And forming a P electrode on the transparent conductive layer, forming an N electrode pad part on the insulating layer, and forming an N electrode expansion part connected with the N electrode pad part in the N electrode connection region.
As a further improvement of the present invention, the insulating layer is also formed on a part of the sidewall surface of the N-type semiconductor layer and the N-electrode connection region under the N-electrode extension.
As a further improvement of the invention, the metal layer is made of chromium, titanium, aluminum, nickel, platinum, gold or alloy formed by the metals, and the thickness of the metal layer is in the range of 0.5-10nm.
As a further improvement of the present invention, the insulating layer is made of silicon dioxide.
The invention has the beneficial effects that the pad part of the N electrode is arranged on the insulating layer and is connected with the N-type semiconductor layer through the N electrode expansion part, so that the luminous layer below the N electrode can be reserved, the luminous efficiency is improved, the metal layer is adopted to replace the transparent conductive layer in the area below the insulating layer, the insulating layer and the semiconductor layer can be firmly adhered by the metal layer with excellent adhesion, the metal layer with nano-scale thickness is transparent, and the luminous area below the N electrode can be effectively utilized, and the utilization rate of the luminous layer is improved.
Drawings
Fig. 1 is a top view of an LED chip in a first embodiment of the invention.
Fig. 2 is a cross-sectional view at AA in fig. 1.
Fig. 3 is a cross-sectional view at BB in fig. 1.
Fig. 4 is a schematic flow chart of a method for manufacturing an LED chip according to the present invention.
Fig. 5 to 9 are schematic views illustrating steps of a method for manufacturing an LED chip according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be clearly and completely described below in conjunction with the detailed description of the present application and the corresponding drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to fall within the scope of the present application.
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present invention and are not to be construed as limiting the present invention.
For purposes of illustration, terms such as "upper," "lower," "rear," "front," and the like, are used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. The term spatially relative position may include different orientations of the device in use or operation than that illustrated in the figures. For example, if the device in the figures is turned over, elements described as "below" or "over" other elements or features would then be oriented "below" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both a spatial orientation of below and above.
As shown in fig. 1 and 2, the present invention provides an LED chip including a substrate 1 and an N-type semiconductor layer 2, a light emitting layer 3, a P-type semiconductor layer 4, a transparent conductive layer 5, an N-electrode 6, and a P-electrode 7 provided thereon.
The substrate is a sapphire substrate, or a silicon-based substrate, or a silicon carbide substrate, or a composite substrate formed by the substrates, or other common LED substrate materials are adopted.
The N-type semiconductor layer 2 and the P-type semiconductor layer 4 may be an N-type gallium nitride epitaxial layer and a P-type gallium nitride epitaxial layer, respectively, or other common LED epitaxial layer materials.
The transparent conductive layer 5 is provided with a first window region 51, and the first window region 51 is disposed above the P-type semiconductor layer 4 to expose the P-type semiconductor layer 4.
In this embodiment, the material of the transparent conductive layer 5 is indium tin oxide. In other embodiments, the current blocking layer 53 may be other transparent conductive oxide materials such as aluminum doped zinc oxide.
A current blocking layer 53 is further disposed between the P-type semiconductor layer 4 and the transparent conductive layer 5, and the current blocking layer 53 is located in a region below the P-electrode 7.
Further, the first window area 51 is located at one end of the LED chip, and is an area where the N electrode 6 is formed. The other end of the LED chip is provided with the P electrode 7, the P electrode 7 includes a circular P electrode pad region 71 and P electrode extension regions 72 symmetrically disposed at two ends of the P electrode pad region 71 and extending toward the first window region 51, and by setting the P electrode extension regions 72, current can be extended along the P electrode extension regions, so that more uniform current distribution is realized inside the LED chip.
Specifically, in this embodiment, the first window area 51 is in the shape of a rounded rectangle with an arc shape toward one side of the P electrode 7. In other embodiments, the shape of the first window area 51 may be adaptively adjusted according to the shape of the N electrode 6 in the LED chip.
In the first window region 51, the metal layer 8 is disposed on the P-type semiconductor layer 4, the insulating layer 9 is disposed above the metal layer 8, and the metal layer 8 is electrically connected to the transparent conductive layer 5.
Preferably, the metal layer 8 is made of a metal material having good adhesion such as chromium, titanium, aluminum, nickel, platinum, gold, or the like, or an alloy of the metals, and has a thickness in the range of 0.5 to 10nm. By using the metal layer 8 formed of a metal material having good adhesion, instead of the transparent conductive layer 5 provided in the conventional art, it is possible to make the connection between the transparent conductive layer and the insulating layer 9 formed thereon stronger, and the insulating layer 9 and the N electrode 6 do not come off due to poor adhesion. The thickness of the metal layer 8 is controlled to be in the nano level of 0.5-10nm, so that the metal layer 8 is nearly transparent, light transmission is realized, and the metal layer is electrically connected with the transparent conductive layer 5 of the periphery, thereby effectively utilizing the light-emitting area below the N electrode 6, improving the utilization rate of the light-emitting layer 3 and improving the light-emitting efficiency of the LED.
In this embodiment, the insulating layer 9 is made of silicon dioxide. In other embodiments, the insulating layer 9 may be made of an insulating material such as silicon nitride.
The N electrode 6 includes an N electrode pad portion 61 and an N electrode extension portion 62, the N electrode pad portion 61 is disposed above the insulating layer 9, and the N electrode extension portion 62 is electrically connected to the N-type semiconductor layer 2. The N electrode pad 61 is located inside the first window area 51, and the sidewall thereof is spaced from the inner wall of the first window area 51 by a distance so as to prevent the N electrode 6 from contacting the transparent conductive layer 5 to generate a short circuit.
The materials of the P electrode 7 and the N electrode 6 are chromium, titanium, aluminum, nickel, platinum, gold, or alloy materials formed by a plurality of the materials, or composite materials formed by a plurality of the materials, and the thickness of the P electrode 7 and the N electrode 6 ranges from 1 nm to 3000nm.
As shown in fig. 3, the P-type semiconductor layer 4 and the light emitting layer 3 are formed with a through N-electrode connection region 41 exposing the N-type semiconductor layer 2, and the transparent conductive layer 5 is provided with a second window region 52 exposing the N-electrode connection region 41.
Further, the N electrode 6 further includes an N electrode extension 62 connected to the N electrode pad 61, and the N electrode extension 62 extends into the N electrode connection region 41 and is electrically connected to the N-type semiconductor layer 2.
Specifically, in this embodiment, the N electrode connection region 41 is disposed at the middle position of the LED chip and adjacent to the N electrode pad portion 61, and the cross section of the N electrode connection region 41 is approximately ellipsoidal, so that the N electrode expansion portion 62 is conveniently LED out from the N electrode pad portion 61 to be electrically connected to the N-type semiconductor layer 2. By connecting the N electrode extension 62 with the N electrode connection area 41, only etching is performed on the N electrode connection area 41 with a relatively small area ratio, so that the area below the N electrode pad 61, which is the main body of the N electrode 6, does not need etching, a light-emitting area at the area is reserved, the utilization rate of the light-emitting layer 3 is improved, and the light-emitting efficiency of the LED chip is improved.
Of course, in other embodiments of the present invention, the shape and position of the N electrode connection region 41 may be adaptively adjusted according to the actual size of the LED chip and the distribution positions of the P electrode 7 and the N electrode 6.
The insulating layer 9 also covers part of the sidewall surface of the N-type semiconductor layer 2 and the N-electrode connection region 41 below the N-electrode extension 62, so as to avoid the occurrence of short circuit of the N-electrode 6.
In some embodiments of the present invention, an insulating protection layer is further disposed on the transparent conductive layer 5, the P electrode 7 and the N electrode 6, where the insulating protection layer exposes the pad areas of the P electrode 7 and the N electrode 6, and covers other parts, so as to protect the LED chip.
The invention also provides a manufacturing method of the LED chip, which comprises the following steps:
S1, providing a substrate 1, growing the N-type semiconductor layer 2, the light-emitting layer 3 and the P-type semiconductor layer 4 on the substrate 1, and etching part of the light-emitting layer 3 and the P-type semiconductor layer 4 to form an N electrode connection region 41 to expose the N-type semiconductor layer 2.
Specifically, in this embodiment, the N electrode connection region 41 is located in the middle area of the surface of the LED chip, is an ellipsoidal area, and is disposed adjacent to the area where the N electrode 6 is disposed in the subsequent process.
Of course, in other embodiments of the present invention, the shape and position of the N electrode connection region 41 may be adaptively adjusted according to the actual size of the LED chip and the distribution positions of the P electrode 7 and the N electrode 6.
S2, forming a metal layer 8 on the P-type semiconductor layer 4.
Specifically, in the present embodiment, forming the metal layer 8 specifically includes depositing a layer of metal with a thickness ranging from 0.5 nm to 10nm on the P-type semiconductor layer 4, coating a photoresist, exposing and developing to form a pattern of the metal layer 8, and stripping the photoresist to form the metal layer 8. The metal layer 8 is made of a metal material having good adhesion such as chromium, titanium, aluminum, nickel, platinum, gold, or the like, or an alloy of the metals.
The shape of the metal layer 8 matches the shape of the N electrode 6.
And S3, forming the transparent conductive layer 5 on the P-type semiconductor layer 4, and forming the first window region 51 exposing the metal layer 8 and the second window region 52 exposing the N electrode connection region 41 in the transparent conductive layer 5.
Before forming the transparent conductive layer 5, a current blocking layer 53 is deposited on the P-type semiconductor layer 4, and the position of the current blocking layer 53 corresponds to the position where the P-electrode 7 is formed in the subsequent process.
Specifically, in this embodiment, forming the transparent conductive layer 5 includes depositing indium tin oxide on the P-type semiconductor layer 4 and the current blocking layer 53, coating photoresist on the surface of the indium tin oxide layer, exposing and developing to form a pattern of the transparent conductive layer 5, and etching and photoresist removing to form the transparent conductive layer 5.
And S4, forming the insulating layer 9 on the metal layer 8.
Specifically, in this embodiment, forming the insulating layer 9 includes depositing a silicon dioxide layer on the P-type semiconductor layer 4 and the metal layer 8, coating photoresist on the surface of the silicon dioxide layer, exposing and developing to form a pattern of the insulating layer 9, and etching and photoresist removing to form the insulating layer 9.
The insulating layer 9 is deposited on a portion of the sidewall surface of the N electrode connection region 41 and a portion of the region where the N electrode connection region 41 is connected to the metal layer 8, in addition to being formed on the metal layer 8, so that the N electrode 6 can be vapor-deposited thereon in a subsequent process.
In this embodiment, the insulating layer 9 is made of silicon dioxide. In other embodiments, the insulating layer 9 may be made of an insulating material such as silicon nitride.
S5, forming a P electrode 7 on the transparent conductive layer 5, forming an N electrode pad portion 61 on the insulating layer 9, and forming an N electrode extension portion 62 connected to the N electrode pad portion 61 in the N electrode connection region 41.
Specifically, in the present embodiment, forming the electrode includes depositing metal, coating photoresist, exposing and developing to form the electrode pattern, and stripping the photoresist to form the P electrode 7 layer and the N electrode 3.
In summary, according to the invention, the pad portion of the N electrode is disposed on the insulating layer and connected to the N-type semiconductor layer through the N electrode extension portion, so that the light emitting layer below the N electrode can be reserved, the light emitting efficiency is improved, the metal layer is used for replacing the transparent conductive layer in the area below the insulating layer, the metal layer with excellent adhesion can firmly adhere to the insulating layer and the semiconductor layer, the metal layer with nano-scale thickness is transparent, and has light transmittance, so that the light emitting area below the N electrode can be effectively utilized, and the utilization rate of the light emitting layer is improved.
It should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is for clarity only, and that the skilled artisan should recognize that the embodiments may be combined as appropriate to form other embodiments that will be understood by those skilled in the art.
The above list of detailed descriptions is only specific to practical embodiments of the present invention, and is not intended to limit the scope of the present invention, and all equivalent embodiments or modifications that do not depart from the spirit of the present invention should be included in the scope of the present invention.
Claims (10)
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| KR101654340B1 (en) * | 2009-12-28 | 2016-09-06 | 서울바이오시스 주식회사 | A light emitting diode |
| WO2015074353A1 (en) * | 2013-11-25 | 2015-05-28 | 扬州中科半导体照明有限公司 | Semiconductor light-emitting diode chip |
| CN208093585U (en) * | 2018-03-30 | 2018-11-13 | 厦门市三安光电科技有限公司 | Light emitting diode |
| CN111446336B (en) * | 2020-04-01 | 2023-05-05 | 厦门三安光电有限公司 | led |
| CN208127231U (en) * | 2018-05-10 | 2018-11-20 | 江西乾照光电有限公司 | Improve chip structure, light emitting diode (LED) display screen and the display device of metal migration |
| CN111463327B (en) * | 2020-05-22 | 2024-12-31 | 湘能华磊光电股份有限公司 | LED chip with improved external quantum efficiency and preparation method thereof |
| CN111509097B (en) * | 2020-06-30 | 2020-10-20 | 华引芯（武汉）科技有限公司 | A kind of high-power semiconductor light-emitting device and preparation method thereof |
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