CN111835299A - Variable gain amplifier with variable bandwidth - Google Patents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/42—Modifications of amplifiers to extend the bandwidth
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/213—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits
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Abstract
The invention discloses a variable gain amplifier with variable bandwidth, which comprises a four-stage bandwidth gain control unit and an output buffer which are cascaded, wherein the bandwidth gain control unit is connected through a direct current offset elimination feedback unit; the variable gain amplifier has broadband performance, can meet the requirements of a system on different bandwidths, meets the requirement of high gain, has a larger digitally controllable gain variable range, and has the advantages of excellent in-band flatness, low voltage, low power consumption, high reliability and the like.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a variable gain amplifier with variable bandwidth.
Background
As an indispensable module in a receiver, a variable gain amplifier plays an extremely important role for the following reasons: in the process of transmitting signals in nature, because the transmission paths and media which pass through the signals are always different, the power of the signals received by a receiver is changed within a certain range, and in order to enable a later-stage analog-to-digital conversion module to have higher resolution and signal-to-noise ratio, the output signals of the later-stage analog-to-digital conversion module must be fixed within a stable small range. Often the receiver front-end can only provide a fixed or small variable gain, which requires that a variable gain amplifier must be added before the analog-to-digital conversion module.
With the increasing performance of wireless signal transmission systems in recent years, the demand for variable gain amplifiers is also increasing, mainly reflected in the following aspects: an increase in signal frequency results in an increase in the bandwidth requirements of the variable gain amplifier; the complexity of signal jumping is increased, and higher variable bandwidth requirements are put forward on the variable gain amplifier; the increasing signal transmission time inevitably requires reducing the power consumption of the variable gain amplifier and reducing the power supply voltage; in order to ensure the stability of the circuit under high gain, it is necessary to eliminate the dc offset voltage.
Disclosure of Invention
Aiming at the defects in the prior art, the variable gain amplifier with the variable bandwidth provided by the invention can meet the requirements of a millimeter wave high-speed wireless communication system on the bandwidth, the gain, the stability, the power consumption and the like of the variable gain amplifier.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that: a variable gain amplifier with variable bandwidth comprises a first-stage bandwidth gain control unit VGA1, a second-stage bandwidth gain control unit VGA2, a third-stage bandwidth gain control unit VGA3, a fourth-stage bandwidth gain control unit VGA4, a first constant current loss and modulation elimination feedback unit, a second-stage direct current imbalance elimination feedback unit and an output buffer;
a first input end and a second input end of the first-stage bandwidth gain control unit VGA1 are jointly used as input ends of a variable gain amplifier to be connected with a signal source, a first output end of the first-stage bandwidth gain control unit VGA1 is connected with a first input end of a second-stage bandwidth gain control unit VGA2, and a second output end of the first-stage bandwidth gain control unit VGA2 is connected with a second input end of the second-stage bandwidth gain control unit VGA 2;
a first output end of the second-stage bandwidth gain control unit VGA2 is connected to a first input end of a third-stage bandwidth gain control unit VGA3 and a first input end of a first constant loss modulation cancellation feedback unit, a second output end of the second-stage bandwidth gain control unit VGA2 is connected to a second input end of a third-stage bandwidth gain control unit VGA3 and a second input end of the first constant loss modulation cancellation feedback unit, a first output end of the first constant loss modulation cancellation feedback unit is connected to a third input end of the first-stage bandwidth gain control unit VGA1, and a second output end of the first constant loss modulation cancellation feedback unit VGA1 is connected to a fourth input end of the first-stage bandwidth gain control unit VGA 1;
a first output end of the third-stage bandwidth gain control unit VGA3 is connected with a first input end of the fourth-stage bandwidth gain control unit VGA4, and a second output end of the third-stage bandwidth gain control unit VGA3 is connected with a second input end of the fourth-stage bandwidth gain control unit VGA 4;
a first output end of the fourth-stage bandwidth gain control unit VGA4 is connected to a first input end of the second dc offset cancellation feedback unit and a first input end of the output buffer, respectively, and a second output end thereof is connected to a second input end of the second dc offset cancellation feedback unit and a second input end of the output buffer, respectively, a first output end of the second dc offset cancellation feedback unit is connected to a third input end of the third-stage bandwidth gain control unit VGA3, and a second output end thereof is connected to a fourth input end of the third-stage bandwidth gain control unit VGA 3;
the first output end and the second output end of the output buffer are jointly used as the output end of the variable gain amplifier to be connected with a post-stage load;
and the control ends of the first-stage bandwidth gain control unit VGA1, the second-stage bandwidth gain control unit VGA2, the third-stage bandwidth gain control unit VGA3 and the fourth-stage bandwidth gain control unit VGA4 are connected with a numerical control device.
Further, the first-stage bandwidth gain control unit VGA1, the second-stage bandwidth gain control unit VGA2, the third-stage bandwidth gain control unit VGA3 and the fourth-stage bandwidth gain control unit VGA4 each include a transconductance amplifier, a transimpedance amplifier, a first variable capacitor array and a second variable capacitor array;
the first input end of the transconductance stage amplifier is used as the first input end of the current bandwidth gain control unit, the second input end of the transconductance stage amplifier is used as the second input end of the current bandwidth gain control unit, the first output end of the transconductance stage amplifier is connected with the first input end of the transimpedance stage amplifier through the A + end of the first variable capacitor array, and the second output end of the transconductance stage amplifier is connected with the second input end of the transimpedance stage amplifier through the A-end of the first variable capacitor array;
the first output end of the trans-impedance amplifier is connected with the B + end of the second variable capacitor array, the second output end of the trans-impedance amplifier is connected with the B-end of the second variable capacitor array, the B + end of the second variable capacitor array is used as the first output end of the current bandwidth gain control unit, and the B-end of the second variable capacitor array is used as the second output end of the current bandwidth gain control unit;
the variable resistor array is connected between the first input end and the first output end of the trans-impedance amplifier and between the second input end and the second output end of the trans-impedance amplifier;
and the control ends of the first variable capacitor array, the second variable capacitor array and the variable resistor array are connected with a numerical control device.
Furthermore, the first variable capacitor array and the second variable capacitor array have the same circuit structure and comprise n variable capacitor circuits;
each variable capacitor circuit comprises a first numerical control switch, a capacitor and a second numerical control switch which are connected in sequence, one end of the first numerical control switch, which is not connected with the capacitor, is used as an A + end of the first variable capacitor array or a B + end of the second variable capacitor array circuit, and one end of the second numerical control switch, which is not connected with the capacitor, is used as an A-end of the first variable capacitor array or a B-end of the second variable capacitor array circuit;
and the control ends of the first numerical control switch and the second numerical control switch are connected with a numerical control device.
Further, the variable resistor arrays in the first-stage bandwidth gain control unit VGA1 and the second-stage bandwidth gain control unit VGA2 are gain coarse-tuning variable resistor arrays with step size of 6 dB;
the variable resistor array in the third-stage bandwidth gain control unit VGA3 is a gain coarse adjustment variable resistor array with the step length of 3 dB;
the variable resistor array in the fourth stage bandwidth gain control unit VGA4 fine-tunes the variable resistor array for gain with a step size of 1 dB.
Further, the gain coarse adjustment variable resistor array with the step size of 6dB comprises a resistor R1;
one end of the resistor R1 is connected to one end of the resistor R2 and one end of the resistor R6, and is connected to the first input end or the second input end of the transimpedance amplifier, the other end of the resistor R2, the resistor R3, the switch SW3, the resistor R4 and one end of the resistor R5 are sequentially connected, a switch SW2 is further connected between a connection node of the resistor R2 and the resistor R3 and a connection node of the resistor R4 and the resistor R5, the other end of the resistor R6, the resistor R7, the switch SW1, the resistor R8 and one end of the resistor R9 are sequentially connected, a switch SW0 is further connected between the connection node of the resistor R6 and the resistor R7 and a connection node of the resistor R8 and the resistor R9, and the other end of the resistor R1 is connected to the other end of the resistor R5 and the other end of the resistor R9, and is connected to the first output end or the second output end of the transimpedance amplifier;
and control ends of the switch SW0, the switch SW1, the switch SW2 and the switch SW3 are connected with a numerical control device.
Further, the gain coarse adjustment variable resistor array with the step size of 3dB comprises a resistor R18;
one end of the resistor R18 is connected to one end of the resistor R18, one end of the resistor R18 and one end of the resistor R18, and is connected to the first input end or the second input end of the transimpedance amplifier, the other end of the resistor R18, one end of the resistor R18 and one end of the resistor R18 are sequentially connected, a switch SW 18 is further connected between a connection node of the resistor R18 and a connection node of the resistor R18 and the resistor R18, the other end of the resistor R18, the switch SW 18, the resistor R18 and one end of the resistor R18 are sequentially connected, a switch SW 18 is further connected between a connection node of the resistor R18 and a connection node of the resistor R18 and the resistor R18, one end of the other end of the resistor R18, the switch SW 18, one end of the resistor R18 and one end of the resistor R18 are further connected between the connection node SW 18 and the resistor R18, the other end of the resistor R18, the other end of the resistor R22, the other end of the resistor R26 and the other end of the resistor R30 are connected, and are connected with a first output end or a second output end of the transimpedance amplifier;
and control ends of the switch SW9, the switch SW10, the switch SW11, the switch SW12 and the switch SW13 are connected with a numerical control device.
Further, the gain fine tuning variable resistor array with the step size of 1dB comprises a resistor R10;
one end of the resistor R10 is respectively connected with one end of the resistor R11, one end of the resistor R14 and the source electrode of the MOS transistor MR, and is connected with the first input end or the second input end of the trans-impedance amplifier, the other end of the resistor R11, one end of the resistor R12 and one end of the resistor R13 are connected in turn, a switch SW6 is connected to two ends of the resistor R12, the other end of the resistor R14, one end of the resistor R15, one end of the switch SW5, one end of the resistor R16 and one end of the resistor R17 are sequentially connected, a switch SW4 is connected between the connecting node of the resistor R14 and the resistor R15 and the connecting node of the resistor R16 and the resistor R17, the other end of the resistor R10, the other end of the resistor R13, the other end of the resistor R17 and the drain electrode of the MOS tube MR are all connected with the first output end or the second output end of the transimpedance amplifier, the base electrodes of the MOS transistors are respectively connected with one end of a switch SW7 and one end of a switch SW8, and the other ends of the switch SW7 and the switch SW8 are vacant;
and control ends of the switch SW4, the switch SW5, the switch SW6, the switch SW7 and the switch SW8 are connected with a numerical control device.
Further, the first dc offset cancellation feedback unit and the second dc offset cancellation feedback unit have the same circuit structure, and each of the first dc offset cancellation feedback unit and the second dc offset cancellation feedback unit includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, and a transistor M5;
one end of the resistor R31 is used as a first input end of the first constant current loss elimination feedback unit or the second direct current offset elimination feedback unit, the other end of the resistor R31 is connected with the bases of the grounded capacitor C1 and the transistor M1, the drain of the transistor M1 is connected with the drain of the transistor M4 and the base of the transistor M4 respectively and is used as a second output end of the first constant current loss elimination feedback unit or the second direct current offset elimination feedback unit, the source of the transistor M4 and the transistor M5 are both connected with the power supply, the drain of the transistor M5 is connected with the base of the transistor M5 and is used as a first output end of the first constant current loss elimination feedback unit or the second direct current offset elimination feedback unit, the drain of the transistor M5 is further connected with the drain of the transistor M2, the source of the transistor M2 and the source of the transistor M1 are both connected with the drain of the transistor M3, the source of the transistor M3 is, the base of the transistor M3 is set to be empty, the base of the transistor M2 is respectively connected with one end of a grounded capacitor C2 and one end of a resistor R32, and the other end of the resistor R32 is used as a second input end of the first dc offset cancellation feedback unit or the second dc offset cancellation feedback unit.
Further, the output buffer is of a frequency multiplier structure and comprises a transistor M6, a transistor M7, a transistor M8 and a transistor M9;
the base of the transistor M6 is used as a first input end of the output buffer, the drain of the transistor M6 is respectively connected with one end of a resistor R33 and the drain of the transistor M8 and is used as a second output end of the output buffer, the source of the transistor M6 and the source of the transistor M7 are both grounded, the drain of the transistor M7 is respectively connected with one end of a resistor R34 and the drain of the transistor M9 and is used as a first output end of the output buffer, the transistor M8 and the transistor M9 are both grounded, the base of the transistor M9 is used as a second input end of the output buffer, and the other end of the resistor R33 and the other end of the resistor R34 are connected with each other and are connected with a power supply.
The invention has the beneficial effects that:
1. the gain control unit adopted by the invention adopts an improved Cherry-Hooper structure, so that the bandwidth performance of the circuit is effectively increased, the circuit can work under low voltage, and the power consumption of the circuit is greatly reduced.
2. The variable capacitor array adopted by the invention can effectively control the bandwidth of the variable gain amplifier and simultaneously meet different bandwidth requirements of a single channel and multiple channels of a communication system.
3. The variable resistor array adopted by the invention can simultaneously realize wide dynamic range and high-precision gain control, simultaneously avoid the use of excessive transistor switches and ensure that the gain curve of the variable gain amplifier has excellent in-band flatness.
4. The invention adopts double negative feedback direct current offset elimination technology, effectively solves the offset voltage problem in the high gain cascade circuit and ensures the stability of the circuit.
5. The frequency multiplier is used as an output buffer of the circuit, so that the bandwidth of the circuit is effectively improved, and the driving capability of the circuit is increased.
6. Compared with the traditional broadband amplifier, the broadband amplifier effectively avoids the use of an inductor, greatly reduces the circuit area and is easy to integrate.
Drawings
Fig. 1 is a schematic diagram of a variable gain amplifier topology with variable bandwidth according to the present invention.
Fig. 2 is a schematic structural diagram of a bandwidth gain control unit according to the present invention.
Fig. 3 is a schematic diagram of the first/second variable capacitor array according to the present invention.
FIG. 4 is a circuit diagram of a variable resistor array with 6dB coarse gain tuning provided by the present invention.
FIG. 5 is a schematic diagram of a 3dB coarse gain tuning variable resistor array circuit according to the present invention.
FIG. 6 is a circuit diagram of a 1dB gain fine tuning variable resistor array according to the present invention.
Fig. 7 is a circuit diagram of the first/second dc offset cancellation feedback unit according to the present invention.
Fig. 8 is a schematic diagram of an output buffer circuit according to the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
As shown in fig. 1, a variable gain amplifier with variable bandwidth includes a first-stage bandwidth gain control unit VGA1, a second-stage bandwidth gain control unit VGA2, a third-stage bandwidth gain control unit VGA3, a fourth-stage bandwidth gain control unit VGA4, a first dc offset cancellation feedback unit, a second-stage dc offset cancellation feedback unit, and an output buffer;
a first input end and a second input end of the first-stage bandwidth gain control unit VGA1 are jointly used as input ends of the variable gain amplifier to be connected with a signal source, a first output end of the first-stage bandwidth gain control unit VGA1 is connected with a first input end of the second-stage bandwidth gain control unit VGA2, and a second output end of the first-stage bandwidth gain control unit VGA2 is connected with a second input end of the second-stage bandwidth gain control unit VGA 2;
a first output end of the second-stage bandwidth gain control unit VGA2 is connected to a first input end of the third-stage bandwidth gain control unit VGA3 and a first input end of the first constant loss modulation cancellation feedback unit, a second output end of the second-stage bandwidth gain control unit VGA2 is connected to a second input end of the third-stage bandwidth gain control unit VGA3 and a second input end of the first constant loss modulation cancellation feedback unit, a first output end of the first constant loss modulation cancellation feedback unit is connected to a third input end of the first-stage bandwidth gain control unit VGA1, and a second output end of the first constant loss modulation cancellation feedback unit VGA1 is connected to a fourth input end of the first-stage bandwidth gain control unit VGA 1;
a first output end of the third-stage bandwidth gain control unit VGA3 is connected to a first input end of the fourth-stage bandwidth gain control unit VGA4, and a second output end thereof is connected to a second input end of the fourth-stage bandwidth gain control unit VGA 4;
a first output end of the fourth-stage bandwidth gain control unit VGA4 is connected to a first input end of the second dc offset cancellation feedback unit and a first input end of the output buffer, respectively, and a second output end thereof is connected to a second input end of the second dc offset cancellation feedback unit and a second input end of the output buffer, respectively, a first output end of the second dc offset cancellation feedback unit is connected to a third input end of the third-stage bandwidth gain control unit VGA3, and a second output end thereof is connected to a fourth input end of the third-stage bandwidth gain control unit VGA 3;
the first output end and the second output end of the output buffer are jointly used as the output end of the variable gain amplifier to be connected with a post-stage load;
the control ends of the first-stage bandwidth gain control unit VGA1, the second-stage bandwidth gain control unit VGA2, the third-stage bandwidth gain control unit VGA3 and the fourth-stage bandwidth gain control unit VGA4 are connected with a numerical control device.
The variable gain amplifier in the embodiment can meet the requirements of a millimeter wave high-speed wireless communication system on the bandwidth, gain, stability, power consumption and the like of the variable gain amplifier.
As shown in fig. 2, each of the first-stage bandwidth gain control unit VGA1, the second-stage bandwidth gain control unit VGA2, the third-stage bandwidth gain control unit VGA3 and the fourth-stage bandwidth gain control unit VGA4 in the present embodiment includes a Cherry-Hooper amplifier with ultra-bandwidth advantage, and the Cherry-Hooper amplifier includes a transconductance-stage amplifier, a transimpedance-stage amplifier, a first variable capacitor array and a second variable capacitor array;
a first input end of the transconductance stage amplifier is used as a first input end of the current bandwidth gain control unit, a second input end of the transconductance stage amplifier is used as a second input end of the current bandwidth gain control unit, a first output end of the transconductance stage amplifier is connected with the first input end of the transimpedance stage amplifier through an A + end of the first variable capacitor array, and a second output end of the transconductance stage amplifier is connected with the second input end of the transimpedance stage amplifier through an A-end of the first variable capacitor array;
the first output end of the trans-impedance amplifier is connected with the B + end of the second variable capacitor array, the second output end of the trans-impedance amplifier is connected with the B-end of the second variable capacitor array, the B + end of the second variable capacitor array is used as the first output end of the current bandwidth gain control unit, and the B-end of the second variable capacitor array is used as the second output end of the current bandwidth gain control unit;
a variable resistor array is connected between the first input end and the first output end of the trans-impedance amplifier and between the second input end and the second output end of the trans-impedance amplifier;
and the control ends of the first variable capacitor array, the second variable capacitor array and the variable resistor array are connected with a numerical control device.
The two variable capacitor arrays and the variable resistor array are digitally controlled, different control words determine the organization of the variable resistor array, and simultaneously determine the gain size and the step length of the gain control unit to which the variable capacitor array and the variable resistor array belong; for a variable capacitor array, different control words determine the equivalent capacitance of the variable capacitor array while varying the bandwidth of the variable gain amplifier.
As shown in fig. 3, the variable capacitor array in the present embodiment is composed of switches and capacitors. The switch is switched on and off to control the increment or decrement of a differential capacitor between the differential nodes A + and A-and between the differential nodes B + and B-, so that the adjustment of the bandwidth is realized, and the requirements of the system under different transmission rates are met; specifically, the first variable capacitor array and the second variable capacitor array have the same circuit structure and comprise n variable capacitor circuits;
each variable capacitor circuit comprises a first numerical control switch, a capacitor and a second numerical control switch which are connected in sequence, wherein one end of the first numerical control switch, which is not connected with the capacitor, is used as an A + end of the first variable capacitor array or a B + end of the second variable capacitor array circuit, and one end of the second numerical control switch, which is not connected with the capacitor, is used as an A-end of the first variable capacitor array or a B-end of the second variable capacitor array circuit;
the control ends of the first numerical control switch and the second numerical control switch are connected with the numerical control device.
In fig. 2, the variable resistor arrays in the first-stage bandwidth gain control unit VGA1 and the second-stage bandwidth gain control unit VGA2 are gain coarse-tuning variable resistor arrays with a step size of 6 dB; the variable resistor array in the third-stage bandwidth gain control unit VGA3 is a gain coarse adjustment variable resistor array with the step length of 3 dB; the variable resistor array in the fourth-stage bandwidth gain control unit VGA4 is a gain fine-tuning variable resistor array with step size of 1 dB;
as shown in FIG. 4, the coarse gain tuning variable resistor array with a step size of 6dB comprises a resistor R1;
one end of a resistor R1 is connected with one end of a resistor R2 and one end of a resistor R6 respectively, and is connected with a first input end or a second input end of the transimpedance-stage amplifier, the other end of the resistor R2, one end of the resistor R3, one end of a switch SW3, one end of a resistor R4 and one end of a resistor R5 are sequentially connected, a switch SW2 is further connected between a connection node of the resistor R2 and the resistor R3 and a connection node of the resistor R4 and the resistor R5, the other end of the resistor R6, the resistor R7, the switch SW1, one end of the resistor R8 and one end of the resistor R9 are sequentially connected, a switch SW0 is further connected between a connection node of the resistor R6 and the resistor R7 and a connection node of the resistor R8 and the resistor R9, and the other end of the resistor R1 is connected with the other end of the resistor R5 and the other end of the resistor R9 respectively;
the control ends of the switch SW0, the switch SW1, the switch SW2 and the switch SW3 are all connected with the numerical control device.
The gain coarse adjustment variable resistor array in the embodiment adopts proportional resistors of the same type, and the equivalent resistance value of the gain coarse adjustment variable resistor array has a 2-time (6dB) change step length by controlling the on-off of the control switch, so that a 16-time (24dB) gain change range is realized; the specific implementation steps are that when the switches are all disconnected, the equivalent resistance value is 12R; the switch SW3 is closed, and other switches are all opened, and the equivalent resistance value is 6R; the switch SW3/SW2 is closed, the switch SW1/SW0 is opened, and the equivalent resistance value is 3R; closing the switch SW3/SW2/SW1, wherein the equivalent resistance value is 1.5R; the switch SW3/SW2/SW1/SW0 is closed, and the equivalent resistance value is 0.75R. The switches in the array are positioned between the resistors, so that the influence of parasitic capacitance of the switches on the sensitive nodes A and B is effectively weakened, and the bandwidth of the circuit and the in-band flatness of a gain curve are greatly improved.
It should be noted that, as shown in fig. 5, the circuit structure of the coarse gain variable resistor array with a step size of 3dB for the variable resistor array in the third-stage bandwidth gain control unit VGA3 is similar to that of fig. 4, and specifically includes a resistor R18;
one end of a resistor R18 is connected with one end of a resistor R19, one end of a resistor R23 and one end of a resistor R27, and is connected with the first input end or the second input end of the transimpedance amplifier, the other end of the resistor R19, one ends of a resistor R20, a resistor R21 and a resistor R22 are sequentially connected, a switch SW9 is further connected between a connection node of the resistor R19 and the resistor R20 and a connection node of the resistor R21 and the resistor R22, the other end of the resistor R23, a resistor R24, a switch SW11, one ends of the resistor R25 and the resistor R26 are sequentially connected, a switch SW10 is further connected between a connection node of the resistor R23 and the resistor R24 and a connection node of the resistor R25 and the resistor R26, the other end of the resistor R27, a resistor R28, a switch SW13, a resistor R29 and one end of the resistor R30 are connected, a connection node of the resistor R27 and a connection node of the resistor R28 and the other end of the resistor R28 are further connected, and a connection node of the resistor R28 and the, The other end of the resistor R26 is connected with the other end of the resistor R30 and is connected with the first output end or the second output end of the transimpedance amplifier; the control ends of the switch SW9, the switch SW10, the switch SW11, the switch SW12 and the switch SW13 are all connected with a numerical control device, and the specific working mechanism is shown in Table 1:
table 1: 3dB gain coarse tuning variable resistor array mechanism
As shown in fig. 6, the gain fine tuning variable resistor array with a step size of 1dB includes a resistor R10;
one end of a resistor R10 is connected with one end of a resistor R11, one end of a resistor R14 and the source of the MOS tube MR respectively, and is connected with a first input end or a second input end of the transimpedance amplifier, the other end of the resistor R11, one ends of a resistor R12 and a resistor R13 are connected in sequence, two ends of a resistor R12 are also connected with a switch SW6, the other end of the resistor R14, a resistor R15, a switch SW5, a resistor R16 and one end of a resistor R17 are connected in sequence, a connection node of the resistor R14 and the resistor R15 and a connection node of the resistor R16 and the resistor R17 are also connected with a switch SW4, the other end of the resistor R10, the other end of the resistor R13, the other end of the resistor R17 and the drain of the MOS tube MR are connected with a first output end or a second output end of the transimpedance amplifier respectively, a base of the MOS tube is connected with one end of a switch SW7 and one end of a switch SW8, and the other end of the switch SW 36;
control ends of the switch SW4, the switch SW5, the switch SW6, the switch SW7 and the switch SW8 are connected with the numerical control device.
The gain fine-tuning variable resistor array in the embodiment is composed of a common resistor and a voltage-controlled MOS variable resistor MR, the gain of the circuit is accurately controlled by controlling the on and off of a switch, the gain variation range of 12dB can be realized by the array, and the step length of the gain variation range is 1 dB. The variable MOS resistor adopted in the array effectively avoids the use of a large number of switches while obtaining 1dB step length, and greatly improves the bandwidth of the circuit and the in-band flatness of a gain curve.
As shown in fig. 7, the two dc offset cancellation feedback units in the present embodiment have the same circuit structure, and each dc offset cancellation feedback unit includes a low-pass filter and a fully differential amplifier, where the low-pass filter is composed of a resistor and a capacitor, and is used to extract the dc offset voltage at the output terminal, and then the dc offset voltage is fed back to the circuit through the fully differential common-source amplifier. The load of the fully differential amplifier is a triode in a connecting diode mode; the direct-current offset voltage of the first-stage gain control unit and the third-stage gain control unit can be effectively eliminated through the two direct-current offset elimination circuits, so that the direct-current offset voltage of the whole link can be eliminated; specifically, the first dc cancellation feedback unit and the second dc cancellation feedback unit each include a transistor M1, a transistor M2, a transistor M3, a transistor M4, and a transistor M5;
one end of the resistor R31 is used as a first input end of the first constant loss modulation elimination feedback unit or the second dc offset elimination feedback unit, the other end is connected to the bases of the grounded capacitor C1 and the transistor M1, the drain of the transistor M1 is connected to the drain of the transistor M4 and the base of the transistor M4, and is used as a second output end of the first constant loss modulation elimination feedback unit or the second dc offset elimination feedback unit, the source of the transistor M4 and the transistor M5 are both connected to the power supply, the drain of the transistor M5 is connected to the base of the transistor M5 and is used as a first output end of the first constant loss modulation elimination feedback unit or the second dc offset elimination feedback unit, the drain of the transistor M5 is further connected to the drain of the transistor M2, the source of the transistor M2 and the source of the transistor M1 are both connected to the drain of the transistor M3, the source of the transistor M3 is grounded, and the base of the transistor M3 is, the base of the transistor M2 is connected to one end of the ground capacitor C2 and one end of the resistor R32, respectively, and the other end of the resistor R32 is used as the second input end of the first dc offset cancellation feedback unit or the second dc offset cancellation feedback unit.
As shown in fig. 8, the output buffer in this embodiment is a frequency multiplier structure, which effectively reduces the parasitic capacitance to ground at the input end, facilitates implementation of a wideband, and greatly increases the driving capability of the circuit, and simultaneously, the lower output load resistance ensures the stronger driving capability of the whole single channel, and can drive a test instrument with an input impedance of 50 ohms, specifically, the output buffer includes a transistor M6, a transistor M7, a transistor M8, and a transistor M9;
the base of the transistor M6 is used as a first input end of the output buffer, the drain of the transistor M6 is respectively connected with one end of the resistor R33 and the drain of the transistor M8, and is used as a second output end of the output buffer, the source of the transistor M6 and the source of the transistor M7 are both grounded, the drain of the transistor M7 is respectively connected with one end of the resistor R34 and the drain of the transistor M9, and is used as a first output end of the output buffer, the transistor M8 and the transistor M9 are both grounded, the base of the transistor M9 is used as a second input end of the output buffer, and the other end of the resistor R33 and the other end of the resistor R34 are mutually connected and are connected with a power supply.
Claims (9)
1. A variable gain amplifier with variable bandwidth is characterized by comprising a first-stage bandwidth gain control unit VGA1, a second-stage bandwidth gain control unit VGA2, a third-stage bandwidth gain control unit VGA3, a fourth-stage bandwidth gain control unit VGA4, a first constant current loss and adjustment elimination feedback unit, a second-stage direct current imbalance elimination feedback unit and an output buffer;
a first input end and a second input end of the first-stage bandwidth gain control unit VGA1 are jointly used as input ends of a variable gain amplifier to be connected with a signal source, a first output end of the first-stage bandwidth gain control unit VGA1 is connected with a first input end of a second-stage bandwidth gain control unit VGA2, and a second output end of the first-stage bandwidth gain control unit VGA2 is connected with a second input end of the second-stage bandwidth gain control unit VGA 2;
a first output end of the second-stage bandwidth gain control unit VGA2 is connected to a first input end of a third-stage bandwidth gain control unit VGA3 and a first input end of a first constant loss modulation cancellation feedback unit, a second output end of the second-stage bandwidth gain control unit VGA2 is connected to a second input end of a third-stage bandwidth gain control unit VGA3 and a second input end of the first constant loss modulation cancellation feedback unit, a first output end of the first constant loss modulation cancellation feedback unit is connected to a third input end of the first-stage bandwidth gain control unit VGA1, and a second output end of the first constant loss modulation cancellation feedback unit VGA1 is connected to a fourth input end of the first-stage bandwidth gain control unit VGA 1;
a first output end of the third-stage bandwidth gain control unit VGA3 is connected with a first input end of the fourth-stage bandwidth gain control unit VGA4, and a second output end of the third-stage bandwidth gain control unit VGA3 is connected with a second input end of the fourth-stage bandwidth gain control unit VGA 4;
a first output end of the fourth-stage bandwidth gain control unit VGA4 is connected to a first input end of the second dc offset cancellation feedback unit and a first input end of the output buffer, respectively, and a second output end thereof is connected to a second input end of the second dc offset cancellation feedback unit and a second input end of the output buffer, respectively, a first output end of the second dc offset cancellation feedback unit is connected to a third input end of the third-stage bandwidth gain control unit VGA3, and a second output end thereof is connected to a fourth input end of the third-stage bandwidth gain control unit VGA 3;
the first output end and the second output end of the output buffer are jointly used as the output end of the variable gain amplifier to be connected with a post-stage load;
and the control ends of the first-stage bandwidth gain control unit VGA1, the second-stage bandwidth gain control unit VGA2, the third-stage bandwidth gain control unit VGA3 and the fourth-stage bandwidth gain control unit VGA4 are all connected with a numerical control device.
2. The variable gain amplifier with variable bandwidth of claim 1, wherein the first stage bandwidth gain control unit VGA1, the second stage bandwidth gain control unit VGA2, the third stage bandwidth gain control unit VGA3 and the fourth stage bandwidth gain control unit VGA4 each comprise a transconductance stage amplifier, a transimpedance stage amplifier, a first variable capacitor array and a second variable capacitor array;
the first input end of the transconductance stage amplifier is used as the first input end of the current bandwidth gain control unit, the second input end of the transconductance stage amplifier is used as the second input end of the current bandwidth gain control unit, the first output end of the transconductance stage amplifier is connected with the first input end of the transimpedance stage amplifier through the A + end of the first variable capacitor array, and the second output end of the transconductance stage amplifier is connected with the second input end of the transimpedance stage amplifier through the A-end of the first variable capacitor array;
the first output end of the trans-impedance amplifier is connected with the B + end of the second variable capacitor array, the second output end of the trans-impedance amplifier is connected with the B-end of the second variable capacitor array, the B + end of the second variable capacitor array is used as the first output end of the current bandwidth gain control unit, and the B-end of the second variable capacitor array is used as the second output end of the current bandwidth gain control unit;
the variable resistor array is connected between the first input end and the first output end of the trans-impedance amplifier and between the second input end and the second output end of the trans-impedance amplifier;
and the control ends of the first variable capacitor array, the second variable capacitor array and the variable resistor array are connected with a numerical control device.
3. The variable gain amplifier with variable bandwidth as claimed in claim 2, wherein the first variable capacitor array and the second variable capacitor array are identical in circuit structure and each comprise n variable capacitor circuits;
each variable capacitor circuit comprises a first numerical control switch, a capacitor and a second numerical control switch which are connected in sequence, one end of the first numerical control switch, which is not connected with the capacitor, is used as an A + end of the first variable capacitor array or a B + end of the second variable capacitor array circuit, and one end of the second numerical control switch, which is not connected with the capacitor, is used as an A-end of the first variable capacitor array or a B-end of the second variable capacitor array circuit;
and the control ends of the first numerical control switch and the second numerical control switch are connected with a numerical control device.
4. The variable gain amplifier of claim 2, wherein the variable resistor arrays in the first stage of the bandwidth gain control VGA1 and the second stage of the bandwidth gain control VGA2 are coarse gain variable resistor arrays with a step size of 6 dB;
the variable resistor array in the third-stage bandwidth gain control unit VGA3 is a gain coarse adjustment variable resistor array with the step length of 3 dB;
the variable resistor array in the fourth stage bandwidth gain control unit VGA4 fine-tunes the variable resistor array for gain with a step size of 1 dB.
5. The variable gain amplifier of claim 4, wherein the coarse gain tuning variable resistor array with a step size of 6dB comprises resistor R1;
one end of the resistor R1 is connected to one end of the resistor R2 and one end of the resistor R6, and is connected to the first input end or the second input end of the transimpedance amplifier, the other end of the resistor R2, the resistor R3, the switch SW3, the resistor R4 and one end of the resistor R5 are sequentially connected, a switch SW2 is further connected between a connection node of the resistor R2 and the resistor R3 and a connection node of the resistor R4 and the resistor R5, the other end of the resistor R6, the resistor R7, the switch SW1, the resistor R8 and one end of the resistor R9 are sequentially connected, a switch SW0 is further connected between the connection node of the resistor R6 and the resistor R7 and a connection node of the resistor R8 and the resistor R9, and the other end of the resistor R1 is connected to the other end of the resistor R5 and the other end of the resistor R9, and is connected to the first output end or the second output end of the transimpedance amplifier;
and control ends of the switch SW0, the switch SW1, the switch SW2 and the switch SW3 are connected with a numerical control device.
6. The variable gain amplifier of claim 4, wherein said coarse gain tuning variable resistor array with a step size of 3dB comprises resistor R18;
one end of the resistor R18 is connected to one end of the resistor R18, one end of the resistor R18 and one end of the resistor R18, and is connected to the first input end or the second input end of the transimpedance amplifier, the other end of the resistor R18, one end of the resistor R18 and one end of the resistor R18 are sequentially connected, a switch SW 18 is further connected between a connection node of the resistor R18 and a connection node of the resistor R18 and the resistor R18, the other end of the resistor R18, the switch SW 18, the resistor R18 and one end of the resistor R18 are sequentially connected, a switch SW 18 is further connected between a connection node of the resistor R18 and a connection node of the resistor R18 and the resistor R18, one end of the other end of the resistor R18, the switch SW 18, one end of the resistor R18 and one end of the resistor R18 are further connected between the connection node SW 18 and the resistor R18, the other end of the resistor R18, the other end of the resistor R22, the other end of the resistor R26 and the other end of the resistor R30 are connected, and are connected with a first output end or a second output end of the transimpedance amplifier;
and control ends of the switch SW9, the switch SW10, the switch SW11, the switch SW12 and the switch SW13 are connected with a numerical control device.
7. The variable gain amplifier with variable bandwidth of claim 4, wherein the gain fine tuning variable resistor array with step size of 1dB comprises resistor R10;
one end of the resistor R10 is respectively connected with one end of the resistor R11, one end of the resistor R14 and the source electrode of the MOS transistor MR, and is connected with the first input end or the second input end of the trans-impedance amplifier, the other end of the resistor R11, one end of the resistor R12 and one end of the resistor R13 are connected in turn, a switch SW6 is connected to two ends of the resistor R12, the other end of the resistor R14, one end of the resistor R15, one end of the switch SW5, one end of the resistor R16 and one end of the resistor R17 are sequentially connected, a switch SW4 is connected between the connecting node of the resistor R14 and the resistor R15 and the connecting node of the resistor R16 and the resistor R17, the other end of the resistor R10, the other end of the resistor R13, the other end of the resistor R17 and the drain electrode of the MOS tube MR are all connected with the first output end or the second output end of the transimpedance amplifier, the base electrodes of the MOS transistors are respectively connected with one end of a switch SW7 and one end of a switch SW8, and the other ends of the switch SW7 and the switch SW8 are vacant;
and control ends of the switch SW4, the switch SW5, the switch SW6, the switch SW7 and the switch SW8 are connected with a numerical control device.
8. The variable gain amplifier of claim 1, wherein the first dc cancellation feedback unit and the second dc cancellation feedback unit have the same circuit structure, and each of the first dc cancellation feedback unit and the second dc cancellation feedback unit comprises a transistor M1, a transistor M2, a transistor M3, a transistor M4, and a transistor M5;
one end of the resistor R31 is used as a first input end of the first constant current loss elimination feedback unit or the second direct current offset elimination feedback unit, the other end of the resistor R31 is connected with the bases of the grounded capacitor C1 and the transistor M1, the drain of the transistor M1 is connected with the drain of the transistor M4 and the base of the transistor M4 respectively and is used as a second output end of the first constant current loss elimination feedback unit or the second direct current offset elimination feedback unit, the source of the transistor M4 and the transistor M5 are both connected with the power supply, the drain of the transistor M5 is connected with the base of the transistor M5 and is used as a first output end of the first constant current loss elimination feedback unit or the second direct current offset elimination feedback unit, the drain of the transistor M5 is further connected with the drain of the transistor M2, the source of the transistor M2 and the source of the transistor M1 are both connected with the drain of the transistor M3, the source of the transistor M3 is, the base of the transistor M3 is set to be empty, the base of the transistor M2 is respectively connected with one end of a grounded capacitor C2 and one end of a resistor R32, and the other end of the resistor R32 is used as a second input end of the first dc offset cancellation feedback unit or the second dc offset cancellation feedback unit.
9. The variable gain amplifier with variable bandwidth as claimed in claim 1, wherein the output buffer is a frequency multiplier structure comprising a transistor M6, a transistor M7, a transistor M8 and a transistor M9;
the base of the transistor M6 is used as a first input end of the output buffer, the drain of the transistor M6 is respectively connected with one end of a resistor R33 and the drain of the transistor M8 and is used as a second output end of the output buffer, the source of the transistor M6 and the source of the transistor M7 are both grounded, the drain of the transistor M7 is respectively connected with one end of a resistor R34 and the drain of the transistor M9 and is used as a first output end of the output buffer, the transistor M8 and the transistor M9 are both grounded, the base of the transistor M9 is used as a second input end of the output buffer, and the other end of the resistor R33 and the other end of the resistor R34 are connected with each other and are connected with a power supply.
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