CN103051299B - Programmable gain amplifier applied to transmitting end of communication system - Google Patents

Abstract

The invention provides a programmable gain amplifier applied to a transmitting end of a communication system, which comprises a plurality of programmable gain amplifying circuits and output buffer stages applied to the transmitting end, wherein the programmable gain amplifying circuits and the programmable gain amplifying circuits are connected in an alternating current coupling mode; the signal output end of each programmable gain amplifying circuit is connected with the signal input end of the next programmable gain amplifying circuit, and the signal output end of the last programmable gain amplifying circuit is connected with the signal input end of the output buffer stage applied to the transmitting end. The programmable gain amplifier of the embodiment of the invention can provide a larger gain adjustment range and can meet the requirements of linearity and bandwidth.

Description

A Programmable Gain Amplifier Applied to the Transmitter of Communication System

technical field

The invention relates to the technical field of integrated circuit design, and more specifically relates to a programmable gain amplifier applied to the transmitting end of a communication system.

Background technique

With the development of communication technology, wireless communication has entered the era of high-speed data transmission, wider frequency band will effectively improve the efficiency of data transmission, so ultra-wideband communication technology has become the focus of research in wireless communication systems.

A transmitter in a wireless communication system is a device used to transmit a signal at a certain frequency. In the communication system, the radio frequency front end of the transmitter modulates and sends the signal. The RF front-end usually includes basic circuit structures such as a programmable gain amplifier, a filter, or a baseband processing circuit, wherein the programmable gain amplifier is used to adjust the signal strength by adjusting its own gain to output a constant signal.

In ultra-wideband communication systems, extremely wide bandwidth is required to transmit information. Programmable gain amplifier is a very important module in the RF front-end, and its performance has a crucial impact on the performance of the entire RF front-end, especially in the use To adjust the transmitter of the output signal, an amplifier with high bandwidth, high linearity and a large gain adjustment range is required. However, the existing programmable gain amplifier is usually an open-loop circuit structure. Although it can meet the requirements of bandwidth and linearity to a certain extent, due to the limitation of the open-loop structure, the gain that can be realized by the programmable gain amplifier is very small, so its The adjustable range of the gain is also small, which cannot meet the gain requirements of the ultra-wideband communication system.

Therefore, a technical problem that needs to be urgently solved by those skilled in the art is: how to innovatively propose an amplifier structure to solve the problem that the programmable gain amplifier at the transmitting end of the communication system has a small gain adjustment range and cannot satisfy high bandwidth and high linearity at the same time. question of degree.

Contents of the invention

In view of this, the present invention provides a programmable gain amplifier applied to the transmitting end of a communication system to solve the problem that the existing programmable gain amplifier has a small gain adjustment range and cannot simultaneously satisfy high bandwidth and high linearity.

To achieve the above object, the present invention provides the following technical solutions:

A programmable gain amplifier applied to the transmitter of a communication system, comprising a plurality of programmable gain amplifier circuits and an output buffer stage applied to the transmitter, wherein,

The programmable gain amplifying circuits and the programmable gain amplifying circuit and the output buffer stage applied to the transmitter are connected in an AC coupling manner; the signal output end of each programmable gain amplifying circuit is connected to the next programmable gain amplifying circuit The signal input terminal of the last programmable gain amplifier circuit is connected to the signal input terminal of the output buffer stage applied to the transmitter.

Preferably, the plurality of programmable gain amplifier circuits have the same circuit structure, and each programmable gain amplifier circuit is a fully differential circuit structure with a symmetrical structure, including two differential branches with the same structure, wherein:

Each differential branch circuit respectively includes a differential input stage of a common-source structure connected to the signal input end and a differential output stage of a common-source structure connected to the signal output end, and a switched capacitor is connected between the differential input stage and the differential output stage Array, and connected with a feedback resistor to form a closed-loop feedback structure;

The differential input stage of one differential branch is connected to the differential input stage of the other differential branch through a switch resistor array to form a source degenerate structure.

Preferably, the switched capacitor array is composed of n capacitor switches connected in parallel, and the capacitor switch string is composed of capacitors and switches connected in series; the switched resistor array is composed of n resistor switch strings connected in parallel, and the resistor switch string is composed of two A resistor and a switch are connected in series, where n is a positive integer.

Preferably, the differential input stage includes a differential input transistor, a bias current transistor and a first current source load transistor, the gate of the differential input transistor is connected to the signal input terminal, and its source is connected to the drain of the bias current transistor, which The drain is connected to the drain of the current source load transistor; the source of the bias current transistor is connected to the power supply voltage, and the gate is connected to the bias voltage; the source of the current source load transistor is grounded, and the gate is connected to the bias voltage;

The differential output stage includes a common source transistor and a second current source load transistor, the drain of the common source transistor is connected to the drain of the second current source load transistor, and is connected to the signal output terminal, and its gate is connected to the first current source load The drain of the second current source is grounded; the gate of the second current source load transistor is connected to a bias voltage, and its source is connected to a power supply voltage;

The switched capacitor array is connected between the drain of the differential input transistor and the drain of the common source transistor;

The feedback resistor is connected between the source of the differential input transistor and the drain of the second current source load transistor.

The switch resistor array is connected between the sources of the two differential input transistors in the two differential branches.

Preferably, the differential input transistor and the bias current transistor are PMOS transistors, the first current source load transistor is an NMOS transistor, the common source transistor is an NMOS transistor, and the second current source load transistor is a PMOS transistor.

Preferably, the output buffer stage applied to the transmitter is a fully differential circuit structure with a symmetrical structure, and each differential branch circuit includes a first transistor, a second transistor and a third transistor, wherein,

The gate of the first transistor is connected to a signal input terminal, its source is connected to the drain of the second transistor, and its drain is connected to the drain of the third transistor and connected to a signal output terminal;

The source of the second transistor is connected to a power supply voltage, and its gate is connected to a bias voltage;

The gate and drain of the third transistor are connected to form a diode, and the source is grounded;

The source of the first transistor in one differential branch is connected to the source of the first transistor in the other differential branch through two source degenerate resistors connected in series.

Preferably, both the first transistor and the second transistor are PMOS transistors, and the third transistor is an NMOS transistor.

Preferably, the signal output terminal of the amplifying circuit is connected to the signal input terminal of the next amplifying circuit through a pair of differentially separated DC capacitors, and the signal output terminal of the last amplifying circuit is connected to the signal input terminal of the output buffer stage through a pair of differentially separated DC capacitors.

Preferably, the programmable gain amplifier specifically includes five programmable gain amplifier circuits.

Preferably, the gain variation ranges of the four programmable gain amplifier circuits in the programmable gain amplifier are the same, and the gain adjustment step of the four programmable gain amplifier circuits is larger than the gain adjustment step of the other programmable gain amplifier circuit long.

It can be seen from the above technical solutions that, compared with the prior art, the present invention provides a programmable gain amplifier applied to the transmitting end of a communication system, the programmable gain amplifier includes a plurality of programmable gain amplifier circuits, and is cascaded Each programmable gain amplifying circuit can provide a gain adjustment range, so cascading multiple programmable gain amplifying circuits can improve the gain adjustment range of the entire amplifier. Moreover, the programmable gain amplifier circuit may adopt a fully differential source degenerate common source amplifier circuit structure, and the source degenerate structure improves linearity. In addition, the programmable gain amplifier circuit forms a closed-loop feedback structure, the gain depends on the ratio of the feedback resistance to the source degeneracy resistance, and the bandwidth depends on the product of the feedback resistance and the compensation capacitor, wherein both the source degeneracy resistance and the compensation capacitor can use switches In the array form, gain control can be realized by controlling different switches and selecting different source degeneracy resistance and compensation capacitance, which ensures that the bandwidth remains unchanged while the gain changes. And each amplifying circuit only needs to provide a small gain, thus avoiding the problem of affecting the linearity of the amplifier when the gain is large, and meeting the requirements of high bandwidth, high linearity and a large gain adjustment range. In addition, the programmable gain amplifier of the present invention adopts an output buffer stage applied to the transmitter, so that the amplifier can drive the load of the transmitter.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present invention, and those skilled in the art can also obtain other drawings according to the provided drawings without creative work.

Fig. 1 is a schematic diagram of the circuit structure of an embodiment of a programmable gain amplifier applied to the transmitting end of a communication system according to the present invention;

Fig. 2 is the schematic diagram of the circuit structure of an embodiment of the amplifying circuit in the programmable gain amplifier of the present invention;

Fig. 3 is a schematic structural diagram of an equivalent circuit structure of an amplifying circuit in a programmable gain amplifier of the present invention;

FIG. 4 is a schematic diagram of the circuit structure of the output buffer stage applied to the transmitter in the programmable gain amplifier of the present invention.

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The embodiment of the present invention discloses a programmable gain amplifier applied to the transmitting end of a communication system. The programmable gain amplifier is composed of a plurality of programmable gain amplifier circuits connected in cascade, and each programmable gain amplifier circuit can provide a gain Adjustment range, higher bandwidth, and higher linearity, cascading multiple amplifier circuits can improve the gain adjustment range of the entire amplifier, and at the same time ensure the bandwidth and linearity indicators. The programmable gain amplifying circuit can adopt a source-degenerate and common-source amplifying circuit structure in a fully differential form, and the linearity is improved by using a source-degenerate structure; and the amplifying circuit forms a closed-loop feedback structure, and the gain depends on the feedback resistance and the source degenerate The ratio of the parallel resistors, the bandwidth depends on the product of the feedback resistor and the compensation capacitor, so a wide bandwidth can be achieved by selecting the appropriate feedback resistor and compensation capacitor; at the same time, the source degenerate resistor and the compensation capacitor are switch arrays, by controlling different switches , and the gain and bandwidth can be adjusted, each amplifying circuit only needs to provide a small gain, thus avoiding the problem of affecting the linearity of the amplifier when the gain is large, and meeting the requirements of high bandwidth and high linearity in ultra-wideband communication systems And gain adjustment range requirements. The programmable gain amplifier of the present invention adopts the output stage applied to the transmitting end, so that the amplifier can drive the load of the transmitting end.

Referring to FIG. 1 , it shows a schematic diagram of a circuit structure of an embodiment of a programmable gain amplifier applied to a transmitting end of a communication system according to the present invention.

In the communication system, especially in the ultra-wideband communication system, the programmable gain amplifier is an important module of the RF front-end, and its performance is very important for the RF front-end, especially at the transmitter, which requires a wide range of gain adjustment and high linearity And a high-bandwidth programmable gain amplifier to adjust the transmit signal to obtain a signal with a constant amplitude, which is output to the analog back-end.

The programmable gain amplifier of the present invention may include a plurality of programmable gain amplifier circuits and an output buffer stage applied to the transmitting end. Wherein, the number of the plurality of programmable gain amplifying circuits is specifically set according to the performance of each programmable gain amplifying circuit, and the performance includes requirements such as available gain range, bandwidth, linearity, and power consumption.

In this embodiment, five programmable gain amplifier circuits may be included, so in conjunction with FIG. 1, the programmable gain amplifier may include a first stage programmable gain amplifier circuit 101, a second stage programmable gain amplifier circuit 102, a third stage programmable gain amplifier circuit A stage programmable gain amplifier circuit 103, a fourth stage programmable gain amplifier circuit 104, a fifth stage programmable gain amplifier circuit 105, and an output buffer stage 106 applied to the transmitting end.

It should be noted that, the present invention does not specifically limit the number of the programmable gain amplifier circuits. In practical applications, the programmable gain amplifier can be cascaded with five programmable gain amplifier circuits to ensure that various indicators of the programmable gain amplifier can be realized.

Wherein, the programmable gain amplifying circuits and between the programmable gain amplifying circuits and the output buffer stage applied to the transmitting end are connected in an AC coupling manner, and the signal output end of each programmable gain amplifying circuit is connected to the next programmable gain amplifying circuit. The signal input terminal of the gain amplifier circuit, and the signal output terminal of the last programmable gain amplifier circuit are connected to the signal input terminal of the output buffer stage.

Specifically, the signal output terminal of the programmable gain amplifier circuit is connected to the signal input terminal of the next programmable gain amplifier circuit through a pair of differential separation capacitors 107, and the signal output terminal of the last programmable gain amplification circuit is connected to the signal input terminal of the next programmable gain amplification circuit through a pair of differential separation direct current capacitors 107. Capacitor 107 is connected to the signal input terminal of the output buffer stage. This method of AC coupling with DC blocking capacitors can eliminate the DC offset phenomenon.

In this embodiment, a plurality of programmable gain amplifier circuits are included and connected through AC coupling, and each programmable gain amplifier circuit can provide an adjustable gain range, wider bandwidth, higher linearity, and more The cascading of multiple programmable gain amplifier circuits ensures the bandwidth and linearity of the programmable gain amplifier, and increases the adjustable range of the gain, so it can meet the high bandwidth, high linearity and gain adjustment range of the programmable gain amplifier. big request.

Wherein, the structure of the plurality of programmable gain amplifier circuits is the same, and each programmable gain amplifier circuit is a fully differential circuit structure with a symmetrical structure, including two differential branches with the same structure, and each differential branch circuit includes a connection A differential input stage with a common-source structure at the signal input terminal and a differential output stage with a common-source structure connected to the signal output terminal, a switched capacitor array connected between the differential input stage and the differential output stage, and a feedback resistor connected to form a closed-loop feedback circuit; The differential input stage of one differential branch is connected to the differential input stage of the other differential branch through a switch resistor array to form a source degenerate structure.

Referring specifically to FIG. 2 , it shows a schematic structural diagram of an embodiment of a programmable gain amplifying circuit in the programmable gain amplifier of the present invention.

For the convenience of description, it is assumed that the two differential branches are respectively the first differential branch and the second differential branch, and the signal input terminal includes a signal input terminal Vinp and another signal input terminal Vinn, and the signal input terminal The output terminal includes a signal output terminal Voutp and another signal output terminal Voutn

The first differential branch circuit includes a first differential input stage 201 of a common source structure connected to the signal input terminal Vinp and a first differential output stage 202 of a common source structure connected to the signal output terminal Voutp, and the second differential branch The circuit includes a second differential input stage 203 of a common-source structure connected to the signal input terminal Vinn and a second differential output stage 204 of a common-source structure connected to the signal output terminal Voutn.

A first switched capacitor array 205 is connected between the first differential input stage 201 and the second differential output stage 202, and a first feedback resistor 206 is connected to form a closed-loop feedback circuit; the second differential input stage 203 and the second differential output stage A second switched capacitor array 207 and a second feedback resistor 208 are connected between the two differential output stages 204 to form a closed-loop feedback circuit.

The first differential input stage 201 and the second differential input stage 203 are connected through a switch resistor array 209 to form a source degenerate structure.

The capacitor contained in the switched capacitor array is the compensation capacitor of the circuit, and the resistor contained in the switched resistor array is the source degenerate resistance.

The amplifying circuit of this implementation adopts a source degenerate circuit structure, which improves the linearity of the circuit. At the same time, the amplifying circuit forms a closed-loop feedback structure. The gain value depends on the ratio of the feedback resistance to the source degeneracy resistance, and the bandwidth depends on the feedback resistance and The product of the compensation capacitance, and the source degeneracy resistance and the compensation capacitance are in the form of a switch array. The appropriate source degeneracy resistance and compensation capacitance can be selected by controlling the switch to meet the requirements of high bandwidth and adjustable gain.

Wherein, specifically, referring to FIG. 2, the first differential input stage 201 includes a differential input transistor M11, a bias current transistor M21, and a first current source load transistor M31, and the gate of the differential input transistor M11 is connected to the signal input terminal Vinp, its source is connected to the drain of the bias current transistor M21, and its drain is connected to the drain of the first current source load transistor M31; the source of the bias current transistor M21 is connected to the power supply voltage, and its gate is connected to the bias Set the voltage Vbp; the source of the first current source load transistor M31 is grounded, and the gate thereof is connected to the bias voltage Vbn.

The second differential input stage 203 has the same structure as the first differential input stage 201, including a differential input transistor M12, a bias current transistor M22 and a first current source load transistor M32, and the gate of the differential input transistor M12 is connected to Signal input terminal Vinn, its source is connected to the drain of the bias current transistor M22, its drain is connected to the drain of the first current source load transistor M32; the source of the bias current transistor M22 is connected to the power supply voltage, and its gate The source of the first current source load transistor M32 is grounded, and the gate of the first current source load transistor M32 is connected to the bias voltage Vbn.

The first differential output stage 202 includes a common source transistor M41 and a second current source load transistor M51, the drain of the common source transistor M41 is connected to the drain of the second current source load transistor M51, and connected to the signal output terminal Voutp , the gate of which is connected to the drain of the first current source load transistor M31, and its source is grounded; the gate of the second current source load transistor M51 is connected to the bias voltage Vbp, and its source is connected to the power supply voltage.

The second differential output stage 204 has the same structure as the second differential output stage 202, including a common source transistor M42 and a second current source load transistor M52, the drain of the common source transistor M42 and the second current source load transistor M52 The drains are connected to the signal output terminal Voutn, the gate is connected to the drain of the first current source load transistor M32, and its source is grounded; the gate of the second current source load transistor M52 is connected to the bias voltage Vbp, which The source is connected to the supply voltage.

The first switched capacitor array 205 is connected between the drain of the differential input transistor M11 and the drain of the common source transistor M41, that is, one end of the first switched capacitor array 205 is connected to the drain of the differential input transistor M11, and the other end Connected to the drain of the common source transistor M41; the second switched capacitor array 207 is connected between the drain of the differential input transistor M12 and the drain of the common source transistor M42, that is, one end of the second switched capacitor array 207 is connected to the differential The drain of the input transistor M12 is connected, and the other end is connected to the drain of the common source transistor M42.

The first feedback resistor 206 is connected between the source of the differential input transistor M11 and the drain of the second current source load transistor M51, that is, one end of the first feedback resistor 206 is connected to the source of the differential input transistor M11, The other end is connected to the drain of the second current source load transistor M51; the second feedback resistor 208 is connected between the source of the differential input transistor M12 and the drain of the second current source load transistor M52, that is, the first One end of the second feedback resistor 208 is connected to the source of the differential input transistor M12, and the other end is connected to the drain of the second current source load transistor M52.

The switch resistor array 209 is connected between the source of the differential input transistor M11 and the source of the differential input transistor M12, that is, one end of the switch resistor array 209 is connected to the source of the differential input transistor M11, and the other end is connected to the source of the differential input transistor M11. The source of M12 is connected.

Wherein, the switch resistor array 209 is composed of n resistor switch strings connected in parallel, and the resistor switch string is composed of two resistors and switches connected in series; the first switch capacitor array 205 and the second switch capacitor array 207 are both composed of n capacitive switches are connected in series and parallel, and the capacitive switch string is composed of capacitors and switches in series, wherein n is a positive integer.

It can be seen from FIG. 2 that in the first switched capacitor array 205, the capacitor switch string includes a capacitor C _n1 and a switch S _n1 , where n=1, 2, 3... For example, the first switched capacitor string includes Capacitor C ₁₁ and switch S ₁₁ , the second switched capacitor string includes capacitor C ₂₁ and switch S ₂₁ . . . the nth switched capacitor string includes capacitor C _n1 and switch S _n1 . In the second switched capacitor array 207, the capacitor switch string includes capacitor C _n2 and switch S _n2 , where n=1, 2, 3... For example, the first capacitor switch string includes capacitor C ₁₂ and switch S n2 . Switch S ₁₂ , the second switched capacitor string includes capacitor C ₂₂ and switch S ₂₂ . . . the nth switched capacitor string includes capacitor C _n2 and switch S _n2 .

In the switch resistor array 209, the resistor switch string includes resistor R _Sn1 , resistor R _Sn2 and switch S _n , such as the first resistor switch string includes resistor R _s11 , R _s12 and switch S ₁ , and the second resistor The switch string includes resistors R _s21 , R _s22 and switch S ₂ . . . The nth resistor switch string includes resistors R _sn1 , R _sn2 and switch S _n .

The first switched capacitor array 205 and the second switched capacitor array 207 are two differential compensation capacitors in the differential circuit structure, and R _Sn1 and R _Sn2 in the switched resistor array are respectively two differential source degenerate resistors.

Since both the compensation capacitor and the source degeneracy resistance are in the form of a switch array, different compensation capacitors and source degeneracy resistances can be obtained by selecting different switches. For details, refer to FIG. 3 , which shows an equivalent circuit structure diagram of a programmable gain amplifier circuit according to the present invention.

In actual work, the differential input transistor M11 and the differential input transistor M12 are a pair of differential input transistors, which are used to convert the input voltage signal of its gate into a current signal, and the bias current transistor M21 and the bias current transistor M22 are used as A current source for a differential input that forces a constant current through the differential input transistor pair. The input signal is transmitted to the source degenerate resistance through the differential input transistor pair, so that the linearity of the conversion transconductance of the input signal is improved. The conversion transconductance is the transconductance of the differential input pair transistor, and the source degenerate structure is adopted. The conversion transconductance performance It is the reciprocal of the source degenerate resistance, which is a linear item, so the linearity of each amplifier circuit is guaranteed, thereby ensuring the linearity of the amplifier.

2 and 3, in the programmable gain amplifier circuit of this embodiment, the gain value depends on the ratio of the feedback resistance to the source degeneracy resistance, and the calculation formula is:

A _v ＝1+R _f /R _s

Among them, R _S is the source degenerate resistance selected in the differential branch, which is R _sn1 or R _sn2 in the switch resistor array; R _f is the feedback resistance in the differential branch, which is the first feedback resistor 206 or the second feedback resistor Resistor 208. It can be known from this formula that the gain of the amplifier circuit depends on the ratio of the two feedback resistors.

The bandwidth is approximated as:

ω _-3dB ≈1/R _f *C

Capacitor C is the compensation capacitor selected by the differential branch circuit, which is C _n1 or C _n1 in the capacitor switch array. The bandwidth of the amplifying circuit is not only related to the compensation capacitor, but also related to the feedback resistor.

From the above two formulas, it can be seen that keeping the feedback resistance R _f constant, and selecting different source degeneracy resistance R _S and compensation capacitance C by controlling the switch, different gains and bandwidths can be obtained.

Wherein, the value of n and the capacitance value or resistance value in each switch array are specifically set according to the requirements for bandwidth and gain variation range in different actual situations.

In the field of integrated circuit design, the differential input transistor and the bias current transistor may be PMOS (P-type Metal-Oxide-Semiconductor, Metal-Oxide-Semiconductor) transistors, and the first current source load transistor may be NMOS A transistor, the common source transistor may be an NMOS (N-type MOS transistor) transistor, and the second current source load transistor may be a PMOS transistor.

Since the compensation capacitor and the source degenerate resistance in the programmable gain amplifier circuit are both in the form of a switch array, by controlling the switch of the switch resistance array, resistors with different resistance values can be selected as the source degenerate resistance. The ratio of the parallel resistance and the interstage feedback resistance is determined. Therefore, keeping the feedback resistance constant, different gains can be obtained according to different source degenerate resistances selected. Capacitors of different values can be selected by controlling the switch of the switched capacitor array. Since the bandwidth of the amplifying circuit depends on the interstage feedback resistance and the feedback capacitance, and the feedback resistance remains unchanged, different bandwidths can be obtained according to different capacitance values, and the The programmable gain amplification circuit adopts the source degenerate circuit structure, which improves the linearity.

In this embodiment of the present invention, the programmable gain amplifier includes a plurality of the above-mentioned programmable gain amplifier circuits, and is connected in the form of AC coupling, and each programmable gain amplifier circuit can provide higher linearity and higher bandwidth. And a gain adjustment range, while using multiple programmable amplifier circuits in the form of AC coupling and cascading, the gain adjustment range is increased on the premise of ensuring bandwidth and linearity. Each programmable gain amplifier circuit only needs to provide a small gain adjustment range, and multiple programmable amplifier circuits can be cascaded to provide a larger gain adjustment range, which avoids the need for a programmable amplifier circuit with a large gain. , the effect on the linearity of the circuit.

In addition, since the follow-up circuit at the transmitting end is usually a low-pass filter, its load is composed of a small capacitor and a large resistance of tens of kiloohms connected in parallel, so in order to be able to drive a larger load, the programmable gain amplifier of the present invention describes The output buffer stage 106 applied to the transmitter is an output buffer stage capable of driving a large load.

Referring to FIG. 4 , it shows a schematic structural diagram of an embodiment of an output buffer stage applied to a transmitter in a programmable gain amplifier of the present invention. The output buffer stage applied to the transmitter is a fully differential circuit structure with a symmetrical structure, and each differential branch includes a first transistor, a second transistor and a third transistor,

The gate of the first transistor is connected to a signal input terminal, its source is connected to the drain of the second transistor, and its drain is connected to the drain of the third transistor and connected to a signal output terminal;

The source of the second transistor is connected to a power supply voltage, and its gate is connected to a bias voltage;

The gate and drain of the third transistor are connected to form a diode, and the source is grounded;

The source of the first transistor in one differential branch is connected to the source of the first transistor in the other differential branch through two source degenerate resistors connected in series, so that the output buffer stage also forms a source degenerate structure.

In conjunction with FIG. 4, for the convenience of description, the two differential branches are assumed to be a first differential branch and a second differential branch, and the first differential branch includes a first transistor Mp1, a second transistor Mp3 and a second transistor Mp3. Three transistors Mn1, wherein: the gate of the first transistor Mp1 is connected to a signal input terminal Vinp1, its source is connected to the drain of the second transistor Mp3, its drain is connected to the drain of the third transistor Mn1, and connected to the signal output Terminal Voutn1; the source of the second transistor Mp3 is connected to the power supply voltage, and the gate is connected to the bias voltage Vbp; the gate and drain of the third transistor Mn1 are connected to form a diode, and the source is grounded.

Similarly, the second differential branch includes: a first transistor Mp2, a second transistor Mp4, and a third transistor Mn2, wherein: the gate of the first transistor Mp2 is connected to another signal input terminal Vinn1, and its source is connected to the second transistor Mp2. The drain of the transistor Mp4 is connected, and its drain is connected to the drain of the third transistor Mn2, and connected to another signal output terminal Voutp1; the source of the second transistor Mp4 is connected to the power supply voltage, and its gate is connected to the bias voltage Vbp; The gate and drain of the three transistors Mn2 are connected to form a diode, and the source is grounded.

The source of the first transistor Mp1 and the source of the first transistor Mp2 are connected through two source degeneracy resistors connected in series, and the two source degeneracy resistors include a source degeneracy resistor R _S1 and a source degeneracy resistor Resistor R _S2 .

Wherein, the first transistor and the second transistor may be PMOS transistors, and the third transistor may be an NMOS transistor.

In practical applications, by controlling different switches in the switched resistor array and switched capacitor array in each stage of the amplifying circuit, different gains and bandwidths can be obtained, achieving a large dynamic range of gain, while ensuring high bandwidth and high linearity degree requirements.

Taking the programmable gain amplifier including five programmable gain amplifier circuits as an example, in order to meet the requirements of the communication system transmitter for the gain adjustment range, the gain variation range of the four programmable gain amplifier circuits in the programmable gain amplifier is set are the same, and the gain adjustment steps of the four programmable gain amplifying circuits are larger than the gain adjusting step of the other amplifying circuit. For example, in order to make the achievable gain variation range of the amplifying circuit 0-50dB (decibel), the gain adjustment step size is 2dB, and the gain adjustment step size refers to the change amount of each gain change. In the case of ensuring high linearity, each stage of amplification circuit adopts the form of five-stage cascading, and each stage provides a small dynamic range of gain. By controlling different switch combinations and selecting different numbers and values of capacitors and resistors, the first four stages of amplifier circuits can achieve coarse tuning of the gain. The dynamic range of gain achieved by each stage is 0-12dB, and the gain adjustment step size is 6dB. The fifth-stage amplifying circuit realizes the fine tuning of the gain, and the achievable dynamic change range of the gain is 0-6dB, and the gain adjustment step is 2dB. At the same time, controlling the switch can ensure the high bandwidth of the amplifier, which can reach hundreds of megahertz, and meets the high bandwidth requirement of the ultra-wideband communication system.

Each embodiment in this specification is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same and similar parts of each embodiment can be referred to each other.

The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (9)

1. A programmable gain amplifier applied to the transmitter of a communication system, characterized in that it comprises a plurality of programmable gain amplifier circuits and an output buffer stage applied to the transmitter, wherein, The programmable gain amplifying circuits and the programmable gain amplifying circuit and the output buffer stage applied to the transmitter are connected in an AC coupling manner; the signal output end of each programmable gain amplifying circuit is connected to the next programmable gain amplifying circuit The signal input end of the last programmable gain amplifier circuit is connected to the signal input end of the output buffer stage applied to the transmitter; Wherein, the plurality of programmable gain amplifier circuits have the same circuit structure, and each programmable gain amplifier circuit is a fully differential circuit structure with a symmetrical structure, including two differential branches with the same structure, wherein: Each differential branch circuit respectively includes a differential input stage of a common-source structure connected to the signal input end and a differential output stage of a common-source structure connected to the signal output end, and a switched capacitor is connected between the differential input stage and the differential output stage Array, and connected with a feedback resistor to form a closed-loop feedback structure; The differential input stage of one differential branch is connected to the differential input stage of the other differential branch through a switch resistor array to form a source degenerate structure. 2. programmable gain amplifier according to claim 1, is characterized in that, described switched capacitor array is made up of n capacitive switch series-parallel connections, and described capacitor switch string is made up of electric capacity and switch series connection; Described switched resistor array is made up of n resistor switches are connected in series and parallel, and the resistor switch string is composed of two resistors and switches in series, wherein n is a positive integer. 3. The programmable gain amplifier according to claim 2, wherein the differential input stage comprises a differential input transistor, a bias current transistor and a first current source load transistor, and the gate of the differential input transistor is connected to the signal input terminal, its source is connected to the drain of the bias current transistor, and its drain is connected to the drain of the current source load transistor; the source of the bias current transistor is connected to the power supply voltage, and its gate is connected to the bias voltage; the current source The source of the load transistor is grounded and its gate is connected to the bias voltage; The differential output stage includes a common source transistor and a second current source load transistor, the drain of the common source transistor is connected to the drain of the second current source load transistor, and is connected to the signal output terminal, and its gate is connected to the first current source load The drain of the second current source is grounded; the gate of the second current source load transistor is connected to a bias voltage, and its source is connected to a power supply voltage; The switched capacitor array is connected between the drain of the differential input transistor and the drain of the common source transistor; The feedback resistor is connected between the source of the differential input transistor and the drain of the second current source load transistor; The switch resistor array is connected between the sources of the two differential input transistors in the two differential branches. 4. The programmable gain amplifier according to claim 3, wherein the differential input transistor and the bias current transistor are PMOS transistors, the first current source load transistor is an NMOS transistor, and the common source transistor is An NMOS transistor, the second current source load transistor is a PMOS transistor. 5. The programmable gain amplifier according to claim 1, wherein the output buffer stage applied to the transmitter is a fully differential circuit structure with symmetrical structure, and each differential branch includes a first transistor, a second transistor and The third transistor, where, The gate of the first transistor is connected to a signal input terminal, its source is connected to the drain of the second transistor, and its drain is connected to the drain of the third transistor and connected to a signal output terminal; The source of the second transistor is connected to a power supply voltage, and its gate is connected to a bias voltage; The gate and drain of the third transistor are connected to form a diode, and the source is grounded; The source of the first transistor in one differential branch is connected to the source of the first transistor in the other differential branch through two source degenerate resistors connected in series. 6. The programmable gain amplifier according to claim 5, wherein the first transistor and the second transistor are both PMOS transistors, and the third transistor is an NMOS transistor. 7. Programmable gain amplifier according to claim 1, is characterized in that, the signal output end of amplifying circuit is connected the signal input end of next amplifying circuit by a pair of differential separation capacitors, and the signal output end of last amplifying circuit passes through A pair of differential DC capacitors are connected to the signal input terminals of the output buffer stage. 8. The programmable gain amplifier according to claim 1, wherein the programmable gain amplifier specifically comprises five programmable gain amplifier circuits. 9. programmable gain amplifier according to claim 7, is characterized in that, four programmable gain amplifier circuit gain variation ranges in the programmable gain amplifier are identical, and the gain of described four programmable gain amplifier circuits The adjustment step is larger than the gain adjustment step of another programmable gain amplifying circuit.