CN111816624A - Wafer-level chip packaging structure and packaging process thereof - Google Patents
Wafer-level chip packaging structure and packaging process thereof Download PDFInfo
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- CN111816624A CN111816624A CN202010698631.0A CN202010698631A CN111816624A CN 111816624 A CN111816624 A CN 111816624A CN 202010698631 A CN202010698631 A CN 202010698631A CN 111816624 A CN111816624 A CN 111816624A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/111—Manufacture and pre-treatment of the bump connector preform
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention discloses a wafer-level chip packaging structure which comprises a wafer, wherein a metal welding pad is arranged on the wafer, a metal contact is correspondingly arranged on the metal welding pad, a plastic packaging layer is coated outside the wafer and the metal welding pad, and the metal contact is partially positioned outside the plastic packaging layer. The invention also discloses a wafer-level chip packaging process, which comprises the following steps: arranging a wafer on the carrying plate, and arranging at least two spaced metal welding pads on the surface of the wafer; implanting a solder ball on the metal pad; melting the solder balls to form metal contacts; cutting a wafer to form a groove; the groove, the metal welding pad and the metal contact on the wafer are sealed in a plastic mode; polishing and thinning the first plastic packaging layer on the upper part of the wafer to expose part of the metal contact; grinding the lower part of the wafer to be thinned so as to form a thinned wafer; and carrying out plastic packaging treatment on the lower part of the wafer to form a second plastic packaging layer. The packaging of a plurality of chips can be realized, and the packaging efficiency is improved; on the basis of the existing equipment, the packaging thickness of the chip is reduced, and the cost is reduced.
Description
Technical Field
The invention relates to the technical field of wafer-level chip packaging, in particular to a wafer-level chip packaging structure and a packaging process thereof.
Background
The purpose of chip package is mainly to mount the shell for semiconductor integrated circuit chip, which plays the role of placing, fixing, sealing, protecting chip and enhancing electrothermal performance, and is also the bridge for communicating the chip internal world with external circuit-the connection points on the chip are connected to the pins of the package shell by wires, and these pins are connected with other devices by wires on the printed board. Therefore, the package plays an important role for both the CPU and other LSI integrated circuits. The wafer level chip packaging technology is a technology for obtaining a single finished chip by cutting after a whole wafer is subjected to packaging test, the size of the packaged chip is consistent with that of a bare chip, and the size of the packaged IC can be greatly reduced.
The conventional chip packaging technology is provided with the lead and the lead, so that the thickness of the packaging structure is large, and the limitation is larger and larger in the field with strict limitation on the thickness.
Disclosure of Invention
In order to solve the technical defects, the technical scheme adopted by the invention is to provide a wafer-level chip packaging structure which comprises a wafer, wherein a metal welding pad is arranged on the wafer, a metal contact is correspondingly arranged on the metal welding pad, a plastic packaging layer is coated outside the wafer and the metal welding pad, and the metal contact is partially positioned outside the plastic packaging layer.
Furthermore, the peripheral sides of the metal contacts are wrapped in the plastic package layer, and the upper surfaces of the metal contacts and the upper surface of the plastic package layer are located on the same horizontal plane.
Furthermore, the upper surface and the lower surface of the metal contact are both circular, and the diameter of the upper surface is larger than that of the lower surface.
The invention also provides a wafer-level chip packaging process, which comprises the following steps:
s1: arranging a wafer on a carrying plate, and printing and forming at least two metal welding pads arranged at intervals on the surface of the wafer;
s2: implanting a solder ball on the metal pad and cooling;
s3: melting the solder balls by a melting process to form metal contacts;
s4: cutting a wafer to form a groove;
s5: carrying out plastic packaging treatment on the groove, the metal welding pad and the metal contact on the wafer to form a first plastic packaging layer;
s6: polishing and thinning the first plastic packaging layer on the upper part of the wafer to expose part of the metal contact;
s7: grinding the lower part of the wafer to be thinned so as to form a thinned wafer;
s8: and carrying out plastic packaging treatment on the lower part of the thinned wafer to form a second plastic packaging layer.
Further, the thickness of the thinned wafer is 150-300 um.
Further, the thickness of the metal pad is 10-50 um.
Further, the thickness of the thinned metal contact is 40-60 um.
Further, the height of first plastic-sealed layer after the attenuate is 50-110um, the height of second plastic-sealed layer is 40-150 um.
Compared with the prior art, the technical scheme of the invention has the beneficial effects that:
the wafer-level chip packaging structure provided by the invention can realize packaging of a plurality of chips, and improves the packaging efficiency; the packaging thickness of the chip is reduced and the cost is reduced on the basis of the existing equipment; and the wafer is wrapped in the plastic packaging layer, so that the wafer chip is effectively protected.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a single wafer chip of a wafer level chip package structure according to an embodiment of the present invention;
FIG. 2 is a flow chart of a wafer level chip packaging process according to an embodiment of the present invention;
fig. 3-12 are schematic views of a wafer level chip package structure corresponding to each step of a wafer level chip package process according to an embodiment of the invention.
The reference numbers are as follows:
1. the chip comprises a wafer, 1a, a groove, 2, a metal welding pad, 3, a metal contact, 4, a plastic packaging layer, 41, a first plastic packaging layer, 42, a second plastic packaging layer, 5, a carrying plate, 6 and a welding ball.
Detailed Description
The invention is further described with reference to the following figures and specific examples.
Example 1
Referring to fig. 1-12, a wafer level chip package structure provided by the present invention includes a wafer 1, a plurality of metal pads 2 are disposed on the wafer 1, each metal pad 2 is correspondingly disposed with a metal contact 3, a molding layer 4 is coated outside the wafer 1 and the metal pad 2, and a portion of the metal contact 3 is located outside the molding layer 4.
Specifically, the wafer 1 is a thinned wafer, and the thickness d1 of the thinned wafer is 150-300 um. Specifically, the thickness of the metal pad 2 is 10-50 um. The metal pad 2 is made of solder paste, silver paste, or the like.
In order to avoid the displacement of the metal pad 2 and the metal contact 3 and facilitate the mounting, specifically, the peripheral side of the metal contact 3 is wrapped in the plastic packaging layer 4, and the upper surface of the metal contact 3 and the upper surface of the plastic packaging layer 4 are located on the same horizontal plane. The upper surface and the lower surface of the metal contact 3 are both planes, and the peripheral side of the metal contact 3 is a cambered surface. The upper and lower surfaces of the metal contact 3 are both circular, and the diameter of the upper surface is larger than that of the lower surface. The metal contact 3 is made of solder balls, and the thickness of the metal contact 3 is 40-60 um. The spacing between two adjacent metal contacts 3 is determined by the size of a single wafer chip.
The plastic package layer 4 is made of epoxy resin.
The invention also provides a wafer-level chip packaging process, which comprises the following steps:
s1: arranging a wafer 1 on a carrying plate 5, and printing and forming at least two metal welding pads 2 arranged at intervals on the surface of the wafer 1;
s2: implanting a solder ball 6 on the metal pad 2 and cooling;
s3: melting the solder balls 6 by a melting process to form metal contacts 3;
s4: cutting a groove 1a on the surface of the wafer 1;
s5: carrying out plastic packaging treatment on the groove 1a, the metal welding pad 2 and the metal contact 3 on the wafer 1 to form a first plastic packaging layer 41;
s6: polishing and thinning the first plastic package layer 41 on the upper part of the wafer 1 to expose part of the metal contact 3;
s7: polishing the lower part of the wafer 1 to thin the wafer to form a thinned wafer;
s8: and turning over the thinned wafer, carrying out plastic packaging treatment on the lower part of the thinned wafer to form a second plastic packaging layer 42, and finally cutting the thinned wafer into single finished products.
Specifically, the metal pad 2 is made of solder paste, silver paste, or the like. The solder balls 6 are firmly fixed to the wafer 1 by solder paste.
Specifically, the melting process is a reflow process, and the melting temperature is related to the melting temperature of the solder balls 6.
The depth of the groove 1a is 200-350 um. The cutting equipment adopts a diamond cutter, and the cutting process adopts half-cut through to prevent the wafer 1 from shifting.
The thickness of the metal pad 2 is 10-50 um. The thickness of the wafer before thinning is 380-635um, and the thickness d1 of the thinned wafer is 150-300 um. The grinding equipment is a grinding wheel, and the thickness of the thinned metal contact 3 is 40-60 um. The thickness of the first molding layer 41 before thinning is 170-250um, the thickness d2 of the thinned first molding layer 41 is 50-110um, and the thickness d3 of the second molding layer 42 is 40-150 um. The thickness of the finished product is 240-560 um.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.
Claims (8)
1. A wafer level chip package structure is characterized in that: including wafer (1), be equipped with metal bonding pad (2) on wafer (1), it is equipped with metal contact (3) to correspond on metal bonding pad (2), the outer cladding of wafer (1) and metal bonding pad (2) has plastic envelope layer (4), metal contact (3) part is located outside plastic envelope layer (4).
2. The wafer-level chip package structure of claim 1, wherein: the periphery of the metal contact (3) is wrapped in the plastic packaging layer (4), and the upper surface of the metal contact (3) and the upper surface of the plastic packaging layer (4) are located on the same horizontal plane.
3. The wafer-level chip package structure of claim 2, wherein: the upper surface and the lower surface of the metal contact (3) are both circular, and the diameter of the upper surface is larger than that of the lower surface.
4. A wafer level chip packaging process is characterized in that: the method comprises the following steps:
s1: arranging a wafer (1) on a carrying plate (5), and printing and forming at least two metal welding pads (2) arranged at intervals on the surface of the wafer (1);
s2: implanting a solder ball (6) on the metal pad (2) and cooling;
s3: melting the solder balls (6) by a melting process to form metal contacts (3);
s4: cutting a wafer (1) to form a groove (1 a);
s5: carrying out plastic packaging treatment on the groove (1a) on the wafer (1), the metal welding pad (2) and the metal contact (3) to form a first plastic packaging layer (41);
s6: grinding and thinning the first plastic packaging layer (41) on the upper part of the wafer (1) to expose part of the metal contact (3);
s7: grinding the lower part of the wafer (1) to thin the wafer to form a thinned wafer;
s8: and carrying out plastic packaging treatment on the lower part of the thinned wafer to form a second plastic packaging layer (42).
5. The wafer-level chip packaging process of claim 4, wherein: the thickness of the thinned wafer is 150-300 mu m.
6. The wafer-level chip packaging process of claim 4, wherein: the thickness of the metal welding pad (2) is 10-50 um.
7. The wafer-level chip packaging process of claim 4, wherein: and the thickness of the thinned metal contact (3) is 40-60 um.
8. The wafer-level chip packaging process of claim 4, wherein: the height of first plastic-sealed layer after the attenuate is 50-110um, the height of second plastic-sealed layer is 40-150 um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010698631.0A CN111816624A (en) | 2020-07-20 | 2020-07-20 | Wafer-level chip packaging structure and packaging process thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010698631.0A CN111816624A (en) | 2020-07-20 | 2020-07-20 | Wafer-level chip packaging structure and packaging process thereof |
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| Publication Number | Publication Date |
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| CN111816624A true CN111816624A (en) | 2020-10-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202010698631.0A Pending CN111816624A (en) | 2020-07-20 | 2020-07-20 | Wafer-level chip packaging structure and packaging process thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024113532A1 (en) * | 2022-11-28 | 2024-06-06 | 北京超材信息科技有限公司 | Manufacturing method for surface acoustic wave device, surface acoustic wave device, and radio frequency module |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103681535A (en) * | 2012-09-01 | 2014-03-26 | 万国半导体股份有限公司 | Wafer level packaging element with thick bottom pedestal and making method thereof |
| CN104124176A (en) * | 2013-04-24 | 2014-10-29 | 万国半导体股份有限公司 | Method for preparation of semiconductor device used in flip installing process |
| CN107068628A (en) * | 2017-03-02 | 2017-08-18 | 上海长园维安微电子有限公司 | A kind of structure and technique for realizing the dough models of TVS chips Ws LCSP six envelope |
| CN110098160A (en) * | 2019-02-26 | 2019-08-06 | 上海朕芯微电子科技有限公司 | A kind of wafer-level packaging chip and preparation method thereof |
-
2020
- 2020-07-20 CN CN202010698631.0A patent/CN111816624A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103681535A (en) * | 2012-09-01 | 2014-03-26 | 万国半导体股份有限公司 | Wafer level packaging element with thick bottom pedestal and making method thereof |
| CN104124176A (en) * | 2013-04-24 | 2014-10-29 | 万国半导体股份有限公司 | Method for preparation of semiconductor device used in flip installing process |
| CN107068628A (en) * | 2017-03-02 | 2017-08-18 | 上海长园维安微电子有限公司 | A kind of structure and technique for realizing the dough models of TVS chips Ws LCSP six envelope |
| CN110098160A (en) * | 2019-02-26 | 2019-08-06 | 上海朕芯微电子科技有限公司 | A kind of wafer-level packaging chip and preparation method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024113532A1 (en) * | 2022-11-28 | 2024-06-06 | 北京超材信息科技有限公司 | Manufacturing method for surface acoustic wave device, surface acoustic wave device, and radio frequency module |
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Application publication date: 20201023 |