CN111554629A

CN111554629A - Chip packaging method

Info

Publication number: CN111554629A
Application number: CN202010367788.5A
Authority: CN
Inventors: 石磊
Original assignee: Nantong Fujitsu Microelectronics Co Ltd
Current assignee: Nantong Fujitsu Microelectronics Co Ltd; Tongfu Microelectronics Co Ltd
Priority date: 2020-04-30
Filing date: 2020-04-30
Publication date: 2020-08-18

Abstract

The application discloses a chip packaging method, which comprises the following steps: providing a first packaging body, wherein the first packaging body comprises at least one connecting chip, a plurality of first conductive columns and a first plastic packaging layer; forming a first rewiring layer on one side of the functional surface connected with the chip; the method comprises the steps that the functional surfaces of a first chip and a second chip which are independent face a first rewiring layer and are electrically connected with the first rewiring layer, wherein signal transmission area bonding pads of the first chip and the second chip are arranged close to each other, and the signal transmission area bonding pads of the first chip and the second chip are electrically connected with a connecting chip through the first rewiring layer; forming an electric connection structure on one side of the non-functional surface of the connection chip, wherein the electric connection structure is electrically connected with the other end of the first conductive column; the electric connection structure faces the packaging substrate and is electrically connected with the packaging substrate. The signal transmission rate between the first chip and the second chip can be improved, and the performance of a packaging device is improved.

Description

Chip packaging method

Technical Field

The present application relates to the field of semiconductor technology, and more particularly, to a chip packaging method.

Background

With the upgrading of electronic products, the requirements for chip packaging technology are increasing, and in the existing chip packaging technology, a chip is usually connected to a silicon interposer first, and then the silicon interposer is connected to a substrate. The electrical performance and the heat conduction performance of the packaged device formed in the mode are excellent, but the cost is high, and the silicon medium plate is high in brittleness, so that the stability of the packaged device is low. Therefore, it is necessary to develop a new packaging technology that can reduce the cost and form a packaged device with excellent performance.

Disclosure of Invention

The technical problem mainly solved by the application is to provide a chip packaging method, which can reduce the cost and improve the signal transmission rate between a first chip and a second chip.

In order to solve the technical problem, the application adopts a technical scheme that: providing a chip packaging method, wherein the chip packaging method comprises the following steps: providing a first packaging body, wherein the first packaging body comprises at least one connecting chip, a plurality of first conductive columns and a first plastic packaging layer; the connecting chips comprise a functional surface and a non-functional surface which are arranged in a back-to-back mode, a plurality of first conductive columns are arranged on the periphery of each connecting chip, and the first plastic packaging layer covers the side surfaces of the connecting chips and the side surfaces of the first conductive columns; forming a first redistribution layer on one side of the functional surface of the connection chip, wherein different areas of the first redistribution layer are electrically connected with the connection chip and the first conductive pillar at corresponding positions through the first plastic package layer; the method comprises the steps that functional surfaces of independent first and second chips face a first redistribution layer and are electrically connected with the first redistribution layer, wherein signal transmission area bonding pads of the first and second chips are arranged close to each other, the signal transmission area bonding pads of the first and second chips are electrically connected with a connecting chip through the first redistribution layer, and non-signal transmission area bonding pads of the first and second chips are electrically connected with one end of a first conductive column through the first redistribution layer; forming an electrical connection structure on one side of the non-functional surface of the connection chip, wherein the electrical connection structure is electrically connected with the other end of the first conductive column; and enabling the electric connection structure to face a packaging substrate, and enabling the electric connection structure to be electrically connected with the packaging substrate.

Wherein the providing the first package comprises: providing a removable carrier plate, wherein the carrier plate is defined with at least one area; forming a plurality of the first conductive pillars at an edge of each of the regions; adhering the connecting chip to the inner side of each region, wherein the thickness of the connecting chip is smaller than the height of the first conductive column, and the non-functional surface of the connecting chip faces the carrier plate; the carrier plate is provided with first lead the formation of electrical pillar one side first plastic envelope layer, first plastic envelope layer with first lead electrical pillar and flush, connect the chip connect the pad on the functional surface follow expose in the first plastic envelope layer.

Wherein before the attaching of the connection chip to the inner side of each of the regions, the method further comprises: and forming a second conductive pillar on the connecting pad of the connecting chip, wherein the sum of the height of the second conductive pillar and the thickness of the connecting chip is less than or equal to the height of the first conductive pillar.

Wherein, be provided with the carrier plate the first conductive pillar one side forms first plastic envelope layer includes: forming the first plastic package layer on one side of the carrier plate, where the first conductive pillars are arranged, and covering the first conductive pillars and the second conductive pillars with the first plastic package layer; grinding the surface of one side, far away from the carrier plate, of the first plastic package layer until the first conductive columns and the second conductive columns are exposed out of the first plastic package layer and are flush with each other; and forming a first passivation layer on one side of the first plastic packaging layer, and forming a first opening at a position of the first passivation layer corresponding to the first conductive pillar and the second conductive pillar.

Wherein before the step of bringing the functional surfaces of the independent first chip and second chip toward the first redistribution layer and electrically connecting to the first redistribution layer, the method further comprises: forming a second passivation layer on one side of the first rewiring layer, and forming a second opening in a position of the second passivation layer corresponding to the first rewiring layer, wherein the position of the second opening corresponds to the signal transmission area bonding pad and the non-signal transmission area bonding pad of the first chip and the second chip one to one; and forming third conductive pillars in the second openings, wherein the third conductive pillars are electrically connected with the first redistribution layer.

Wherein the facing the functional surfaces of the independent first and second chips toward the first redistribution layer and electrically connected with the first redistribution layer comprises: and bonding and connecting the signal transmission region bonding pad and the non-signal transmission region bonding pad on the first chip and the second chip with the third conductive pillar at the corresponding positions respectively.

Wherein before the electrical connection structure is formed on the non-functional surface side of the connection chip, the method further comprises: forming an underfill between the functional surfaces of the first chip and the second passivation layer; forming a second plastic packaging layer on one side of the second passivation layer, wherein the second plastic packaging layer covers the side faces of the first chip and the second chip; and removing the carrier plate.

Wherein, said form the electrical connection structure in said non-functional face one side of connecting the chip, the electrical connection structure with the other end electricity of said first conducting pillar is connected, include: forming a third passivation layer on one side of the first package body, which is far away from the first chip, wherein a third opening is formed in the third passivation layer, corresponding to the other end of the first conductive pillar; and forming a solder ball in the third opening, wherein the electric connection structure comprises the solder ball.

Wherein, said form the electrical connection structure in said non-functional face one side of connecting the chip, the electrical connection structure with the other end electricity of said first conducting pillar is connected, include: forming a fourth passivation layer on one side of the first package body, which is far away from the first chip, wherein a fourth opening is formed in the fourth passivation layer corresponding to the other end of the first conductive pillar; forming a second re-routing layer on the fourth passivation layer, the second re-routing layer being electrically connected to the first conductive pillar; forming a fifth passivation layer on one side of the second rewiring layer, wherein a fifth opening is formed in the fifth passivation layer at a position corresponding to the second rewiring layer; and forming a solder ball in the fifth opening, wherein the electric connection structure comprises the solder ball and the second re-wiring layer.

The first packaging body comprises at least two packaging units, each packaging unit comprises at least one connecting chip and a plurality of first conductive columns located on the periphery of the connecting chip, and the first plastic packaging layer continuously covers all the packaging units; before the electrically connecting structure is directed to a package substrate and electrically connected to the package substrate, the method further includes: and cutting off the area between the adjacent packaging units to obtain the packaging device containing the single packaging unit.

The beneficial effect of this application is: the chip packaging method provided by the application adopts different connection modes for the signal transmission area and the non-signal transmission area of the main chip: for the signal transmission area, the connecting chip is adopted to connect the first chip and the second chip, so that the signal transmission rate between the first chip and the second chip is improved, and the performance of a packaged device is improved; for the non-signal transmission area, the electric connection structure is adopted to be connected with the packaging substrate, so that the packaging cost can be reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:

FIG. 1 is a schematic flow chart diagram illustrating an embodiment of a chip packaging method according to the present application;

FIG. 2 is a schematic structural diagram of an embodiment corresponding to step S101 in FIG. 1;

FIG. 3 is a schematic flowchart of an embodiment corresponding to step S101 in FIG. 1;

FIG. 4a is a schematic structural diagram of an embodiment corresponding to step S201 in FIG. 3;

FIG. 4b is a schematic structural diagram of an embodiment corresponding to step S202 in FIG. 3;

FIG. 4c is a schematic structural diagram of an embodiment corresponding to step S203 in FIG. 3;

FIG. 4d is a schematic structural diagram of an embodiment corresponding to step S204 in FIG. 3;

FIG. 5 is a schematic structural diagram of another embodiment corresponding to step S204 in FIG. 3;

FIG. 6 is a schematic structural diagram of an embodiment corresponding to step S102 in FIG. 1;

FIG. 7 is a schematic structural diagram of an embodiment corresponding to step S103 in FIG. 1;

FIG. 8 is a flowchart illustrating an embodiment of the method before step S104 in FIG. 1;

FIG. 9a is a schematic structural diagram of an embodiment corresponding to step S301 in FIG. 8;

FIG. 9b is a schematic structural diagram of an embodiment corresponding to step S302 in FIG. 8;

FIG. 10a is a schematic structural diagram of an embodiment corresponding to step S104 in FIG. 1;

FIG. 10b is a schematic structural diagram of another embodiment corresponding to step S104 in FIG. 1;

fig. 11 is a schematic structural diagram of an embodiment corresponding to step S105 in fig. 1.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Referring to fig. 1, fig. 1 is a schematic flow chart illustrating an embodiment of a chip packaging method according to the present application, the chip packaging method including:

step S101: a first package body 20 is provided, wherein the first package body 20 includes at least one connection chip 12, a plurality of first conductive pillars 14, and a first molding compound layer 16.

Specifically, referring to fig. 2, fig. 2 is a schematic structural diagram of an embodiment corresponding to step S101 in fig. 1. Fig. 2 is a schematic diagram illustrating a case where the first package 20 includes one connection chip 12, and in some cases, the first package 20 may include a plurality of connection chips 12, and the connection chips 12 may further include conductive traces (not shown). The connecting chip 12 includes a functional surface 120 and a non-functional surface 122 that are disposed opposite to each other, a plurality of first conductive pillars 14 are disposed on the periphery of each connecting chip 12, and the first molding compound layer 16 covers the side surfaces of the connecting chip 12 and the first conductive pillars 14, where the left and right sides of the connecting chip 12 and the first conductive pillars 14 on fig. 2 are not filled with patterns, that is, the first molding compound layer 16.

In one embodiment, please refer to fig. 3, fig. 3 is a flowchart illustrating an embodiment corresponding to step S101 in fig. 1, where the step S101 specifically includes:

step S201: a removable carrier plate 11 is provided, the carrier plate 11 defining at least one area.

Specifically, referring to fig. 4a, fig. 4a is a schematic structural diagram of an embodiment corresponding to step S201 in fig. 3, the carrier 11 in fig. 4a only schematically shows one of the regions, in practical application, the carrier 11 may be a larger region divided into a plurality of small regions, and the package of the first package 20 is started in each of the small regions.

Step S202: a plurality of first conductive pillars 14 are formed at the edge of each region.

Specifically, referring to fig. 4b, fig. 4b is a schematic structural diagram of an embodiment corresponding to step S202 in fig. 3, in order to form the first conductive pillar 14 on the carrier 11, a metal layer (not shown) is first deposited on the carrier 11, a patterned mask layer is then formed on the metal layer, the mask layer is provided with a through hole, the first conductive pillar 14 is then formed in the through hole, and finally the mask layer and the metal layer not covered by the first conductive pillar 14 are removed.

Step S203: the connecting chip 12 is adhered to the inner side of each region, the thickness of the connecting chip 12 is smaller than the height of the first conductive pillar 14, and the non-functional surface 122 of the connecting chip 12 faces the carrier 11.

Specifically, referring to fig. 4c, fig. 4c is a schematic structural view of an embodiment corresponding to step S203 in fig. 3, and the non-functional surface 122 of the connecting chip 12 and the carrier 11 can be adhered by a peelable adhesive such as a double-sided adhesive. The carrier 11 is made of a hard material such as metal or plastic.

In a specific application scenario, the connection chip 12 includes a connection pad (not shown), and before step S203, the method further includes forming a second conductive pillar 15 on the connection pad of the connection chip 12, and controlling a sum of a height of the second conductive pillar 15 and a thickness of the connection chip 12 to be less than or equal to a height of the first conductive pillar 14. The first conductive pillar 14 and the second conductive pillar 15 are made of at least one metal material selected from copper, nickel, gold, and silver. Of course, in other embodiments, the second conductive pillars 15 may be formed on the functional surface 120 of the connection chip 12 after the connection chip 12 and the carrier 11 are attached.

Step S204: a first molding compound layer 16 is formed on the side of the carrier 11 where the first conductive pillars 14 are disposed, the first molding compound layer 16 is flush with the first conductive pillars 14, and the connection pads on the functional surface 120 of the connection chip 12 are exposed from the first molding compound layer 16.

Specifically, referring to fig. 4d, fig. 4d is a schematic structural diagram of an embodiment corresponding to step S204 in fig. 3, in which the first molding compound layer 16 is a blank portion of fig. 4d without using a filling pattern, the first molding compound layer 16 is formed on two sides and above the connection chip 12 and the first conductive pillars 14, the connection chip 12 and the first conductive pillars 14 are covered first, and then the first molding compound layer 16 is polished to be flush with the first conductive pillars 14. When the height of the first conductive pillars 14 is greater than the sum of the thickness of the connection chip 12 and the height of the second conductive pillars 15, after the first molding compound layer 16 is made to be flush with the first conductive pillars 14 by grinding, the first molding compound layer 16 and the first conductive pillars 14 are continuously ground, so that the second conductive pillars 15 are exposed from the first molding compound layer 16, and at this time, the first conductive pillars 14, the second conductive pillars 15, and the first molding compound layer 16 are flush. The first molding compound layer 16 can effectively fix the connecting chip 12 and the first conductive pillars 14, and the material of the first molding compound layer 16 may be epoxy resin or the like.

Further, referring to fig. 5, fig. 5 is a schematic structural diagram of another embodiment corresponding to step S204 in fig. 3, a first passivation layer 17 is further included on a surface of the first molding compound layer 16 on a side away from the carrier 11, and first openings (not shown) are formed on the first passivation layer 17 at positions corresponding to the first conductive pillars 14 and the second conductive pillars 15, where fig. 5 is a schematic cross-sectional view only, regions filled with the same pattern in fig. 5 are all the first passivation layer 17, and a plurality of first openings are formed in the fig. 5 at positions corresponding to the first conductive pillars 14 and the second conductive pillars 15.

Step S102: the first rewiring layer 21 is formed on the functional surface 120 side of the connection chip 12.

Specifically, referring to fig. 6, fig. 6 is a schematic structural diagram of an embodiment corresponding to step S102 in fig. 1, which follows step S204, and illustrates that a patterned first redistribution layer 21 is formed as required in practice, and the first redistribution layer 21 fills the first opening, so that different areas of the first redistribution layer 21 are electrically connected to the connection chip 12 and the first conductive pillar 14 at corresponding positions through the first molding layer 16 and the first passivation layer 17, respectively.

Step S103: the functional surfaces of the independent first chip 22 and second chip 24 face the first redistribution layer 21 and are electrically connected to the first redistribution layer 21.

Specifically, referring to fig. 7, fig. 7 is a schematic structural diagram of an embodiment corresponding to step S103 in fig. 1, wherein the signal transmission area pad 220 of the first chip 22 and the signal transmission area pad 240 of the second chip 24 are disposed close to each other, the signal transmission area pad 220 of the first chip 22 and the signal transmission area pad 240 of the second chip 24 are electrically connected to the connection chip 12 through the first redistribution layer 21, and the non-signal transmission area pad 222 of the first chip 22 and the non-signal transmission area pad 242 of the second chip 24 are electrically connected to one end of the first conductive pillar 14 through the first redistribution layer 21.

Further, before step S103, please refer to fig. 6, after the first redistribution layer 21 is formed, a second passivation layer 26 is formed on one side of the first redistribution layer 21, and second openings (not shown) are formed in positions of the second passivation layer 26 corresponding to the first redistribution layer 21, where the positions of the second openings correspond to the signal transmission area pads (220, 240) and the non-signal transmission area pads (222, 242) of the first chip 22 and the second chip 24 one by one, and further third conductive pillars 28 are formed in the second openings, and the third conductive pillars 28 are electrically connected to the first redistribution layer 21, so as to improve the connection reliability between the third conductive pillars 28 and the first redistribution layer 21.

Specifically, the signal transmission area pad 220 of the first chip 22 and the signal transmission area pad 240 of the second chip 24 correspond to the third conductive pillar 28 on the first redistribution layer 21 electrically connected to the connection chip 12, and are bonded and connected thereto. The non-signal transmission area pad 222 of the first chip 22 and the non-signal transmission area pad 242 of the second chip 24 are connected to the third conductive pillar 28 on the first redistribution layer 21 electrically connected to the first conductive pillar 14 by bonding. The bonding connection is realized by using a method such as thermocompression or soldering for the bonding pads and/or the third conductive pillars 28 on the first chip 22 and the second chip 24, so that the signal transmission region of the first chip 22 and the signal transmission region of the second chip 24 are electrically connected through the connection chip 12, and the speed and stability of high-frequency and high-density signal transmission are improved. In addition, the first chip 22 and the second chip 24 may be pre-formed with conductive pillars corresponding to the signal transmission area pads 240 and the non-signal transmission area pads 242.

In a specific application scenario, the first chip 22 is a CPU chip, the second chip 24 is a GPU chip, and the connection chip 12 is a silicon bridge, so that the signal transmission region between the CPU chip and the GPU chip performs signal transmission through the silicon bridge, thereby improving the signal transmission performance. In addition, the above-mentioned one first chip 22 may be electrically connected with at least one second chip 24 through the connection chip 12. For example, the signal transmission region pads are disposed at four corners of the first chip 22, and the number of the second chips 24 corresponding to one first chip 22 may be four, and the chip types of the four second chips 24 may be the same or different.

Further, before step S104, please refer to fig. 8, fig. 8 is a schematic flowchart of an embodiment corresponding to step S104 in fig. 1, and before step S104, the method further includes:

step S301: an underfill 32 is formed between the functional sides of the first chip 22 and the second chip 24 and the second passivation layer 26.

Specifically, referring to fig. 9a, fig. 9a is a schematic structural diagram of an embodiment corresponding to step S301 in fig. 8, where the underfill 32 fills up the gap between the first chip 22 and the second chip 24 and the second passivation layer 26 and the first redistribution layer 21, so as to further fix the positions of the first chip 22 and the second chip 24, thereby reducing the probability of the first chip 22 and the second chip 24 tilting in the subsequent process, and the underfill 32 can protect the corresponding circuit structures on the first chip 22 and the second chip 24, thereby reducing the probability of the circuit structures short-circuiting.

Step S302: a second molding compound layer 34 is formed on one side of the second passivation layer 26, and the second molding compound layer 34 covers the side surfaces of the first chip 22 and the second chip 24.

Specifically, referring to fig. 9b, fig. 9b is a structural diagram of an embodiment corresponding to the step S302 in fig. 8, in which a second molding compound layer 34 formed on one side of the second passivation layer 26 covers side surfaces of the first chip 22 and the second chip 24 and covers non-functional surfaces of the first chip 22 and the second chip 24, but after the grinding process, the non-functional surfaces of the first chip 22 and the second chip 24 are exposed from the second molding compound layer 34 so as to facilitate heat dissipation of the first chip 22 and the second chip 24, and the first chip 22 and the second chip 24 are further fixed by the second molding compound layer 34 covering the side surfaces of the first chip 22 and the second chip 24.

Step S303: the carrier plate 11 is removed.

Specifically, please refer to fig. 9b, the peelable glue connecting the carrier 11 in fig. 9b is peeled off, so that the carrier 11 can be removed.

Step S104: forming an electrical connection structure on the side of the non-functional surface 122 of the connection chip 12, wherein the electrical connection structure is electrically connected to the other end of the first conductive pillar 14;

in an embodiment, referring to fig. 10a, fig. 10a is a schematic structural view of an embodiment corresponding to step S104 in fig. 1, a third passivation layer 42 is formed on a side of the first package 20 away from the first chip 22, and a third opening (not shown) is disposed on the third passivation layer 42 corresponding to another end position of the first conductive pillar 14. Solder balls 44 are formed in the third openings, and the electrical connection structure includes the solder balls 44.

In another embodiment, please refer to fig. 10b, where fig. 10b is a schematic structural diagram of another embodiment corresponding to step S104 in fig. 1, a fourth passivation layer 52 is formed on a side of the first package 20 away from the first chip 22, and a fourth opening (not shown) is disposed on the fourth passivation layer 52 corresponding to another end position of the first conductive pillar 14; a second re-wiring layer 54 is formed on the fourth passivation layer, the second re-wiring layer 54 being electrically connected to the first conductive pillars 14. A fifth passivation layer 56 is formed on the second rewiring layer 54 side, and a fifth opening (not shown) is provided in the fifth passivation layer 56 at a position corresponding to the second rewiring layer 54. Solder balls 58 are formed in the fifth openings, and the electrical connection structure includes the solder balls 58 and the second re-wiring layer 56.

Further, the drawings in the present application are only schematic, in practical applications, the carrier 11 includes a plurality of areas, the first package 20 is packaged in the plurality of areas of the carrier 11 at the same time, and the first package 20 further includes at least two package units, each package unit includes at least one connection chip 12 and a plurality of first conductive pillars 14 located at the periphery of the connection chip 12, and the first molding compound 16 continuously covers all the package units. It is therefore necessary to cut away the area between adjacent package units to obtain a packaged device containing a single package unit before performing the final packaging step S105.

Step S105: the electrical connection structure is directed toward the package substrate 60 and electrically connected to the package substrate 60.

Specifically, referring to fig. 11, fig. 11 is a schematic structural diagram of an embodiment corresponding to step S105 in fig. 1, in which the package substrate 60 is electrically connected to the electrical connection structure, and the package substrate 60 is further electrically connected to the first conductive pillars 14.

In summary, the chip packaging method provided by the present application adopts different connection methods for the signal transmission region and the non-signal transmission region of the first chip 22 and the second chip 24: for the signal transmission region, the connecting chip 12 is used for connecting the first chip 22 and the second chip 24, so that the signal transmission rate between the first chip 22 and the second chip 24 is improved, and the performance of the packaged device is improved; for the non-signal transmission region, the package substrate 60 is connected by using an electrical connection structure, so that the package cost can be reduced.

The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.

Claims

1. A chip packaging method is characterized by comprising the following steps:

providing a first packaging body, wherein the first packaging body comprises at least one connecting chip, a plurality of first conductive columns and a first plastic packaging layer; the connecting chips comprise a functional surface and a non-functional surface which are arranged in a back-to-back mode, a plurality of first conductive columns are arranged on the periphery of each connecting chip, and the first plastic packaging layer covers the side surfaces of the connecting chips and the side surfaces of the first conductive columns;

forming a first redistribution layer on one side of the functional surface of the connection chip, wherein different areas of the first redistribution layer are electrically connected with the connection chip and the first conductive pillar at corresponding positions through the first plastic package layer;

the method comprises the steps that functional surfaces of independent first and second chips face a first redistribution layer and are electrically connected with the first redistribution layer, wherein signal transmission area bonding pads of the first and second chips are arranged close to each other, the signal transmission area bonding pads of the first and second chips are electrically connected with a connecting chip through the first redistribution layer, and non-signal transmission area bonding pads of the first and second chips are electrically connected with one end of a first conductive column through the first redistribution layer;

forming an electrical connection structure on one side of the non-functional surface of the connection chip, wherein the electrical connection structure is electrically connected with the other end of the first conductive column;

and enabling the electric connection structure to face a packaging substrate, and enabling the electric connection structure to be electrically connected with the packaging substrate.

2. The chip packaging method according to claim 1, wherein the providing the first package body comprises:

providing a removable carrier plate, wherein the carrier plate is defined with at least one area;

forming a plurality of the first conductive pillars at an edge of each of the regions;

adhering the connecting chip to the inner side of each region, wherein the thickness of the connecting chip is smaller than the height of the first conductive column, and the non-functional surface of the connecting chip faces the carrier plate;

the carrier plate is provided with first lead the formation of electrical pillar one side first plastic envelope layer, first plastic envelope layer with first lead electrical pillar and flush, connect the chip connect the pad on the functional surface follow expose in the first plastic envelope layer.

3. The chip packaging method according to claim 2, wherein before the attaching the connection chip to the inner side of each of the regions, the method further comprises:

and forming a second conductive pillar on the connecting pad of the connecting chip, wherein the sum of the height of the second conductive pillar and the thickness of the connecting chip is less than or equal to the height of the first conductive pillar.

4. The chip packaging method according to claim 3, wherein the forming the first molding compound layer on the side of the carrier where the first conductive pillars are disposed comprises:

forming the first plastic package layer on one side of the carrier plate, where the first conductive pillars are arranged, and covering the first conductive pillars and the second conductive pillars with the first plastic package layer;

grinding the surface of one side, far away from the carrier plate, of the first plastic package layer until the first conductive columns and the second conductive columns are exposed out of the first plastic package layer and are flush with each other;

and forming a first passivation layer on one side of the first plastic packaging layer, and forming a first opening at a position of the first passivation layer corresponding to the first conductive pillar and the second conductive pillar.

5. The chip packaging method according to claim 1, wherein before the step of bringing the functional surfaces of the independent first and second chips toward the first redistribution layer and electrically connecting to the first redistribution layer, the method further comprises:

forming a second passivation layer on one side of the first rewiring layer, and forming a second opening in a position of the second passivation layer corresponding to the first rewiring layer, wherein the position of the second opening corresponds to the signal transmission area bonding pad and the non-signal transmission area bonding pad of the first chip and the second chip one to one;

and forming third conductive pillars in the second openings, wherein the third conductive pillars are electrically connected with the first redistribution layer.

6. The chip packaging method according to claim 5, wherein the facing the functional surfaces of the independent first and second chips toward the first redistribution layer and electrically connected to the first redistribution layer comprises:

and bonding and connecting the signal transmission region bonding pad and the non-signal transmission region bonding pad on the first chip and the second chip with the third conductive pillar at the corresponding positions respectively.

7. The chip packaging method according to claim 5, wherein before forming the electrical connection structure on the non-functional surface side of the connection chip, the method further comprises:

forming an underfill between the functional surfaces of the first chip and the second passivation layer;

forming a second plastic packaging layer on one side of the second passivation layer, wherein the second plastic packaging layer covers the side faces of the first chip and the second chip;

and removing the carrier plate.

8. The chip packaging method according to claim 1, wherein the forming an electrical connection structure on the non-functional surface side of the connection chip, the electrical connection structure being electrically connected to the other end of the first conductive pillar, includes:

forming a third passivation layer on one side of the first package body, which is far away from the first chip, wherein a third opening is formed in the third passivation layer, corresponding to the other end of the first conductive pillar;

and forming a solder ball in the third opening, wherein the electric connection structure comprises the solder ball.

9. The chip packaging method according to claim 1, wherein the forming an electrical connection structure on the non-functional surface side of the connection chip, the electrical connection structure being electrically connected to the other end of the first conductive pillar, includes:

forming a fourth passivation layer on one side of the first package body, which is far away from the first chip, wherein a fourth opening is formed in the fourth passivation layer corresponding to the other end of the first conductive pillar; forming a second re-routing layer on the fourth passivation layer, the second re-routing layer being electrically connected to the first conductive pillar;

forming a fifth passivation layer on one side of the second rewiring layer, wherein a fifth opening is formed in the fifth passivation layer at a position corresponding to the second rewiring layer;

and forming a solder ball in the fifth opening, wherein the electric connection structure comprises the solder ball and the second re-wiring layer.

10. The chip packaging method according to claim 1,

the first packaging body comprises at least two packaging units, each packaging unit comprises at least one connecting chip and a plurality of first conductive columns positioned on the periphery of the connecting chip, and the first plastic packaging layer continuously covers all the packaging units;

before the electrically connecting structure is directed to a package substrate and electrically connected to the package substrate, the method further includes: and cutting off the area between the adjacent packaging units to obtain the packaging device containing the single packaging unit.