CN111799179A - Method for forming semiconductor device - Google Patents
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- CN111799179A CN111799179A CN202010760341.4A CN202010760341A CN111799179A CN 111799179 A CN111799179 A CN 111799179A CN 202010760341 A CN202010760341 A CN 202010760341A CN 111799179 A CN111799179 A CN 111799179A
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 238000005530 etching Methods 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 238000009966 trimming Methods 0.000 claims abstract description 16
- 238000004381 surface treatment Methods 0.000 claims abstract description 13
- 239000010410 layer Substances 0.000 claims description 167
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 238000004380 ashing Methods 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 239000002344 surface layer Substances 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 31
- 239000007789 gas Substances 0.000 description 6
- 238000002161 passivation Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000002679 ablation Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 125000004430 oxygen atom Chemical group O* 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000004215 Carbon black (E152) Substances 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- -1 fluorine ions Chemical class 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 229930195733 hydrocarbon Natural products 0.000 description 1
- 150000002430 hydrocarbons Chemical class 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention provides a method for forming a semiconductor device, which comprises the following steps: providing a front-end device, wherein the front-end device comprises a dielectric layer, a metal layer embedded in the dielectric layer and a first substrate covering the dielectric layer; forming a mask layer over the first substrate; trimming the edge of the periphery of the mask layer; taking the trimmed mask layer as a mask, and etching to remove the first substrate below the opening; processing the surface of the trimmed mask layer to remove floating charges on the surface of the trimmed mask layer; and further etching the dielectric layer below the opening by taking the trimmed mask layer after surface treatment as a mask. Trimming the edge of the periphery of the mask layer; and processing the surface of the mask layer to remove floating charges on the surface of the mask layer, so that the problem that the edge of the wafer is ablated due to the point discharge of the edge of the mask layer is avoided, the problem that the mask layer is ablated in the deep hole etching process of the wafer dielectric layer is solved, and the quality and the yield of the wafer are improved.
Description
Technical Field
The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a forming method of a semiconductor device.
Background
With the trend of highly integrated semiconductor development, the integration of chips with different functions is the main development direction of semiconductor packaging technology, and wafer level stacking based on 3D-IC technology can achieve the goals of lower cost, faster speed and higher density. After wafer bonding, deep holes are formed in the bonded wafer, and metal layers are filled in the deep holes to realize interconnection between different wafers.
With the increasing number of bonded wafers, the plasma dry etching technology corresponding to the bonded wafers faces a bottleneck, a thick dielectric layer needs to be etched through by plasma to form deep holes, and the etching time becomes very long without changing the dielectric layer material and the mask layer material too much, so that negative effects can be brought, for example, in the process of etching the dielectric layer for a long time, the mask layer (for example, photoresist) which shields the dielectric layer has point discharge, and the phenomenon that the mask layer (for example, photoresist) is ablated (as shown in a position A in fig. 1) is very easy to occur at the edge of the wafer, so that the whole wafer is scrapped.
Disclosure of Invention
The invention aims to provide a method for forming a semiconductor device, which avoids the situation that the edge point discharge of a mask layer is ablated to further damage a wafer.
The invention provides a method for forming a semiconductor device, which comprises the following steps:
providing a front-end device, wherein the front-end device comprises a dielectric layer, a metal layer embedded in the dielectric layer and a first substrate covering the dielectric layer;
forming a mask layer over the first substrate, the mask layer having an opening over the metal layer;
trimming the edge of the periphery of the mask layer;
taking the trimmed mask layer as a mask, and etching to remove the first substrate below the opening;
processing the surface of the trimmed mask layer to remove floating charges on the surface of the trimmed mask layer;
and further etching the dielectric layer below the opening by taking the trimmed mask layer after surface treatment as a mask.
Further, after the first substrate below the opening is removed by etching, the surface of the trimmed mask layer is processed for more than two hours.
Further, the material of the mask layer includes: and (7) photoresist.
Further, the surface treatment of the trimmed mask layer includes: by ashing, introducingO2And SF6The trimmed mask layer with partial thickness is removed through reaction of the mixed gas, so that floating charges on the surface layer of the trimmed mask layer are removed.
Further, the ashing process parameters include: the pressure of the chamber is 40 mT-60 mT, the power of the upper electrode is 1000W-1200W, the power of the lower electrode is 30W-50W, O2The flow rate is 180 sccm-200 sccm, SF6The flow rate is 15sccm to 35sccm, and the time is 100s to 220 s.
Furthermore, the width of trimming the peripheral edge of the mask layer is more than or equal to 1 mm.
Further, a plasma dry etching process is adopted for etching the dielectric layer below the opening, and the process parameters comprise: the pressure of the chamber is 10 mTorr-14 mTorr, CF4The flow rate of (1) is 40-60 sccm, CHF3The flow rate of the RF power source is 60-80 sccm, the RF power source provides 450-550W of power and 170-190V of bias voltage, and the duration is 60-80 s.
Further, the dielectric layer comprises a first oxide layer, a silicon nitride layer and a second oxide layer which are stacked.
Further, the thickness of the mask layer after the surface treatment and the trimming is more than or equal to 5 μm.
Further, the front-end device further includes: a second substrate; the dielectric layer is formed on a second substrate, the wafer where the second substrate is located is a carrier wafer or a device wafer, and the wafer where the first substrate is located is a device wafer.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a method for forming a semiconductor device, which comprises the following steps: providing a front-end device, wherein the front-end device comprises a dielectric layer, a metal layer embedded in the dielectric layer and a first substrate covering the dielectric layer; forming a mask layer over the first substrate; trimming the edge of the periphery of the mask layer; taking the trimmed mask layer as a mask, and etching to remove the first substrate below the opening; processing the surface of the trimmed mask layer to remove floating charges on the surface of the trimmed mask layer; and further etching the dielectric layer below the opening by taking the trimmed mask layer after surface treatment as a mask. Trimming the edge of the periphery of the mask layer; and processing the surface of the trimmed mask layer to remove floating charges on the surface of the trimmed mask layer, so that the edge tip of the mask layer is prevented from being ablated to further damage the wafer, the problem of mask layer ablation at the edge of the wafer is solved in the deep hole etching process of the wafer dielectric layer, and the quality and the yield of the wafer are improved.
Drawings
FIG. 1 is a schematic diagram of photoresist ablation occurring at the edge of a semiconductor device wafer.
Fig. 2 is a flow chart illustrating a method for forming a semiconductor device according to an embodiment of the invention.
Fig. 3 to 7 are schematic views of steps of a method for forming a semiconductor device according to an embodiment of the present invention.
Wherein the reference numbers are as follows:
11-a second substrate; 12-an insulating layer; 13-a metal layer; 14-a dielectric layer; 14 a-a first oxide layer; 14 b-a silicon nitride layer; 14 c-a second oxide layer; 15-a first substrate; 16-a passivation layer; 17-mask layer.
Detailed Description
The embodiment of the invention provides a method for forming a semiconductor device. The invention is described in further detail below with reference to the figures and specific examples. The advantages and features of the present invention will become more apparent from the following description. It is to be noted, however, that the drawings are designed in a simplified form and are not to scale, but rather are to be construed in an illustrative and descriptive sense only and not for purposes of limitation.
An embodiment of the present invention provides a method for forming a semiconductor device, as shown in fig. 2, including:
providing a front-end device, wherein the front-end device comprises a dielectric layer, a metal layer embedded in the dielectric layer and a first substrate covering the dielectric layer;
forming a mask layer over the substrate, the mask layer having an opening over the metal layer;
trimming the edge of the periphery of the mask layer;
taking the trimmed mask layer as a mask, and etching to remove the first substrate below the opening;
processing the surface of the trimmed mask layer to remove floating charges on the surface of the trimmed mask layer;
and further etching the dielectric layer below the opening by taking the trimmed mask layer after surface treatment as a mask.
The steps of the method for forming a semiconductor device according to the embodiment of the present invention will be described in detail with reference to fig. 3 to 7.
As shown in fig. 3, a front-end device is provided, which includes a dielectric layer 14, a metal layer 13 embedded in the dielectric layer 14, and a first substrate 15 covering the dielectric layer 14. Illustratively, the front-end device further comprises: a second substrate 11; the dielectric layer 14 is located on the second substrate 11, the insulating layer 12 is formed on the second substrate 11, the metal layer 13 is formed on the insulating layer 12, and the metal layer 13 is embedded in the dielectric layer 14. The front-end device may be a plurality of stacked and bonded wafers, the wafer on which the second substrate 11 is located may be a carrier wafer or a device wafer, and the wafer on which the first substrate 15 is located may be a device wafer, for example. The components formed in the first substrate 15 and the second substrate 11 may be the same or different, and are configured according to actual requirements. In some embodiments, the substrate may be a semiconductor substrate, made of any semiconductor material suitable for semiconductor devices (such as Si, SiC, SiGe, etc.). In other embodiments, the substrate may be a composite substrate such as a silicon-on-insulator (SOI) substrate or a silicon germanium-on-insulator (sige-on-insulator substrate). It will be understood by those skilled in the art that the substrate is not subject to any limitations, but may be selected according to the actual application. Various device (not limited to semiconductor device) components (not shown) may be formed in the substrate. The substrate may also have been formed with other layers or members, such as: gate structures, contact holes, dielectric layers, metal lines and vias, and the like.
A mask layer 17 is formed over the first substrate 15, specifically, a passivation layer 16 may be formed over the first substrate 15, and the mask layer 17 is formed over the passivation layer 16. The mask layer 17 has an opening B located above the metal layer 13; the mask layer is made of, for example, a photoresist, and has a thickness of, for example, 10 to 20 μm.
As shown in fig. 4, the peripheral edge of the mask layer 17 is trimmed to a trim width W of 1mm or more. Specifically, a trimming machine can be used for trimming, the mask layer 17 with the whole thickness of the periphery is removed, and the passivation layer 16 at the periphery is exposed. And removing the edge of the mask layer 17 by a certain width to prevent the edge point discharge of the mask layer 17 from being ablated to further damage the wafer.
As shown in fig. 5, the trimmed mask layer 17 is used as a mask, and the first substrate 15 under the opening is etched and removed. Further, after the first substrate below the opening is removed by etching, the surface of the trimmed mask layer is processed for more than two hours to ensure that the surface of the trimmed mask layer 17 is free charge released.
As shown in fig. 6, the trimmed surface of the mask layer is processed to remove the floating charges on the trimmed surface of the mask layer. In particular, with O2Ashing processes to remove portions of the thickness (e.g.
) The trimmed mask layer 17 (e.g., photoresist) is removed to completely remove floating charges on the surface of the trimmed mask layer 17.
By the use of O2Ashing, using high reactive oxygen atoms in oxygen plasma to react with hydrocarbon oxygen high molecular compound in photoresist to generate CO and CO2、H2O、N2And the volatile substances are waited, and finally the purpose of removing the photoresist is achieved. Introducing O with a certain flow ratio2And SF6Of mixed gas of (1), wherein SF6The flow accounts for 8-20% of the total gas flow, can effectively improve the concentration of oxygen atoms in plasma and the generation amount of activated photoresist, and increase lightAnd the photoresist ashing rate is used for thoroughly removing the floating charges on the surface layer of the mask layer 17. Wherein the pressure of the chamber is 40 mT-60 mT, the power of the upper electrode is 1000W-1200W, the power of the lower electrode is 30W-50W, and O is2The flow rate is 180 sccm-200 sccm, SF6The flow rate is 15sccm to 35sccm, and the time is 100s to 220 s.
As shown in fig. 7, the dielectric layer 14 under the opening is etched by using the trimmed mask layer 17 after surface treatment as a mask. The dielectric layer 14 may include a first oxide layer 14a, a silicon nitride layer 14b, and a second oxide layer 14 c. The silicon nitride layer 14b may serve as an etch stop layer. The first Oxide layer 14a and the second Oxide layer 14c may be Low dielectric constant (Low-K) material layers, such as similar oxides (oxides) containing silicon, oxygen, carbon, hydrogen elements, or silicon glass doped with fluorine ions, which may also be referred to as fluorinated glass (FSG). The first oxide layer 14a has good compactness and good surface coverage, and is used for improving the adhesive force between the silicon nitride layer 14b and the second substrate 11, relieving the stress of the silicon nitride layer 14b and preventing the chip on the wafer from being broken possibly caused by overlarge stress of the silicon nitride layer 14 b.
The thickness of the mask layer 17 after the surface treatment and the trimming, that is, the remaining mask layer 17 is 5 μm or more. And etching the dielectric layer by using CF-based gas until the metal layer 13 is exposed. And etching to form a deep hole C, and depositing metal in the deep hole C, wherein the deposited metal is a metal interconnection line, and copper is generally selected as a metal interconnection line material.
In one embodiment, a plasma dry etch process is used, the pressure in the plasma chamber is set to 10mTorr to 14mTorr, and the etch gas comprises a fluorocarbon-containing gas, such as: CF (compact flash)4The flow rate of (1) is 40-60 sccm, CHF3The flow rate of the RF power source is 60-80 sccm, the RF power source provides 450-550W of power and 170-190V of bias voltage, and the duration is 60-80 s.
In summary, the present invention provides a method for forming a semiconductor device, including: providing a front-end device, wherein the front-end device comprises a dielectric layer, a metal layer embedded in the dielectric layer and a first substrate covering the dielectric layer; forming a mask layer over the first substrate; trimming the edge of the periphery of the mask layer; taking the trimmed mask layer as a mask, and etching to remove the first substrate below the opening; processing the surface of the trimmed mask layer to remove floating charges on the surface of the trimmed mask layer; and etching the dielectric layer below the opening by taking the trimmed mask layer subjected to surface treatment as a mask. Trimming the edge of the periphery of the mask layer; and processing the surface of the trimmed mask layer to remove floating charges on the surface of the trimmed mask layer, so that the edge tip of the mask layer is prevented from being ablated to further damage the wafer, the problem of mask layer ablation at the edge of the wafer is solved in the deep hole etching process of the wafer dielectric layer, and the quality and the yield of the wafer are improved.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the method disclosed by the embodiment, the description is relatively simple because the method corresponds to the device disclosed by the embodiment, and the relevant points can be referred to the description of the method part.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A method of forming a semiconductor device, comprising:
providing a front-end device, wherein the front-end device comprises a dielectric layer, a metal layer embedded in the dielectric layer and a first substrate covering the dielectric layer;
forming a mask layer over the first substrate, the mask layer having an opening over the metal layer;
trimming the edge of the periphery of the mask layer;
taking the trimmed mask layer as a mask, and etching to remove the first substrate below the opening;
processing the surface of the trimmed mask layer to remove floating charges on the surface of the trimmed mask layer;
and further etching the dielectric layer below the opening by taking the trimmed mask layer after surface treatment as a mask.
2. The method for forming a semiconductor device according to claim 1, wherein after the first substrate under the opening is removed by etching, the trimmed mask layer is subjected to surface treatment for more than two hours.
3. The method for forming a semiconductor device according to claim 1, wherein the mask layer is made of a material including: and (7) photoresist.
4. The method for forming a semiconductor device according to claim 3, wherein the surface treatment of the trimmed mask layer includes: adopting an ashing process and introducing O2And SF6The trimmed mask layer with partial thickness is removed through reaction of the mixed gas, so that floating charges on the surface layer of the trimmed mask layer are removed.
5. The method of forming a semiconductor device according to claim 4, wherein using ashing process parameters comprises: the pressure of the chamber is 40 mT-60 mT, the power of the upper electrode is 1000W-1200W, the power of the lower electrode is 30W-50W, O2The flow rate is 180 sccm-200 sccm, SF6The flow rate is 15sccm to 35sccm, and the time is 100s to 220 s.
6. The method for forming a semiconductor device according to any one of claims 1 to 5, wherein a width of the trimming of the peripheral edge of the mask layer is 1mm or more.
7. The method for forming a semiconductor device according to any one of claims 1 to 5, wherein a plasma dry etching tool is used for etching the dielectric layer below the openingThe technological process includes the following steps: the pressure of the chamber is 10 mTorr-14 mTorr, CF4The flow rate of (1) is 40-60 sccm, CHF3The flow rate of the RF power source is 60-80 sccm, the RF power source provides 450-550W of power and 170-190V of bias voltage, and the duration is 60-80 s.
8. The method for forming a semiconductor device according to any one of claims 1 to 5, wherein the dielectric layer includes a first oxide layer, a silicon nitride layer, and a second oxide layer which are stacked.
9. The method for forming a semiconductor device according to any one of claims 1 to 5, wherein a thickness of the mask layer after the trimming after the surface treatment is 5 μm or more.
10. The method for forming a semiconductor device according to any one of claims 1 to 5, wherein the front-end device further includes: a second substrate; the dielectric layer is formed on the second substrate, the wafer where the second substrate is located is a carrier wafer or a device wafer, and the wafer where the first substrate is located is a device wafer.
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| CN202010760341.4A CN111799179B (en) | 2020-07-31 | 2020-07-31 | Method for forming semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117577520A (en) * | 2024-01-17 | 2024-02-20 | 粤芯半导体技术股份有限公司 | Image sensor and method of forming same |
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2020
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| US5885756A (en) * | 1995-09-13 | 1999-03-23 | Samsung Electronics Co., Ltd. | Methods of patterning a semiconductor wafer having an active region and a peripheral region, and patterned wafers formed thereby |
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| CN117577520A (en) * | 2024-01-17 | 2024-02-20 | 粤芯半导体技术股份有限公司 | Image sensor and method of forming same |
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