JP2002334879A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

(57) Abstract: In a step of forming a buried interconnect, an insulating film in a bevel region of a wafer is prevented from being etched. A protective film is formed in a bevel region of a wafer, and covers a surface of an insulating film in the bevel region. Subsequently, a photoresist film 18 is formed on the insulating film 16, and then the photoresist film 18 is patterned. At this time, a part of the photoresist film 18 is
Is formed so as to overlap the protective film 17 in the bevel region. Thereafter, the insulating film 16 and the etch stopper film 15 are etched using the photoresist film 18 as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to a method for manufacturing a semiconductor integrated circuit device, in which a conductive film containing copper as a main component is deposited in a wiring groove formed in an insulating film. The present invention relates to a technique which is effective when applied to a method for manufacturing a semiconductor integrated circuit device in which a wiring is formed by removing a conductive film.

[0002]

2. Description of the Related Art In order to reduce the resistance of wiring constituting a semiconductor integrated circuit device, a copper-based material (Cu (copper) or copper alloy) has been applied to a wiring material.

The present inventors are studying a damascene method for forming a wiring using a copper-based material. In this damascene method, after forming a groove for forming a wiring in an insulating film, a conductor film for forming a wiring is deposited on the insulating film and in the groove for forming the wiring, and further, unnecessary portions of the conductive film are formed. Chemical Mechanical Polishing (CMP)
This is a method in which a buried wiring is formed in a groove for forming a wiring by removing the conductive film only in the above-described groove by removing it by a shing method or the like. According to this method, the size of the wiring can be made smaller than the size of the wiring having the normal structure, and in particular, the processing size of a copper-based material that is difficult to perform fine processing by the etching method can be reduced.

[0004]

By the way, the present inventors have found that the following problems occur in the wiring forming process using the above damascene method.

That is, a photoresist film serving as a mask is formed before the above-described dry etching step, but this photoresist film is formed so as to extend from the edge of the wafer to the back surface. Further, the photoresist film formed on the outer peripheral portion of the wafer tends to remain even after the dry etching process. Therefore, there is a possibility that the photoresist film on the outer peripheral portion of the wafer adheres to the stage on which the wafer is mounted in the dry etching apparatus and becomes a foreign matter source. For example, the yield of a semiconductor integrated circuit device having a logic circuit such as a microprocessor is greatly affected by foreign matter adhering to a wafer used for manufacturing the same. Therefore, it is desired to suppress the generation of foreign matter during manufacturing.

In order to solve this problem, the photoresist film formed on the outer peripheral portion of the wafer is removed before the dry etching step. For this reason, in the above-described dry etching step, if the dry etching apparatus is not provided with a clamp mechanism for protecting the outer peripheral portion of the wafer from etching, the insulating film is also etched in the outer peripheral portion and the bevel region of the wafer. .

Here, when the dry etching apparatus is of a single wafer type, the thickness of the insulating film formed on the outer peripheral portion and the bevel region of the wafer is not controlled, and the film thickness becomes a product. Generally, a semiconductor chip (hereinafter, abbreviated as a chip) is generally formed so as to be much thinner than a film thickness of a region where the semiconductor chip is obtained (hereinafter referred to as a chip obtaining region). That is, in the outer peripheral portion and the bevel region of the wafer, the photoresist film is also removed although the insulating film is formed only thinly.
The thin insulating film is always exposed to a dry etching atmosphere. Therefore, in the outer peripheral portion and the bevel region of the wafer, the insulating film is entirely etched. As a result, a wiring formed below the insulating film may be exposed, or etching may reach a lower insulating film. As a result, the outer peripheral portion and the surface of the bevel region of the wafer become a rough surface etched unevenly, and there is a problem that a foreign material is generated. In particular, when a metal film forming a lower wiring or the like is exposed, the metal film is likely to be peeled off and become a foreign substance.

Further, when wirings are formed in multiple layers on a wafer, all the insulating films in the outer peripheral portion and the bevel region of the wafer are finally dry-etched, so that the rough surface of the wafer is exposed. I will. When wiring is formed on the rough surface of this wafer by the damascene method, C
Cu for barrier conductor film and seed film for preventing diffusion of u
A film is sequentially deposited by a sputtering method or the like, and a Cu film is further deposited thereon by a plating method or the like. However, the barrier conductor film formed on the rough surface of the wafer cannot completely cover the rough surface or is not formed with a film thickness sufficient for the barrier function. Therefore, there is a problem that the diffusion preventing property for the Cu film formed on the barrier conductor film is reduced, and Cu is diffused into the wafer. It is known that the diffusion rate of Cu in Si is extremely high, and Cu invading from the outer periphery of the wafer
May diffuse to the chip acquisition area and affect device characteristics.

Therefore, the present inventors investigated known examples from the viewpoint of preventing intrusion of Cu into the wafer.

[0010] For example, Japanese Patent Application Laid-Open No. 2000-260776 discloses that at least one of the regions where the intrusion of Cu, such as the outer peripheral region, bevel region, and back surface region, of a wafer is likely to trap Cu or mobile ions. A technique for providing a function of preventing diffusion is disclosed.

[0011] For example, see Japanese Patent Application Laid-Open No. 2000-9117.
No. 5 discloses a technique for forming a protective insulating film for preventing intrusion and diffusion of Cu in a region where Cu is likely to enter, such as a bevel region and a back surface region of a wafer.

An object of the present invention is to provide a technique for preventing generation of foreign matter from the outer peripheral portion of a wafer during a manufacturing process of a semiconductor integrated circuit device.

Another object of the present invention is to provide a technique for preventing the diffusion of Cu from the outer peripheral portion of a wafer.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0015]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the present invention provides a step of forming a masking layer on an insulating film on a semiconductor wafer, a step of forming a protective film having a predetermined thickness in a first region on an outer peripheral portion of the semiconductor wafer, Forming the masking layer and the protective film, and then etching the insulating film using the masking layer as a mask to form at least one of a connection hole and a wiring groove.

The present invention also provides a step of forming a masking layer on an insulating film on a semiconductor wafer, a step of forming a protective film having a predetermined thickness in a first region on an outer peripheral portion of the semiconductor wafer, After forming the masking layer and the protective film, etching the insulating film using the masking layer as a mask, forming at least one of a connection hole and a wiring groove; and, after etching the insulating film, the masking layer and Removing the protective film, forming a first conductive film on the surface of the insulating film including the inside of the connection hole and the wiring groove, and forming the first hole on the surface of the first conductive film. Forming a second conductive film for filling the wiring groove, removing the first conductive film and the second conductive film outside the connection hole and the wiring groove, and forming a plug and a wiring; It is intended to include a step of forming at least one.

The present invention also provides a step of forming a masking layer on an insulating film on a semiconductor wafer, and a method of protecting a predetermined thickness of an organic material as a main component in a first region on an outer peripheral portion of the semiconductor wafer. Forming a film and, after forming the masking layer and the protective film, etching the insulating film using the masking layer as a mask to form at least one of a connection hole and a wiring groove.

Further, the present invention provides a step of forming a masking layer on an insulating film on a semiconductor wafer, and protecting a predetermined thickness of an organic material as a main component in a first region on an outer peripheral portion of the semiconductor wafer. Forming a film, and after forming the masking layer and the protective film, etching the insulating film using the masking layer as a mask to form at least one of a connection hole and a wiring groove; and Removing the masking layer and the protective film after the etching, forming a first conductive film on the surface of the insulating film including the inside of the connection hole and the wiring groove; Forming a second conductive film for burying the connection hole and the wiring groove on the surface of the film; and forming the first conductive film and the second conductive film outside the connection hole and the wiring groove. Removed by It is intended to include a step of forming at least one of the plug and wire.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing the present invention in detail,
The meaning of the terms in the present application is as follows.

The wafer refers to a single-crystal silicon substrate (generally a substantially circular plane), a sapphire substrate, a glass substrate, other insulating, anti-insulating or semiconductor substrates, etc., used for manufacturing an integrated circuit, and a composite substrate thereof. In the present application, the term “semiconductor integrated circuit device” refers not only to a semiconductor integrated circuit device formed on a semiconductor such as a silicon wafer or a sapphire substrate or an insulator substrate, but also to a TFT (Thin) unless it is explicitly stated otherwise. -Film-Transistor) and S
It also includes those made on an insulating substrate such as glass such as TN (Super-Twisted-Nematic) liquid crystal.

The element formation surface is the main surface of the wafer,
A surface on which device patterns corresponding to a plurality of chip regions are formed by photolithography.

The bevel region of the wafer refers to a region at an outer peripheral portion of the wafer that is angled with respect to the flat surface of the main surface and the back surface of the wafer.

The transfer pattern is a pattern transferred onto a wafer by a mask, and specifically refers to a resist pattern and a pattern on the wafer actually formed using the resist pattern as a mask.

The resist pattern is a film pattern obtained by patterning a photosensitive resin film (resist film) by a photolithography technique. Note that this pattern includes a simple resist film having no opening in the corresponding portion.

The single-wafer processing refers to a method of processing various wafers one by one when performing various processing on the wafers.
Since the processing conditions can be controlled for each wafer, the processing accuracy and reproducibility are excellent, and it is advantageous for miniaturization of the apparatus itself.

In general, the chemical mechanical polishing is performed in such a manner that a surface to be polished is brought into contact with a polishing pad made of a relatively soft cloth-like sheet material or the like, and is relatively moved in the surface direction while supplying a slurry to perform polishing. In addition, in the present application, in addition to this, a CML (Chemical Mechanical) in which polishing is performed by moving a surface to be polished relatively to a hard grindstone surface.
Lapping), abrasives using other fixed abrasives, and abrasive-free CMP using no abrasives.

In the following embodiments, for the sake of convenience, the description will be made by dividing into a plurality of sections or embodiments when necessary, but unless otherwise specified, they are not irrelevant to each other. Is related to some or all of the other modifications, details, supplementary explanations, and the like.

In the following embodiments, when referring to the number of elements (including the number, numerical value, amount, range, etc.), the number is particularly limited to a specific number and is clearly limited to a specific number in principle. Except in cases, the number is not limited to the specific number, and may be more than or less than the specific number.

Further, in the following embodiments, the constituent elements (including element steps, etc.) are not necessarily essential, unless otherwise specified, and when it is deemed essential in principle. Needless to say, there is nothing.

Similarly, in the following embodiments, when referring to the shapes, positional relationships, and the like of the constituent elements, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, etc. And those similar or similar to the shape or the like. This is the same for the above numerical values and ranges.

Also, in the present embodiment, a MISFET (Metal Insulato
r Semiconductor Field Effect Transistor)
, The p-channel MISFET is abbreviated as pMIS, and the n-channel MISFET is abbreviated as nMIS.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) In Embodiment 1, the present invention is applied to a method of manufacturing a semiconductor integrated circuit device in which, for example, nMISQn is formed in a p-type well of a semiconductor substrate.

First, as shown in FIG. 1, a wafer (semiconductor wafer) 1 made of, for example, single crystal silicon having a specific resistance of about 10 Ωcm is heat-treated at about 850 ° C., and a thin silicon oxide film having a thickness of about 10 nm is formed on its surface. Form a film.
This silicon oxide film is formed for the purpose of relieving stress applied to the substrate when densifying (burning) the silicon oxide film embedded in the element isolation trench in a later step. Next, on the silicon oxide film,
For example, a silicon nitride film having a thickness of about 120 nm is formed by CVD.
(Chemical Vapor Deposition) method. Since the silicon nitride film has the property of being hardly oxidized, it is used as a mask for preventing the oxidation of the surface of the wafer 1 below (the active region).

Next, the silicon nitride film and the silicon oxide film in the element isolation region are removed by dry etching using a photoresist film patterned by a photolithography technique as a mask. Subsequently, a groove 2 having a depth of about 350 nm is formed in the wafer 1 in the element isolation region by dry etching using the remaining silicon nitride film as a mask.

Subsequently, in order to remove a damaged layer formed on the inner wall of the groove 2 by etching, the wafer 1 is heat-treated at about 1000 ° C. to form a thin silicon oxide film 3 with a film thickness of about 10 nm on the inner wall of the groove 2. I do. Subsequently, a silicon oxide film 4 having a thickness of about 380 nm is deposited on the wafer 1 by the CVD method, and then, in order to improve the film quality of the silicon oxide film 4,
The wafer 1 is heat-treated to densify (bake) the silicon oxide film 4.

Next, the silicon oxide film 4 is polished by a CMP method using the silicon nitride film as a stopper and is left inside the groove 2 to form an element isolation groove having a flattened surface. Subsequently, the silicon nitride film and the silicon oxide film remaining on the active region of the wafer 1 are removed by wet etching using hot phosphoric acid.

Next, a heat treatment is performed on the wafer 1 to form a thin silicon oxide film (not shown) on the main surface of the wafer 1 which becomes a pad oxide film at the time of ion implantation. Subsequently, a p-type impurity, for example, B (boron) is ion-implanted into a region of the wafer 1 where an nMIS is to be formed, thereby forming a p-type well 5. After the formation of the p-type well 5, the silicon oxide film used in the ion implantation step is removed using a HF (hydrofluoric acid) -based cleaning solution.

Next, as shown in FIG. 2, the wafer 1 is wet-oxidized to form a clean gate oxide film 6 having a thickness of about 3.5 nm on the surface of the p-type well 5. Then, wafer 1
Non-doped polycrystalline Si having a thickness of about 90 to 100 nm
A film is deposited by a CVD method. Note that this polycrystalline Si film is
For example, after depositing amorphous (amorphous) Si by a CVD method, the amorphous Si may be subjected to a heat treatment to change the amorphous Si into polycrystalline Si.

Subsequently, using a mask for ion implantation,
For example, P (phosphorus) is ion-implanted into the non-doped polycrystalline Si film above the p-type well 5 to form an n-type polycrystalline Si film. Further, a silicon oxide film is deposited on the surface of the n-type polycrystalline Si film to form a laminated film, and the laminated film is etched using a photoresist film patterned by photolithography as a mask, thereby forming a gate electrode 7 and a cap insulating film. A film 8 is formed. Incidentally, WSi _x over the gate electrode 7, MoSi _x, TiSi _x, may be stacked refractory metal silicide film such as TaSi _x or CoSi _x. The cap insulating film 8 can be formed by, for example, a CVD method.

Subsequently, after removing the photoresist film used for processing the gate electrode 7, an n-type impurity, for example, P is ion-implanted into the p-type well 5 and n-type impurities are implanted into the p-type well 7 on both sides of the gate electrode 7. ^The- type semiconductor region 9 is formed.

Subsequently, a silicon oxide film having a thickness of about 100 nm is deposited on the wafer 1 by the CVD method. Thereafter, the silicon oxide film is anisotropically etched using a reactive ion etching (RIE) method to form a sidewall spacer 10 on the side wall of the gate electrode 7 of the nMIS. Subsequently, an n-type impurity, for example, As (arsenic) is ion-implanted into the p-type well 5 to form the n ⁺ -type semiconductor region 11 (source and drain) of nMIS. Thus, source and drain regions having an LDD (Lightly Doped Drain) structure are formed in nMISQn, and nMISQn is completed.

Next, as shown in FIGS. 3 and 4, a silicon oxide film 12 is deposited on the wafer 1 by the CVD method. FIG. 4 shows a region including the element formation surface (main surface), the back surface, and the bevel region of the wafer 1, and the thin film remaining on the wafer 1 after each of the above-described steps for easy understanding of the configuration. Are collectively shown as a thin film T. Thereafter, the surface is flattened by polishing the silicon oxide film 12 by, for example, a CMP method.

Next, as shown in FIG. 5, a connection hole 13 is formed in the silicon oxide film 12 on the n ⁺ type semiconductor region 11 on the main surface of the wafer 1 by using a photolithography technique.
Subsequently, a barrier conductor film 14A of, for example, titanium nitride is formed on the wafer 1 by a sputtering method, and a conductive film 14B of, for example, tungsten is deposited by a CVD method. Subsequently, the plug 14 is formed by removing the barrier conductor film 14A and the conductive film 14B on the silicon oxide film 12 other than the connection holes 13 by, for example, the CMP method.

Next, as shown in FIGS. 6 and 7, an etch made of a silicon nitride film having a film thickness of about 100 nm on the element formation surface of the wafer 1 is formed on the wafer 1 by, for example, a single wafer type plasma CVD apparatus. A stopper film (insulating film) 15 is formed. At this time, the thickness of the etch stopper film 15 in the bevel region of the wafer 1 is relatively thinner than the element formation surface. On the back surface of the wafer 1, the etch stopper film 15 is hardly formed. The etch stopper film 15 has a function of avoiding damage to the lower layer due to excessive digging and deterioration of processing dimensional accuracy when forming a groove or a hole for forming a wiring in the insulating film on the upper layer. , And a function of preventing Cu deposited on the wafer 1 in a later step from diffusing into the thin film T.

Subsequently, for example, the surface of the etch stopper film 15 is doped with fluorine-added Si by a single-wafer CVD apparatus.
An OF (silicon oxide) film is deposited, and an insulating film 16 having a thickness of about 400 nm on the element formation surface of the wafer 1 is deposited. At this time, the insulating film 16 in the bevel region of the wafer 1 is formed.
Is relatively thinner than the element formation surface. On the back surface of the wafer 1, the insulating film 16 is hardly formed. When an SiOF film is used as the insulating film 16, since the SiOF film is a low dielectric constant film, the overall dielectric constant of the wiring of the semiconductor integrated circuit device can be reduced, and the wiring delay can be improved.

Next, as shown in FIG. 8, a protective film 17 is selectively formed on the bevel region (first region) of the wafer 1.
At this time, the protective film 17 does not cover the flat portion of the element formation surface of the wafer 1 so as not to affect the thickness distribution of the photoresist film formed on the element formation surface of the wafer 1. By forming this protective film 17, the insulating film 16 not covered by the photoresist film on the bevel region of the wafer 1 can be formed in an etching process for forming a wiring groove in the etch stopper film 15 and the insulating film 16 later. In addition, the etching of the etch stopper film 15 can be prevented.

In a later step, in order to prevent the protective film 17 from becoming a source of foreign matter, the protective film 17 is removed in a step until the embedded wiring is formed in the insulating film 16 later. It is desirable to form. It is desirable that the protective film 17 have appropriate mechanical strength.
That is, when the wafer 1 is transferred, the bevel region of the wafer 1 comes into contact with a wafer cassette or the like, so that the wafer 1
The purpose is to prevent microscopic breakage from occurring. This is because the damaged wafer 1 is further damaged during the photolithography process and the etching process, and has a possibility of cracking or generating foreign matter from a damaged portion.

Thus, in the first embodiment, an organic resist film made of a novolak resin or the like, an organic film such as a polyimide film, a polyisoprene film, or a polymethyl methacrylate film can be exemplified as the protective film 17. From the viewpoint of mechanical strength, a polyimide film is preferable. In the case where an organic resist film is used as the protective film 17, baking is performed at a higher temperature (about 150 ° C. to 200 ° C.) than in the case where an organic resist film is used in the photolithography process, and the film is sufficiently cured. When an organic resist film is used,
It can be removed simultaneously with the removal of the photoresist film. Therefore, even if the protective film 17 is provided, the number of steps for removing the protective film 17 does not increase.

The thickness of the protective film 17 may be such that a desired mechanical strength is obtained. If the desired mechanical strength is obtained, a relatively thin film having a thickness of, for example, about 1 μm or less may be used. It may be.

Here, a method for forming the protective film 17 will be described in detail. First, for example, an organic solvent in which several percent of the organic raw material is dissolved with respect to the amount of the solvent is applied to the bevel portion of the wafer 1. At this time, for example, as shown in FIG. 9, a guide (first mechanism) G is arranged at a predetermined distance from the end of the wafer 1, and the solution dropping mechanism L is placed in a region between the wafer 1 and the guide G. The organic solution 17A is added dropwise. Organic solution 1 dropped
7A can be held between the wafer 1 and the guide G by capillary action. When the guide G is removed in this state, the organic solution 17A can be attached to the bevel region of the wafer 1. Thereafter, the organic solution 17A is heat-treated.
A desired protective film 17 can be formed by advancing the cross-linking reaction while evaporating the organic solvent.

At this time, as the guide G, one having a shape surrounding the entire outer periphery of the wafer 1 may be used, or one having a shape facing a part of the bevel region of the wafer 1 may be used.
In this case, while keeping the distance between the guide G and the outer peripheral end of the wafer 1 constant, the organic solution 17A is moved to the outer peripheral end of the wafer 1 while moving the guide G one or more turns along the outer periphery of the wafer 1. The protective film 17 can be formed over the entire bevel region of the wafer 1 by dropping the guide G on the region between the wafer G and the wafer facing end (hereinafter simply referred to as the facing end). In order to move the guide G along the outer periphery of the wafer 1 while maintaining a constant distance between the opposite end of the guide G and the outer peripheral end of the wafer 1, the opposite end of the guide G and the outer periphery of the wafer 1 are moved. A mechanism for measuring the distance to the end and controlling the distance within a predetermined range may be provided. By providing this mechanism, the amount of the organic solution 17A held between the guide G and the bevel region of the wafer 1 can be adjusted.
Thereby, the thickness of the protective film 17 can be adjusted favorably.

Instead of using the guide G and the solution dropping mechanism L, for example, an organic solution 1 as shown in FIG.
It is also possible to use the pad (second mechanism) P1 wetted with 7A. The pad P1 is formed of a material that is elastically deformed, such as a nonwoven fabric, and can be used while being attached to a highly rigid base P2, such as a metal plate.

After the pad P1 is pressed into the bevel region of the wafer 1 by a predetermined amount, the pad P1 is moved from the contact position along the outer periphery of the wafer 1 so that the organic solution 17A adheres to the bevel region of the wafer 1. Can be. At this time, the wafer 1 is rotated by one or more rotations while keeping the amount of pushing of the pad 1 into the wafer 1 constant, or the pad 1 is moved by one or more rotations along the outer periphery of the wafer 1, and Organic solution 1 over the entire bevel region of 1
7A can be deposited. When rotating the wafer 1 or moving the pad P1 along the outer periphery of the wafer 1, a mechanism (not shown) for keeping the amount of pushing the pad 1 into the wafer 1 constant is used. When the pad P1 is used, the organic solution 17A can be adhered in a more limited state when the protective film 17 is formed.

A predetermined amount of the organic solution 17A is sprayed onto the bevel region of the wafer 1 by a solution spraying mechanism (third mechanism) S as shown in FIG. It can also be attached. Here, the injection rate of the organic solution 17A is kept constant,
By rotating the wafer 1 at a constant rotation speed, the organic solution 17A can be attached to the entire bevel region of the wafer 1. At this time, the injection rate of the organic solution 17A is about 0.1 ml to 0.5 ml per minute, and the rotation speed of the wafer 1 is about several times to several tens of times per minute.

If the organic solution 17A sprayed by the solution spraying mechanism S cannot be sufficiently narrowed so as to be sprayed only to the bevel region of the wafer 1, for example, as shown in FIG. 4) The element formation surface of the wafer 1 may be covered by B. As a result, extra spray particles (organic solution 17A) directed toward the element formation surface of the wafer 1 are accumulated on the shielding plate B, and the organic solution 17A can be selectively attached only to the bevel region of the wafer 1.

FIG. 13 shows the outer peripheral portion of the wafer 1 in more detail, and illustration of each thin film formed on the wafer 1 is omitted for explanation.

In the outer peripheral portion of the wafer 1, particularly in the bevel region, the thicknesses of the etch stopper film 15 and the insulating film 16 are not sufficiently controlled, and the film thickness is smaller than the film thickness on the element forming surface. Relatively thinner. Nevertheless, in the case where the etch stopper film 15 and the insulating film 16 are dry-etched using a single-wafer-type dry etching apparatus, the photoresist film formed in the bevel region of the wafer may be a source of foreign matter. To prevent this, it has been removed before the dry etching step. Therefore, according to the general technique examined by the present inventors, when a groove or the like is formed in the insulating film 16 by etching, the outer peripheral portion of the wafer 1 is removed except for the region A1 covered with the photoresist film. The area A2 is exposed to the etching gas.

On the other hand, in the first embodiment, by covering the area A2 exposed from the photoresist film on the outer periphery of the wafer 1 with the protective film 17,
Most of the bevel region of the wafer 1 can be covered with the photoresist film and the protective film 17. Thereby, the etch stopper film 15 and the insulating film 16 on the bevel region are formed.
Can be prevented from being etched. Further, even if the area A3 close to the back side of the wafer 1 in the bevel area cannot be covered by the protective film 17, the etching rate on the lower side of the wafer 1 is extremely slower than that on the upper side. Exposure of the crystalline silicon can be prevented.

A region A4 at the center of the bevel region (the center in the thickness direction of the outer peripheral edge of the wafer 1) is a portion that is likely to collide with a wafer cassette or the like while the wafer 1 is being transferred.
If a collision occurs, it is a place where minute chips or cracks are likely to occur. As described above, the protective film 17 is formed on the region A4, and it is possible to prevent such minute chips and cracks. Preventing minute chipping and cracking in the region A4 can prevent generation of foreign matter from the region A4 and cracking of the entire wafer 1. That is, the protective film 17 is formed by the etching gas to form the insulating film 16 and the etch stopper film 16.
In addition to protecting the wafer 1, the outer peripheral portion and other members of the wafer 1 are protected from damage due to collision when the wafer 1 is transferred.

Next, as shown in FIGS. 14 and 15,
A photoresist film (masking layer) 18 is formed on the insulating film 16 by a coating method. Subsequently, the photoresist film 18 on the bevel region and the back surface of the wafer 1 is subjected to exposure processing, and then removed by washing with an organic solvent. Next, a photoresist film 18 on the element formation surface of the wafer 1 is formed.
Is patterned by photolithography. At this time, a part of the photoresist film 18 is formed so as to overlap the protective film 17 in the bevel region of the wafer 1.
This makes it possible to reliably prevent the surface of the insulating film 16 from being exposed in the bevel region of the wafer 1 after the formation of the photoresist film 18.

Next, as shown in FIGS. 16 and 17,
The insulating film 16 is dry-etched using the photoresist film 18 as a mask. The dry etching condition at this time is, for example, a single-wafer parallel plate narrow electrode RIE (Reacti
using ve Ion Etching) apparatus, using an etching gas composed of _{CHF 3 / O 2 / Ar CHF} 3, O 2 and respectively 20 cm ₃ / min about the flow rate of Ar, as 20 cm ₃ / min approximately and 200 cm ₃ / min approximately , Internal pressure of 4Pa
The power applied to the upper electrode and the lower electrode of the parallel plate type narrow electrode RIE apparatus is about 1000 W and about 200 W, respectively, and the temperature of the lower electrode is about 0 ° C.

Then, using the photoresist film 18 as a mask, the etch stopper film 15 is etched to form a wiring groove 19.

In the above-described dry etching process of the insulating film 16 and the etch stopper film 15, the protective film 17 serves as a mask in the bevel region of the wafer 1, so that the etching of the insulating film 16 and the etch stopper film 15 can be prevented. Thereby, it is possible to prevent the thin film T under the etch stopper film 15 from being etched. That is, it is possible to prevent a defect that is a source of foreign matter due to the uneven surface of the bevel region of the wafer 1 being unevenly etched.

The purpose of forming the protective film 17 is to prevent the insulating film 16 and the etch stopper film 15 from being etched in the bevel region of the wafer 1 and exposing the silicon oxide film 15 therebelow. is there. That is, immediately after the formation of the wiring groove 19, the insulating film 16 and the etch stopper film 15 are formed over the entire bevel region of the wafer 1.
If the state can be left, the protective film 17 may be removed during the etching step of forming the wiring groove 19.

Next, as shown in FIGS. 18 and 19,
The protection film 17 and the photoresist film 18 are removed by an ashing technique or a cleaning technique. At this time, the protective film 17
Is not completely removed, it may become a source of foreign matter. Therefore, in the step of forming the protective film 17 described above,
The thickness of the protective film 17 is set in advance to a thickness that can be removed.

Subsequently, surface treatment of the wafer 1 is performed by sputter etching in an Ar (argon) atmosphere. Thereby, the reaction layer on the surface of the plug 14 exposed at the bottom of the wiring groove 19 can be removed. At this time, the sputter etching amount is P-TEOS (Plasma Tetraethylo).
(rthosilicate) film, for example, about 20 ° to 180 °, preferably about 100 °. In addition,
1 Oite to this embodiment, a case has been exemplified for removing the reaction layer on the surface of the plug 14 by the sputter etching in an argon atmosphere, for example, H ₂ (hydrogen) and C
If the reaction layer can be sufficiently removed by annealing in a reducing gas such as O (carbon monoxide) or a mixed atmosphere of a reducing gas and an inert gas, this annealing and sputter etching should be replaced. Is also good. In the case of the annealing treatment, loss of the insulating film 16 due to sputter etching and charging damage of the gate oxide film 6 due to electrons can be prevented.

Next, as shown in FIGS. 20 and 21,
On the wafer 1, for example, a Ta (tantalum) film to be a barrier conductor film (first conductive film) 20A is deposited. In the first embodiment, the Ta film can be exemplified to be deposited by a long throw sputtering method in which the distance between the tantalum target and the wafer 1 is about 200 mm and the film thickness is about 50 nm. This TaN film is deposited by improving the adhesion of a Cu (copper) film deposited in a later step and improving the C
This is performed to prevent the diffusion of u. In the first embodiment, a Ta film is exemplified as the barrier conductor film 20A. However, a TaN (tantalum nitride) film, a TiN (titanium nitride) film, a laminated film of a metal film such as a Ta film and a nitride film, or the like is used. There may be. When the barrier conductor film is Ta or TaN, the adhesion to the Cu film is better than when TiN is used. When the barrier conductor film 20A is a TiN film, the surface of the TiN film can be sputter-etched immediately before the formation of the Cu film, which is a subsequent step. By such sputter etching, water, oxygen molecules and the like adsorbed on the surface of the TiN film can be removed, and the adhesion of the Cu film can be improved. This technique is particularly effective when forming a copper film by breaking the vacuum and exposing the surface to the atmosphere after depositing the TiN film. This technique is not limited to the TiN film.
The aN film is also effective although there is a difference in effect.

Subsequently, for example, a Cu film or a copper alloy film serving as a seed film is deposited by a long throw sputtering method in which the distance between the target and the wafer 1 is about 200 mm (not shown). When the seed film is a copper alloy film, the alloy contains Cu in an amount of about 80% by weight or more. The thickness of the seed film is set to be about 100 nm on the surface (flat portion of the element formation surface) of the barrier conductor film 20A excluding the inside of the wiring groove 19. In the first embodiment, a case where a long throw sputtering method is used for depositing a seed film is exemplified. However, an ionized sputtering method that ionizes Cu sputtering atoms to increase the directivity of sputtering may be used.

Subsequently, for example, a Cu film is formed on the entire surface of the wafer 1 on which the seed film is deposited so as to fill the wiring groove 19, and the Cu film and the seed film are combined to form a conductive film (second conductive film). Film) 20B. The Cu film that fills the wiring groove 19 is formed by, for example, an electrolytic plating method, and the plating solution is, for example, 10% CuS in H ₂ SO ₄ (sulfuric acid).
O ₄ (copper sulfate) and an additive for improving the coverage of the Cu film are used. When an electrolytic plating method is used to form the Cu film, the growth rate of the Cu film can be electrically controlled, so that the coverage of the conductive film 20B inside the wiring groove 19 can be improved. In the first embodiment, the case where the electrolytic plating method is used for depositing the conductive film 20B is illustrated, but an electroless plating method may be used. When the electroless plating method is used, since no voltage application is required, damage to the wafer 1 due to the voltage application can be reduced.
It can be reduced as compared with the case where the electrolytic plating method is used.

As described above, the insulating film 16 in the bevel region of the wafer 1 is not exposed to the etching gas during the etching step for forming the wiring groove 19. That is, since the surface of the insulating film 16 can be prevented from being rough, the entire bevel region of the wafer 1 is covered with the barrier conductor film 20.
A can cover. Thereby, the barrier properties of the barrier conductor film 20A in the bevel region of the wafer 1 can be improved, and it is possible to prevent Cu forming the conductive film 20B from diffusing into the wafer 1. That is, it is possible to reliably prevent the problem that Cu diffuses from the outer peripheral portion of the wafer 1 into the chip region. As a result, the yield and operation stability of the semiconductor integrated circuit device according to the first embodiment can be improved.

Further, since the barrier property of the barrier conductor film 20A in the bevel region of the wafer 1 can be improved, the heat treatment step can be performed without adding a step of completely removing Cu attached to the bevel region. . As a result, the manufacturing process of the semiconductor integrated circuit device according to the first embodiment can be simplified.

Further, following the step of forming the conductive film 20B, the Cu film is fluidized by an annealing treatment, so that the filling property of the conductive film 20B into the wiring groove 19 can be further improved.

Next, as shown in FIGS. 22 and 23,
For example, the excess barrier conductor film 20A and the conductive film 20B on the insulating film 16 are polished by the CMP method with the surface of the insulating film 16 on the flat surface of the element forming surface of the wafer 1 as a polishing end point, and the barrier conductor The buried wiring 20 is formed by leaving the film 20A and the conductive film 20B. In the polishing step by the CMP method, for example, a polishing slurry containing an oxidizing agent such as hydrogen peroxide and having alumina abrasive grains dispersed therein is used, and the conductive film 20B and the barrier conductor film 20 are used.
A is collectively polished with the same platen. Since the Cu film has a relatively higher polishing rate than the Ta film, most of the Cu film outside the wiring groove 19 is polished first. Thereafter, over-polishing is performed to remove the excess barrier conductor film 20A remaining outside the wiring groove 19, leaving a laminated film of the barrier conductor film 20A and the conductive film 20B only in the wiring groove 19, and Can be completed. In addition,
In the first embodiment, the time for polishing the Cu film outside the wiring groove 19 is about 2.5 minutes, the over-polishing time for removing the barrier conductor film 20A is about 0.5 minutes, It can be exemplified that polishing is performed for about 3 minutes in total.

Subsequently, the polishing abrasive grains and Cu adhered to the surface of the wafer 1 are removed by, for example, two-stage brush scrub cleaning using a 0.1% aqueous ammonia solution and pure water. Can be completed. Although the barrier conductor film 20A may remain in the bevel region of the wafer 1 after the above-described CMP step and cleaning step, the semiconductor chip to be a product is not obtained from the bevel region. Membrane 20
A thin film can be stacked on the remaining barrier conductor film 20A without adding a step of removing A.

Next, as shown in FIGS. 24 and 25,
A silicon nitride film is deposited on the buried wiring 20 and the insulating film 16 to form a barrier insulating film 21A. For deposition of this silicon nitride film, for example, a plasma CVD method can be used, and its thickness is set to about 50 nm. The barrier insulating film 21A has a function of suppressing diffusion of Cu, which is the conductive film 20B. This prevents diffusion of copper into the silicon oxide film 12, the insulating film 16 together with the barrier conductor film 20A and the insulating film formed on the barrier insulating film 21A in a later step, maintains their insulating properties, and improves semiconductor integration. The reliability of the circuit device can be improved. The barrier insulating film 21A also functions as an etch stopper layer when performing etching in a later step.

Subsequently, an insulating film 21B having a thickness of about 400 nm is deposited on the surface of the barrier insulating film 21A. This insulating film 21B is an SiOF film such as a CVD oxide film to which fluorine is added. When an SiOF film is used as the insulating film 21B, the overall dielectric constant of the wiring of the semiconductor integrated circuit device can be reduced, and the wiring delay can be improved.

Subsequently, a silicon nitride film is deposited on the surface of the insulating film 21B by, for example, a plasma CVD method, and an etch stopper film 21C having a thickness of about 50 nm is deposited. When the etching stopper film 21C forms a groove or a hole for forming a wiring in an insulating film deposited on the etching stopper film 21C in a later step, excessive etching may damage the lower layer or deteriorate processing dimensional accuracy. Or to avoid doing so.

Subsequently, for example, an SiOF film is deposited on the surface of the etch stopper film 21C to form an insulating film 21D.
The insulating film 21 is formed by combining the barrier insulating film 21A, the insulating film 21B, the etch stopper film 21C, and the insulating film 21D. The insulating film 21D is deposited by a CVD method, and has a thickness of, for example, about 300 nm. This insulating film 21D
Has a function of lowering the overall dielectric constant of the wiring of the semiconductor integrated circuit device, similarly to the insulating film 21B, and can improve the wiring delay.

Subsequently, the insulating film 21D is formed, for example, by CMP.
After the surface is flattened by polishing by a method, a silicon oxide film having a thickness of about 100 nm is deposited on the insulating film 21D by, for example, a plasma CVD method using TEOS gas, and the insulating film 22 is deposited. Subsequently, the insulating film 2
An anti-reflection film 23A having a thickness of about 0.12 μm is formed on the surface of No. 2.

Subsequently, a protective film 24A is formed in the bevel region of the wafer 1 by a process similar to the process of forming the protective film 17 (see FIG. 8). By forming this protective film 24A, similarly to the case of the protective film 17, the photoresist film on the bevel region of the wafer 1 is covered by etching when forming a connection hole in the insulating film 21 in a later step. It is possible to prevent the unetched insulating film 21 from being etched. Further, by forming the protective film 24A, it is possible to prevent the wafer 1 from being damaged due to the bevel region of the wafer 1 coming into contact with a wafer cassette or the like.

Next, as shown in FIGS. 26 and 27,
The photoresist film 18 (see FIGS. 14 and 15)
In the same process as the process of film formation and patterning,
Photoresist film (masking layer) 25 on insulating film 21
Form A. At this time, similarly to the case of the photoresist film 18, a part of the photoresist film 25A is formed so as to overlap the protective film 24A in the bevel region of the wafer 1. This makes it possible to reliably prevent the surface of the insulating film 21 from being exposed in the bevel region of the wafer 1 after the formation of the photoresist film 25A.

Next, as shown in FIGS. 28 and 29,
Using the photoresist film 25A as a mask, for example, CHF
_The anti-reflection film 23 is etched using an etching gas containing ₃ / CF ₄ / Ar as a component. Then, for example, C ₄
Using an etching gas containing F ₈ / O ₂ / Ar as a component,
The insulating film 21D on the insulating film 22 and the etch stopper film 21C is etched. Then, for example, CHF ₃
Etch stopper film 21C is etched using an etching gas containing / O ₂ as a component. Subsequently, the insulating film 21B below the etch stopper film 21C is etched using an etching gas containing, for example, C ₄ F ₈ / O ₂ / Ar as a component. By the steps up to this point, the connection hole 26A
Can be formed.

At this time, in the bevel region of the wafer 1, the protective film 24A serves as a mask, so that the etching of the insulating film 21 can be prevented. Accordingly, it is possible to prevent the insulating film 16 and the etch stopper film 15 below the insulating film 21 and the thin film T below the insulating film 21 from being etched. That is, the surface of the bevel region of the wafer 1 becomes a rough surface which is unevenly etched, and can be prevented from becoming a source of foreign matter.

Next, as shown in FIGS. 30 and 31,
The photoresist film 25A, the protective film 24A, and the antireflection film 2 are formed by the same process as the process of removing the protective film 17 and the photoresist film 18 (see FIGS. 18 and 19).
Remove 3A.

Next, as shown in FIGS. 32 and 33,
After embedding an anti-reflection film made of the same material as the anti-reflection film 23A (see FIGS. 24 and 25) in the connection hole 26A,
Further, the antireflection film is formed on the wafer 1 and the connection hole 2 is formed.
The antireflection film in 6A and the antireflection film on the wafer 1 are combined to form an antireflection film 23B.

Subsequently, a protective film 24B is formed in the bevel region of the wafer 1 by a process similar to the process of forming the protective film 17 (see FIG. 8) and the protective film 24A. By forming this protective film 24B, similarly to the case of the protective film 17 and the protective film 24A, the photoresist on the bevel region of the wafer 1 is etched by etching when forming a wiring groove in the insulating film 21 in a later step. Insulating film 21 not covered with film
Can be prevented from being etched. Further, by forming the protective film 24B, it is possible to prevent the wafer 1 from being damaged due to the bevel region of the wafer 1 coming into contact with a wafer cassette or the like.

Subsequently, a photoresist film (masking layer) 25B is formed on the insulating film 21 by a process similar to the process of forming and patterning the photoresist film 18 and the photoresist film 25A. At this time, as in the case of the photoresist film 18 and the photoresist film 25A, a part of the photoresist film 25B is formed so as to overlap the protective film 24B in the bevel region of the wafer 1. Thereby, after the formation of the photoresist film 25B,
Exposing the surface of the insulating film 21 in the bevel region of the wafer 1 can be prevented.

Next, as shown in FIGS. 34 and 35,
Using the photoresist film 25B as a mask, for example, N ₂ /
The insulating film 22 is formed using an etching gas containing O ₂ as a component.
Is etched on the antireflection film 23B on the upper part of FIG. continue,
The insulating film 22 and the insulating film 21D above the etch stopper film 21C are etched using an etching gas containing C ₄ F ₈ / O ₂ / Ar as a component. At this time, in the bevel region of the wafer 1, the protective film 24B serves as a mask, so that the etching of the insulating film 21 can be prevented.

The protection films 17, 24A, 2 according to the first embodiment
If the etching process is repeated without forming 4B, all the insulating films such as the insulating film 21, the insulating film 16, the etch stopper film 15, and the thin film T may be etched in the bevel region of the wafer 1. . In such a case, for example, there is a possibility that a metal film such as the barrier conductive film 20A and the conductive film 20B forming the buried wiring 20 is exposed and peeled off and becomes a source of foreign matter. Further, when the insulating film is etched in the bevel region of the wafer 1, the single crystal silicon forming the wafer 1 appears. If the process of forming the buried wiring is advanced in this situation, the surface of the single crystal silicon is so rough that it cannot be covered with the barrier conductor film for preventing the diffusion of Cu. It will spread inside.

In the first embodiment, by forming the protective films 17, 24A and 24B in the bevel region of the wafer 1, even when the etching process is repeated, the etching of the insulating film in the bevel region is prevented. It is possible. Thus, the exposure of the metal film forming the embedded wiring and the exposure of the single crystal silicon forming the wafer 1 can be prevented. As a result, it is possible to prevent Cu from diffusing into single-crystal silicon, so that the yield and operation stability of the semiconductor integrated circuit device according to the first embodiment can be improved.

Next, as shown in FIGS. 36 and 37,
The photoresist film 25B and the protective film 2 are formed by the same process as the process of removing the photoresist film 25A, the protective film 24A and the antireflection film 23A (see FIGS. 30 and 31).
4B and the antireflection film 23B are removed to form a wiring groove 26B.

Next, as shown in FIGS. 38 and 39,
A sputter etching process performed to remove the reaction layer on the surface of the plug 14 exposed at the bottom of the wiring groove 19 (FIG. 1)
8 and FIG. 19).
Sputter etching is performed to remove the reaction layer on the surface of the embedded wiring 20 exposed at the bottom of A. The sputter etching amount at this time is 2 in terms of a P-TEOS film.
It is about 0 ° to 180 °, preferably about 100 °.

Subsequently, the barrier conductor film (first conductive film) is formed on the wafer 1 by the same process as the process of depositing the Ta film as the barrier conductor film 20A (see FIGS. 20 and 21).
A Ta film to be 27A is deposited. In the first embodiment, the Ta film is exemplified as the barrier conductor film 27A.
As in the case of the barrier conductor film 20A, a TaN film, TiN
It may be a film or a laminated film of a metal film and a nitride film.

Subsequently, for example, a Cu film or a copper alloy film serving as a seed film similar to the seed film when forming the conductive film 20B is deposited by a long throw sputtering method or an ionization sputtering method (not shown). . Thereafter, the entire surface of the wafer 1 on which the seed film has been deposited, the conductive film 20B that fills the wiring groove 19 becomes Cu.
By a process similar to the process of depositing the film, for example, a Cu film is deposited so as to fill the connection hole 26A and the wiring groove 26B, and the Cu film and the seed film are combined to form a conductive film (second conductive film) 27B. And After the conductive film 27B is formed, the Cu film is fluidized by an annealing process, so that the filling property of the conductive film 27B into the connection holes 26A and the wiring grooves 26B can be further improved.

As in the step of forming the wiring groove 19 (see FIGS. 16 and 17), the connection hole 26A and the wiring groove 2 are formed.
During the etching process for forming 6B, the insulating film 22 in the bevel region of the wafer 1 is not exposed to the etching gas. That is, since the surface of the insulating film 22 can be prevented from becoming rough, the entire bevel region of the wafer 1 can be covered with the barrier conductor film 27A. Thereby, the barrier conductor film 27A in the bevel region is formed on the wafer 1.
Of the conductive film 27B can be prevented from diffusing into the wafer 1. As a result, the yield and operation stability of the semiconductor integrated circuit device according to the first embodiment can be improved.

Further, similarly to the case of the barrier conductor film 20A, the barrier property of the barrier conductor film 27A in the bevel region of the wafer 1 can be improved, so that a step of completely removing Cu attached to the bevel region can be eliminated. A heat treatment step can be performed. As a result, the manufacturing process of the semiconductor integrated circuit device according to the first embodiment can be simplified.

Subsequently, excess barrier conductor film 27A and conductive film 27B on insulating film 22 are removed, and connection holes 26A
The buried wiring 27 is formed by leaving the barrier conductor film 27A and the conductive film 27B inside the wiring groove 26B. The removal of the barrier conductor film 27A and the conductive film 27B is performed by polishing using, for example, a CMP method.

Subsequently, the abrasive grains and Cu attached to the surface of the wafer 1 are removed by two-stage brush scrub cleaning using, for example, a 0.1% ammonia aqueous solution and pure water. A semiconductor integrated circuit device is manufactured. After the above-described CMP step and cleaning step, the barrier conductor film 27A may remain in the bevel region of the wafer 1 as in the case of the barrier conductor film 20A (see FIG. 23). Since no chip is obtained, the remaining barrier conductor film 2 can be removed without adding a step of removing the remaining barrier conductor film 27A.
It is possible to laminate a thin film on 7A. FIG.
By the same steps as those described with reference to FIGS.
Wiring may be further formed in multiple layers above the embedded wiring 27.

In the above-described first embodiment, the case where the protective film is formed in the bevel region of the wafer 1 before performing all the etching processes at the time of forming the embedded wirings 20 and 27 has been described. Since the purpose is to prevent exposure in the bevel region of the wafer 1, it is not always necessary to apply to all photolithography steps. Depending on the film thickness in the bevel region and the dry etching conditions at the time of forming the insulating film, if the metal film forming the underlying embedded wiring and the single crystal silicon forming the wafer 1 are not exposed,
Normally, a protective film similar to the above-described protective film 17 may be formed about once every time about two or three wiring layers are formed. This makes it possible to reduce the number of manufacturing steps of the semiconductor integrated circuit device according to the present embodiment.

(Embodiment 2) In the method of manufacturing a semiconductor integrated circuit device according to Embodiment 2, a process of forming a protective film in the bevel region of the wafer 1 in Embodiment 1 and a method of forming the protective film after the formation of the protective film This is the reverse of the process of forming the photoresist film. Other members and manufacturing steps are the same as those in the above-described step 1.

The method of manufacturing the semiconductor integrated circuit device according to the second embodiment is the same as that of the first embodiment up to the step described with reference to FIG.

After that, as shown in FIG. 40, the photoresist film 18 (FIG.
And FIG. 15) are formed on the insulating film 16. Subsequently, the photoresist film 18 on the bevel region and the back surface of the wafer 1 is subjected to exposure processing, and then removed by washing with an organic solvent. Next, the photoresist film 18 on the element formation surface of the wafer 1 is patterned by photolithography.

Next, as shown in FIG. 41, the protective film 17 (see FIG. 8) described in the first embodiment is formed in the bevel region of the wafer 1. By forming this protective film 17, an insulating film which is not covered by the photoresist film on the bevel region of the wafer 1 by etching when forming a wiring groove in the etch stopper film 15 and the insulating film 16 in a later step 16 and the etch stopper film 15 can be prevented from being etched. Further, a part of the protective film 17 is formed so as to overlap the photoresist film 18 in the bevel region of the wafer 1. This makes it possible to reliably prevent the surface of the insulating film 16 from being exposed in the bevel region of the wafer 1 after the formation of the protective film 17. Further, by forming the protective film 17, it is possible to prevent the wafer 1 from being finely damaged due to the bevel region of the wafer 1 coming into contact with a wafer cassette or the like.

Next, as shown in FIG. 42, the insulating film 16 and the etch stopper film 15 are etched by a process similar to the dry etching process described with reference to FIGS. Then, a wiring groove 19 is formed.

As in the case of the first embodiment, in the above-described dry etching step of the insulating film 16 and the etch stopper film 15, the protective film 17 serves as a mask in the bevel region of the wafer 1, and the insulating film 16 and the etch Etching of the stopper film 15 can be prevented. This allows
It is possible to prevent the silicon oxide film 12 below the etch stopper film 15 from being etched. In other words, it is possible to prevent the surface of the bevel region of the wafer 1 from being unevenly etched and roughening the surface, thereby preventing the generation of foreign matter from the bevel region. If the insulating film 16 and the etch stopper film 15 can be left over the entire bevel region of the wafer 1 after the etching process of the etching stopper 15, the protective film 17 is removed during the etching step of forming the wiring groove 19. You may.

Thereafter, in the first embodiment, FIG.
The semiconductor integrated circuit device according to the second embodiment is manufactured by the same steps as those described with reference to FIGS.

The photoresist film 25A and the protective film 24
A (see FIGS. 25 to 27), a photoresist film 25B and a protective film 24B (see FIGS. 32 and 3).
3) also in the step of forming the photoresist film 18 and the protective film 17 in the same order as the step of forming the photoresist film 18 and the protective film 17.
The photoresist film may be formed first, and the protection film may be formed later.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above-described embodiment, the invention mainly made by the present inventors is applied to a semiconductor substrate.
Although the method for manufacturing the semiconductor integrated circuit device on which the MIS is formed has been illustrated, the present invention may be applied to a method for manufacturing a semiconductor integrated circuit device on which the pMIS is formed.

The method of manufacturing a semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device manufactured by a wiring forming process using a damascene method, such as a microprocessor, which requires a high-speed operation, an SRAM (Static R).
The present invention can also be applied to a semiconductor integrated circuit device having a memory circuit that requires high-speed operation, such as an andom access memory, or a hybrid semiconductor integrated circuit device in which the microprocessor and the memory circuit are provided on the same semiconductor substrate.

[0113]

The effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows. (1) A step of forming at least one of a connection hole and a wiring groove by etching an insulating film on an element formation surface of a wafer by covering the insulating film with a protective film on a bevel region (first region) of the wafer. In the above, since the insulating film on the bevel region can be prevented from being etched,
The generation of foreign matter from the bevel region can be prevented. (2) A step of forming at least one of a connection hole and a wiring groove by etching the insulating film on the element formation surface of the wafer by covering the insulating film with a protective film on the bevel region (first region) of the wafer. In the above, since the insulating film on the bevel region can be prevented from being etched,
The barrier property of the barrier conductor film in the bevel region of the wafer can be improved.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention;

FIG. 2 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 1;

3 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 2;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to the embodiment of the present invention during a manufacturing step;

5 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 3;

6 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 5;

FIG. 7 is an essential part cross sectional view of the semiconductor integrated circuit device of one embodiment of the present invention during a manufacturing step;

8 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 7;

FIG. 9 is a fragmentary cross-sectional view showing one example of a method for forming a protective film in a bevel region of a wafer during a manufacturing process of a semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view showing another example of the method for forming the protective film in the bevel region of the wafer during the manufacturing process of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view showing still another example of the method for forming the protective film in the bevel region of the wafer during the manufacturing process of the semiconductor integrated circuit device according to one embodiment of the present invention;

12 is a fragmentary cross-sectional view showing a modification of the method of forming the protective film shown in FIG.

FIG. 13 is a fragmentary cross-sectional view showing the vicinity of a bevel region of a wafer used for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view of the semiconductor integrated circuit device according to the embodiment of the present invention during a manufacturing step;

15 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 8;

16 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 14;

17 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 15;

18 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 16;

19 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 17;

20 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 18;

21 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 19;

FIG. 22 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 20;

23 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 21;

FIG. 24 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 22;

FIG. 25 is an essential part cross sectional view of the semiconductor integrated circuit device of one embodiment of the present invention during a manufacturing step;

26 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 24;

FIG. 27 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 25;

FIG. 28 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 26;

FIG. 29 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 27;

30 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 28;

FIG. 31 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 29;

32 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 30;

FIG. 33 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 31;

34 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 32;

35 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 33;

36 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 34;

FIG. 37 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 35;

38 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 36;

39 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 37;

FIG. 40 is an essential part cross sectional view showing the method of manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 41 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 40;

FIG. 42 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 41;

[Explanation of symbols]

Reference Signs List 1 wafer 2 groove 3 silicon oxide film 4 silicon oxide film 5 p-type well 6 gate oxide film 7 gate electrode 8 cap insulating film 9 n ^- type semiconductor region 10 sidewall spacer 11 n ⁺ type semiconductor region (source, drain) 12 oxidation Silicon film 13 Connection hole 14 Plug 14A Barrier conductor film 14B Conductive film 15 Etch stopper film (insulation film) 16 Insulation film 17 Protective film 17A Organic solution 18 Photoresist film (masking layer) 19 Wiring groove 20A Barrier conductor film (first) 20B Conductive film (second conductive film) 20 Embedded wiring 21 Insulating film 21A Barrier insulating film 21B Insulating film 21C Etch stopper film 21D Insulating film 22 Insulating film 23A Anti-reflective film 23B Anti-reflective film 24A Protective film 24B Protective film 25A Photoresist film (masking layer) 25B Photoresist film (masking layer) 26A Connection hole 26B Wiring groove 27 Embedded wiring 27A Barrier conductor film (first conductive film) 27B Conductive film (second conductive film) A1-A4 region B Shield plate (fourth mechanism) ) G guide (first mechanism) L solution dropping mechanism P1 pad (second mechanism) P2 base Qn nMIS S solution jetting mechanism (third mechanism) T thin film

Continuing from the front page (72) Inventor Hiroyuki Maruyama 6-16-16 Shinmachi, Ome-shi, Tokyo 3 Co., Ltd. Inside the Hitachi, Ltd. Device Development Center (72) Inventor Ken Tsugane 6-16-16 Shinmachi, Ome-shi, Tokyo 3 Co., Ltd. Inside Hitachi, Ltd. Device Development Center (72) Inventor Takuya Nise 5-2-2-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Hitachi Ultra-SII Systems Co., Ltd. (72) Inventor Kensuke Ishikawa Ome, Tokyo 6-16-16, Shinmachi, Shichi, Japan Hitachi, Ltd. Device Development Center Co., Ltd. (72) Inventor Norita Yoneya 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo F-term in the Hitachi, Ltd. Semiconductor Group (reference) 5F033 HH11 HH21 HH32.

Claims (39)

[Claims] 1. A step of forming an insulating film on a semiconductor wafer, a step of forming a masking layer on the insulating film, and a step of protecting a first region of an outer peripheral portion of the semiconductor wafer. Forming a film; (d) after the steps (b) and (c), etching the insulating film using the masking layer as a mask to form at least one of a connection hole and a wiring groove; e) after the step (d), removing the masking layer and the protective film;
(F) forming a first conductive film on the surface of the insulating film including the inside of the connection hole and the wiring groove; (g) forming the connection hole and the wiring groove on the surface of the first conductive film; Forming a second conductive film to be buried, (h) removing the first conductive film and the second conductive film outside the connection hole and the wiring groove to form at least one of a plug and a wiring A method of manufacturing a semiconductor integrated circuit device. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the step (c) is performed after the step (b). 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the step (c) is performed before the step (b). 4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said protective film is made of a material which is removed simultaneously with said masking layer in said step (e). Manufacturing method. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said protective film is an organic film containing polyimide as a main component. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said protective film and said masking layer partially overlap each other. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said second conductive film contains copper as a main component. 8. A step of forming an insulating film on a semiconductor wafer, a step of forming a masking layer on the insulating film, and a step of forming a masking layer on the insulating film.
Forming a protective film mainly composed of an organic material,
(D) after the steps (b) and (c), etching the insulating film using the masking layer as a mask to form at least one of a connection hole and a wiring groove; (e) the step (d). Removing the masking layer and the protective film after the step; (f) forming a first conductive film on the surface of the insulating film including the inside of the connection hole and the wiring groove; Forming a second conductive film for burying the connection hole and the wiring groove on the surface of the first conductive film; and (h) forming the first conductive film outside the connection hole and the wiring groove and the second conductive film. 2 Remove the conductive film,
A method for manufacturing a semiconductor integrated circuit device, comprising: forming at least one of a plug and a wiring. 9. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein the step (c) is performed after the step (b). 10. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein the step (c) is performed before the step (b). 11. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein said protective film is made of a material which is removed simultaneously with said masking layer in said step (e). Manufacturing method. 12. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein said protective film and said masking layer partially overlap each other. 13. The method for manufacturing a semiconductor integrated circuit device according to claim 8, wherein said protective film contains polyimide as a main component. 14. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein the step (c) comprises: (c1) placing the first mechanism at a position on the outer peripheral portion of the semiconductor wafer which is not in contact with the first region. (C2) injecting a solution to be a material of the protective film between the first region and the first mechanism at a predetermined rate, and holding the solution;
(C3) evaporating a solvent from the solution to form the protective film. 15. The method of manufacturing a semiconductor integrated circuit device according to claim 14, wherein, in the step (c2), the semiconductor wafer is kept at a constant distance between the first region and the first mechanism. And a method of manufacturing a semiconductor integrated circuit device, characterized in that at least one of the first mechanism is rotated at least once around a center of the semiconductor wafer at a predetermined number of rotations. 16. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein in the step (c), (c1) the first region on the outer peripheral portion of the semiconductor wafer is made of a solution serving as a material of the protective film. A semiconductor integrated circuit device comprising: a step of applying the solution to the first region by pushing it into the wet second mechanism; and (c2) evaporating a solvent from the solution to form the protective film. Manufacturing method. 17. The method of manufacturing a semiconductor integrated circuit device according to claim 16, wherein in the step (c1), the semiconductor wafer is kept constant while the first region is pushed into the second mechanism. And a method of manufacturing a semiconductor integrated circuit device, wherein at least one of the second mechanism is rotated at least once around a center of the semiconductor wafer at a predetermined number of rotations. 18. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein the step (c) comprises: (c1) using the third mechanism to protect the first region in an outer peripheral portion of the semiconductor wafer using a third mechanism. By spraying the solution that will be the material of the membrane,
A method for manufacturing a semiconductor integrated circuit device, comprising: a step of applying the solution; and (c2) a step of evaporating a solvent from the solution to form the protective film. 19. The method for manufacturing a semiconductor integrated circuit device according to claim 18, wherein in the step (c1), a fourth mechanism is disposed at a position separated by a predetermined distance from an element formation surface of the semiconductor wafer, A method for manufacturing a semiconductor integrated circuit device, wherein the solution is selectively applied to the first region. 20. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein said second conductive film contains copper as a main component. 21. (a) forming an insulating film on a semiconductor wafer, (b) forming a masking layer on the insulating film, and (c) protecting a first region on an outer peripheral portion of the semiconductor wafer. Forming a film; (d) after the steps (b) and (c), etching the insulating film using the masking layer as a mask to form at least one of a connection hole and a wiring groove; e) After the step (d),
Removing the masking layer and the protective film. A method for manufacturing a semiconductor integrated circuit device, comprising: 22. The method of manufacturing a semiconductor integrated circuit device according to claim 21, wherein the step (c) is performed after the step (b). 23. The method of manufacturing a semiconductor integrated circuit device according to claim 21, wherein the step (c) is performed before the step (b). 24. The method of manufacturing a semiconductor integrated circuit device according to claim 21, wherein said protective film has a mechanical strength such that no foreign matter is generated at the time of etching in said step (d). A method for manufacturing a semiconductor integrated circuit device. 25. The method of manufacturing a semiconductor integrated circuit device according to claim 21, wherein said protective film is made of a material which is removed simultaneously with said masking layer in said step (e). Manufacturing method. 26. The method of manufacturing a semiconductor integrated circuit device according to claim 21, wherein said protective film is an organic film containing polyimide as a main component. 27. The method of manufacturing a semiconductor integrated circuit device according to claim 21, wherein said protective film and said masking layer partially overlap each other. 28. (a) a step of forming an insulating film on a semiconductor wafer, (b) a step of forming a masking layer on the insulating film, and (c) a first region on an outer peripheral portion of the semiconductor wafer. Forming a protective film mainly composed of an organic material,
(D) after the steps (b) and (c), etching the insulating film using the masking layer as a mask to form at least one of a connection hole and a wiring groove; (e) the step (d). Removing the masking layer and the protective film after the step. 29. The method of manufacturing a semiconductor integrated circuit device according to claim 28, wherein the step (c) is performed after the step (b). 30. The method of manufacturing a semiconductor integrated circuit device according to claim 28, wherein the step (c) is performed before the step (b). 31. The method of manufacturing a semiconductor integrated circuit device according to claim 28, wherein said protective film is made of a material which is removed simultaneously with said masking layer in said step (e). Manufacturing method. 32. The method of manufacturing a semiconductor integrated circuit device according to claim 28, wherein said protective film and said masking layer partially overlap each other. 33. The method of manufacturing a semiconductor integrated circuit device according to claim 28, wherein said protective film is mainly composed of polyimide. 34. The method of manufacturing a semiconductor integrated circuit device according to claim 28, wherein the step (c) comprises: (c1) placing the first mechanism at a position on the outer peripheral portion of the semiconductor wafer which is not in contact with the first region. Arranging, (c2) the first step
Injecting a solution to be a material of the protective film between a region and the first mechanism at a predetermined rate, and holding the solution;
(C3) evaporating a solvent from the solution to form the protective film. 35. The method of manufacturing a semiconductor integrated circuit device according to claim 34, wherein in the step (c2), the semiconductor wafer is kept at a constant distance between the first region and the first mechanism. And a method of manufacturing a semiconductor integrated circuit device, characterized in that at least one of the first mechanism is rotated at least once around a center of the semiconductor wafer at a predetermined number of rotations. 36. The method of manufacturing a semiconductor integrated circuit device according to claim 28, wherein in the step (c), (c1) the first region on the outer peripheral portion of the semiconductor wafer is a solution that becomes a material of the protective film. Push into the wet second mechanism,
A method for manufacturing a semiconductor integrated circuit device, comprising: a step of applying the solution to a region; and (c2) a step of evaporating a solvent from the solution to form the protective film. 37. In the method of manufacturing a semiconductor integrated circuit device according to claim 36, in the step (c1), the semiconductor wafer is kept constant while pushing the first region into the second mechanism. And a method of manufacturing a semiconductor integrated circuit device, wherein at least one of the second mechanism is rotated at least once around a center of the semiconductor wafer at a predetermined rotation speed. 38. The method of manufacturing a semiconductor integrated circuit device according to claim 28, wherein in the step (c), (c1) the protection is performed by using a third mechanism in the first region on an outer peripheral portion of the semiconductor wafer. A step of applying the solution as a material for the film by spraying the solution; and (c2) evaporating a solvent from the solution to form the protective film. Production method. 39. The method of manufacturing a semiconductor integrated circuit device according to claim 38, wherein in the step (c1), a fourth mechanism is disposed at a position separated by a predetermined distance from the semiconductor wafer, and A method for manufacturing a semiconductor integrated circuit device, wherein the method is applied only to a first region.