CN111739937A - Fabrication of a SiC MOSFET Based on High-k Gate Dielectric and Low-Temperature Ohmic Contact Technology - Google Patents

Abstract

The invention relates to a preparation method of a SiC MOSFET based on a high-k gate dielectric and a low-temperature ohmic contact process, comprising: cleaning a SiC substrate with an epitaxial N-type lightly doped SiC layer; form N+ source region, P-type channel region and P+ terminal region; deposit high-k gate dielectric layer on the epitaxial layer, then deposit gate metal, and pattern by etching; deposit passivation layer dielectric on the epitaxial layer, and pass Etch patterning; deposit low temperature ohmic contact metal layer on epitaxial layer and heavily doped substrate, anneal to form ohmic contact; thicken metal on epitaxial layer and heavily doped substrate. This method reduces the carbon cluster density at the gate interface and improves the channel mobility.

Description

A SiC MOSFET based on high-k gate dielectric and low-temperature ohmic contact process preparation

technical field

The invention belongs to the field of semiconductor power devices, and particularly relates to a preparation method of a SiC MOSFET based on a high-k gate dielectric and a low-temperature ohmic contact process.

Background technique

Silicon carbide material has large forbidden band width, high breakdown electric field, large thermal conductivity and stable physical properties, and is an excellent manufacturing material for high-power, high-voltage, high-temperature power semiconductor devices. Since silicon carbide has the characteristics of realizing N and P types through doping, and generating SiO ₂ by natural oxidation, its preparation process has a high degree of compatibility and similarity with the traditional silicon power device process. Mature craftsmanship.

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used electronic devices. It is a majority carrier device, which avoids minority carrier injection during bipolar transistor operation, so it has a faster response speed. At the same time, silicon carbide power MOSFETs can provide a very large safe operating area, and multiple cell structures can be used in parallel, with high power density advantages.

However, there are still some problems in the silicon carbide MOSFET prepared by thermal oxidation process: the silicon oxide generated by thermal oxidation of silicon carbide will have carbon residues in the form of dangling bonds and carbon clusters at the interface, which will lead to a higher SiC/SiO2 interface. interface state, the mobility of the device decreases, and the electrical conductivity deteriorates. At the same time, the relative permittivity of SiO ₂ is 3.9, while that of SiC is about 9.7, which will make the SiO ₂ side of the SiC/SiO ₂ interface have a high electric field strength when the device is working, which will limit the reliability of the device. For example: "Advanced processing for mobility improvement in 4H-SiCMOSFETs: A review", by C.Maria et al., Mat.Sci.Semicon.Proc., 2018; "Improvedinversion channel mobility for 4H-SiC MOSFETs following high temperatureanneals in nitric oxide", GY Chung et al., IEEE Electron Device Letter, 2001; "Silicon carbide: A unique platform for metal-oxide-semiconductor physics", G. Liu et al., Applied Physics Reviews, 2015.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is to provide a preparation method of SiC MOSFET based on high-k gate dielectric and low-temperature ohmic contact process, so as to overcome the defect of low mobility of traditional SiC MOSFET.

The present invention provides a preparation method of a SiC MOSFET based on a high-k gate dielectric and a low-temperature ohmic contact process, comprising:

(1) cleaning the SiC substrate of the epitaxial N-type lightly doped SiC layer;

(2) The N+ source region, the P-type channel region and the P+ terminal region are formed by ion implantation and annealing in the epitaxial layer of the SiC substrate;

(3) depositing a high-k gate dielectric layer on the epitaxial layer;

(4) depositing gate metal on the surface of the high-k gate dielectric layer, and patterning the gate metal and the dielectric by etching;

(5) depositing a passivation layer medium on the epitaxial layer, and patterning it by etching;

(6) depositing a low-temperature ohmic contact metal layer on the epitaxial layer and the heavily doped substrate, and annealing to form an ohmic contact;

(7) Thicken the metal in the epitaxial layer and the heavily doped substrate.

In the step (1), the thickness of the SiC substrate is 200-400 μm, and the doping concentration is 1×10 ¹⁶ -1×10 ²¹ cm ^-3 .

In the step (1), the thickness of the epitaxial N-type lightly doped SiC layer is 5-30 μm, and the doping concentration is 1×10 ¹⁴ -1×10 ¹⁷ cm ^-3 .

The cleaning process in the step (1) includes: standard RCA cleaning; high-temperature oxidation of the silicon carbide epitaxial wafer to form a sacrificial oxide layer, and then etching the sacrificial oxide layer until the surface oxide layer is completely removed.

The ions implanted in the step (2) are N ions, P ions or Al ions. P-type ions with a doping concentration of 10 ¹⁵ -10 ¹⁸ cm ^-3 are ion implanted, and N-type ions with a doping concentration of 10 ¹⁵ -10 ¹⁹ cm ^-3 are ion implanted.

In the step (3), the high-k gate dielectric is any one of Al ₂ O ₃ , SiO ₂ , Si ₃ N ₄ , HfO ₂ , AlN, La ₂ O ₅ , and AlON or a stacked structure thereof; the high-k gate dielectric The layer thickness is 5-80 nm.

The deposition method in the step (3) includes MOCVD, PECVD, ALD, MBE, electron beam evaporation or radio frequency sputtering.

The etching methods in the steps (3) and (5) include fluorine-based RIE etching, ICP etching or DHF wet etching.

In the step (4), the gate metal is at least one of TiN, Ni, and Al.

In the step (4), the deposition method includes electron beam evaporation or magnetron sputtering; the etching method includes reactive ion etching or H ₂ SO ₄ wet etching.

In the step (5), the passivation layer medium is SiO ₂ or Si ₃ N ₄ ; the deposition method includes LPCVD or PECVD.

In the step (5), the thickness of the passivation layer is 100-2000 nm.

In the step (6), a low-temperature ohmic contact metal layer is deposited on the epitaxial layer and the heavily doped substrate, and annealing to form an ohmic contact is as follows: sequentially depositing a carbon layer of 1-50 nm and a nickel layer of 10-500 nm, and realizing ohmic contact by annealing, wherein the deposition The method includes chemical vapor deposition, magnetron sputtering or electron beam evaporation, and the annealing temperature is 700-950°C.

In the step (7), the thickening metal is any one of Ti, Al, Ni or a laminated metal thereof, and the thickness of the thickening metal is 1-10 μm.

The present invention also provides a SiC MOSFET prepared by the above method.

The present invention also provides an application of the SiC MOSFET prepared by the above method.

The invention relates to a method for manufacturing a high-k gate dielectric layer. The high-k gate dielectric layer is deposited on the surface of a clean silicon carbide epitaxial wafer after cleaning by using a physical or chemical vapor deposition method. These growths are low-temperature thin film growth methods (150-500°C), which avoid the high-temperature process in thermal oxidation, so help to reduce the impurity content in the dielectric layer, and at the same time reduce the SiC/SiO ₂ interface by carbon clusters, impurities caused by the interface state. Taking Al ₂ O ₃ as an example, its k value is 9-10 and its forbidden band width is 8.7-8.8 eV. Due to its high k value and forbidden band width, it will withstand lower electric field strength in device applications, thus avoiding premature breakdown of the gate dielectric. The invention relates to a manufacturing method of low-temperature ohmic contact. A carbon/nickel stack structure is deposited on the surface of heavily doped silicon carbide, and ohmic contact can be achieved by performing multiple annealing. In the traditional SiC ohmic contact manufacturing process, the SiC/Ni structure needs to be rapidly annealed at high temperature (~1000°C), and such a high temperature will cause the crystallization of the high-k gate dielectric, resulting in problems such as large leakage current. By introducing carbon into the nickel-based ohmic contact, the invention reduces the Schottky barrier height between the metal semiconductors and realizes the preparation of the ohmic contact under relatively low temperature annealing conditions.

beneficial effect

The present invention prepares silicon carbide MOSFET based on high-k gate dielectric and low-temperature ohmic contact process. Compared with traditional SiC power MOSFET, the present invention has the advantage of using high-k dielectric as gate dielectric, which reduces the density of carbon clusters at the interface and improves channel migration. Rate. The experimental data show that the interface state density of Al-based high-k gate dielectric grown by ALD deposition can reach 10 ¹¹ -10 ¹² cm ^-2 eV ^-1 , which is lower than that of SiO ₂ prepared by thermal oxidation (4× 10 ¹² -10 ¹³ cm ^-2 eV ^-1 ). The mobility can also be increased from 25-30 cm ² /Vs to 30-50 cm ² /Vs.

At the same time, when the device works in the reverse withstand voltage region, due to the high dielectric constant of the high-k dielectric, the electric field concentration effect in the gate dielectric is avoided, thereby preventing the early breakdown of the gate dielectric. In general, the dielectric constant of Al-based high-k dielectrics will increase from 3.9 to 7-10 compared to thermally oxidized SiO ₂ . According to Gauss's law, when SiC reaches the critical breakdown electric field (3MV/cm), the electric field strength in _SiO2 is 8.3MV/cm, while the electric field strength in high-k medium is only 3-4MV/cm, obviously the high-k medium When used as a gate dielectric, it is more difficult to break down, so that the high critical breakdown electric field of SiC can be fully utilized.

Description of drawings

FIG. 1 is a schematic cross-sectional structure diagram of an epitaxial layer of a SiC substrate of the present invention after forming an N+ source region and a P-type channel region.

FIG. 2 is a schematic cross-sectional structure diagram of the device after the deposition of the high-k gate dielectric layer of the present invention.

FIG. 3 is a schematic cross-sectional structure diagram of the device after the gate metal layer is deposited and etched according to the present invention.

FIG. 4 is a schematic cross-sectional structure diagram of the device after the passivation layer deposition of the present invention.

FIG. 5 is a schematic diagram of a cell of a SiC high-k gate dielectric MOSFET device of the present invention.

Detailed ways

The present invention will be further described below in conjunction with specific embodiments. It should be understood that these examples are only used to illustrate the present invention and not to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms also fall within the scope defined by the appended claims of the present application.

The present invention will be described as an embodiment of a specific environment, namely a high-k gate dielectric silicon carbide metal oxide semiconductor field effect transistor (MOSFET). However, embodiments of the present invention can also be applied to various metal oxide semiconductor field effect transistors.

Silicon carbide substrate source: Dongguan Tianyu Semiconductor Technology Co., Ltd. All medicines were used directly in the synthesis process and device preparation process without secondary purification.

Example 1

(1) Clean the SiC substrate with the epitaxial N-type lightly doped SiC layer (thickness 13μm, doping concentration 6×10 ¹³ cm ^-3 ); the cleaning process includes: standard RCA cleaning; high-temperature oxidation of the silicon carbide epitaxial wafer to form The sacrificial oxide layer is then etched until the surface oxide layer is completely removed.

(2) As shown in FIG. 1, three types of implantation regions can be formed in the substrate. The three implanted regions are respectively a P-type implanted region, an N+-type implanted region, and a P+-type implanted region. Specifically, the N+ type implantation region is disposed between the P and P+ type implantation regions. P-type and P+-type implanted regions are formed by implanting aluminum and phosphorus ions. According to an embodiment, P-type ions with a doping concentration of 10 ¹⁵ -10 ¹⁸ cm ^-3 may be implanted. Similarly, N+ type implantation regions are formed by implanting nitrogen ions. According to an embodiment, N-type ions at a doping concentration of 10 ¹⁵ -10 ¹⁹ cm ^-3 may be implanted. The implanted ions are activated by a high temperature process of 1700°C.

(3) A gate dielectric layer is deposited over the substrate, as shown in FIG. 2 . The gate dielectric can be deposited by atomic layer deposition (ALD), the dielectric type chosen in this example is Al ₂ O ₃ . Optionally, the dielectric layer may be SiO ₂ , Si ₃ N ₄ , HfO ₂ , AlN, La ₂ O ₅ , or AlON. According to the embodiment, the optional thickness of the gate dielectric layer is 50 nm, and the thickness of the selected thickness mainly depends on the performance parameters of the device, such as operating voltage, reverse withstand voltage, and the like.

(4) Deposit gate metal on the surface of the high-k gate dielectric layer, and pattern the gate metal and the dielectric by etching; FIG. 3 shows a cross-sectional view of the device after the gate metal is deposited and patterned. According to an embodiment, the gate metal may be formed of TiN, prepared using a suitable deposition technique such as magnetron sputtering, and patterned by etching.

(5) A passivation layer dielectric is deposited on the epitaxial layer, and patterned by etching; FIG. 4 shows a schematic view of the structure after the passivation layer is deposited. According to an example, the passivation layer can be selected from SiO ₂ , and the deposition method can be selected from PECVD. The purpose of this step is to isolate the gate metal in preparation for the next step of depositing the source metal. The thickness of the passivation layer will affect the capacitance properties of the device, and in this embodiment, the thickness is selected to be 600 nm.

(6) Deposit a low-temperature ohmic contact metal layer on the epitaxial layer and the heavily doped substrate, anneal to form an ohmic contact, and thicken the metal; FIG. 5 shows a screenshot of the device after depositing the source-drain metal and the thickened metal. According to the embodiment, the source-drain metal can be realized by annealing a 100 nm carbon-nickel laminated structure, the optional deposition method is magnetron sputtering or electron beam evaporation, and the annealing temperature is 800°C. The optional type of thickening metal is Ti, Al, Ni laminated metal with a thickness of 2.5 μm.

The experimental data show that the interface state density of the Al ₂ O ₃ gate dielectric grown by ALD deposition (the interface state density can be calculated by the conductometric method. The specific implementation process: the capacitance-frequency test of the MOSCAP (MOS capacitor) structure can be obtained. The test condition of capacitance and conductance with frequency relationship is 100k-1MHz. By the formula

and

其中μ_FE是场效应迁移率，L和W是MOSFET的栅长度和宽度，分别取值500和80μm，C_ox是氧化物单位电容,对Al₂O₃而言C_ox＝8.23×10^-11F/m，V_ds是测试条件中的源漏电压)也可以提高至40cm²/Vs，同时高k介质的临界击穿电场强度(通过MOSCAP结构进行漏电测试即可，测试限流100μA)也可达到8MV/cm。Calculate the interface density of states. where G _m and C _m are the test conductance and capacitance values, ω=2πf is the angular frequency, C _ox is the oxide unit capacitance, for Al ₂ O ₃ C _ox =8.23×10 ^-11 F/m, q is the electron The electric quantity is 1.6×10 ^-19 C, τ _it is the time constant, and D _it is the interface state density. ) can reach 10 ¹¹ -10 ¹² cm ^-2 eV ^-1 , the mobility (derived from the test of the transfer characteristic curve of the lateral MOSFET structure, the test conditions V _ds =0.1V, V _g =-5to 20V. The derivation formula

where _μFE is the field-effect mobility, L and W are the gate length and width of the MOSFET, which are 500 and 80 μm, respectively, C _ox is the oxide unit capacitance, and for Al ₂ O ₃ C _ox =8.23×10 ^-11 F/m, V _ds is the source-drain voltage in the test conditions) can also be increased to 40cm ² /Vs, and the critical breakdown electric field strength of high-k dielectrics (the leakage test can be performed through the MOSCAP structure, the test current limit is 100μA) is also Can reach 8MV/cm.

Example 2

The high-k dielectric layer in step (3) in Embodiment 1 can be replaced. In this embodiment, the ALD method is used to grow the La ₂ O ₅ (5nm)/Al ₂ O ₃ (45nm) dielectric layer, and its thickness can be selected as 50nm. Other conditions were not changed, and were the same as in Example 1.

The calculation process is the same as that of Example 1. For the laminated structure, C _ox =5.5×10 ⁻¹¹ F/m, and other experimental data remain unchanged. In this embodiment, the interface state density can reach 7×10 ¹¹ -10 ¹² cm ^-2 eV ^-1 , the mobility is 35 cm ² /Vs, and the critical breakdown electric field strength can reach 8.7MV/cm.

Example 3

The high-k dielectric layer in step (3) in Embodiment 1 can be replaced. In this embodiment, the SiO ₂ (5nm)/AlN (45nm) dielectric layer grown by the CVD method is selected to have a thickness of 50nm. Other conditions were not changed, and were the same as in Example 1.

The calculation process is the same as that of Example 1. For the laminated structure, C _ox =6.2×10 ^-11 F/m, and other experimental data remain unchanged. In this embodiment, the interface state density can reach 7×10 ¹⁰ -4×10 ¹² cm ^-2 eV ^-1 , the mobility is 26 cm ² /Vs, and the critical breakdown electric field can reach 16.8MV/cm.

Comparative Example 1

According to the reference "Advanced processing for mobility improvement in 4H-SiCMOSFETs: A review", the interface state density of SiO ₂ prepared by conventional thermal oxidation is currently 4×10 ¹² -10 ¹³ cm ^-2 eV ^-1 , and the channel mobility is 25-30cm ² /Vs. Compared with the data of the interface state density and mobility of the present invention, there is a certain gap.

Claims (10)

1. A preparation method of a SiC MOSFET based on a high-k gate dielectric and low-temperature ohmic contact process comprises the following steps:

(1) cleaning the SiC substrate of the epitaxial N-type lightly doped SiC layer;

(2) forming an N + source region, a P-type channel region and a P + terminal region on an epitaxial layer of the SiC substrate in an ion implantation and annealing mode;

(3) depositing a high-k gate dielectric layer on the epitaxial layer;

(4) depositing gate metal on the surface of the high-k gate dielectric layer, and patterning the gate metal and the dielectric by etching;

(5) depositing a passivation layer medium on the epitaxial layer, and patterning by etching;

(6) depositing a low-temperature ohmic contact metal layer on the epitaxial layer and the heavily doped substrate, and annealing to form ohmic contact;

(7) the metal is thickened on the epitaxial layer and the heavily doped substrate.

2. The method as claimed in claim 1, wherein the thickness of the SiC substrate in step (1) is 200-400 μm, and the doping concentration is 1 × 10¹⁶-1×10²¹cm^-3The thickness of the epitaxial N-type lightly doped SiC layer is 5-30 μm, and the doping concentration is 1 × 10¹⁴-1×10¹⁷cm^-3。

3. The method according to claim 1, wherein the ions implanted in step (2) are N ions, P ions or Al ions; the annealing temperature is 1500-1900 ℃.

4. The method of claim 1, wherein in step (3), the high-k gate dielectric is Al₂O₃、SiO₂、Si₃N₄、HfO₂、AlN、La₂O₅Or AlON or a laminated structure thereof; the thickness of the high-k gate dielectric layer is 5-80 nm; deposition methods include MOCVD, PECVD, ALD, MBE, electron beam evaporation or radio frequency sputtering.

5. The method according to claim 1, wherein in the step (4), the gate metal is at least one of TiN, Ni and Al; the deposition method comprises electron beam evaporation or magnetron sputtering; the etching method comprises reactive ion etching or H₂SO₄And (5) wet etching.

6. The method of claim 1, wherein the passivation layer dielectric in step (5) is SiO₂Or Si₃N₄(ii) a Deposition methods include LPCVD or PECVD; the etching method comprises fluorine-based RIE etching, ICP etching or DHF wet etching.

7. The method of claim 1, wherein in step (6), a low temperature ohmic contact metal layer is deposited on the epitaxial layer and the heavily doped substrate, and the annealing step is performed to form an ohmic contact as follows: sequentially depositing a carbon layer with the thickness of 1-50nm and a nickel layer with the thickness of 10-500nm, and realizing ohmic contact through annealing, wherein the deposition method comprises chemical vapor deposition, magnetron sputtering or electron beam evaporation, and the annealing temperature is 700-950 ℃.

8. The method according to claim 1, wherein the thickened metal in the step (7) is any one of Ti, Al and Ni or a laminated metal thereof, and the thickness of the thickened metal is 1-10 μm.

9. A SiC MOSFET made by the method of claim 1.

10. Use of a SiC MOSFET made according to the method of claim 1.

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