CN111739934B - Gallium nitride high electron mobility transistor with junction field plate - Google Patents
Gallium nitride high electron mobility transistor with junction field plate Download PDFInfo
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- H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
- H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
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Abstract
本发明提出一种具有结型场板的氮化镓基高电子迁移率晶体管，在传统的氮化镓HEMT器件基础上，在其势垒层上方形成一个纵向的PN结作为耐压结构调制器件的表面电场，优化横向的电场分布，达到了提升击穿电压的目的。一方面，在栅极处于阻断状态时纵向的PN结二极管会辅助耗尽器件沟道的二维电子气，承受一部分漏极电压，减小栅极边缘漏极侧所承受的电压，减小该处峰值电场。在正向导通状态时，PN结耗尽区可以避免栅极产生过大的泄漏电流，保证器件的正向导通电流能力。与常规金属场板相比本发明使用PN结作场板不会引入附加的寄生电容，保证了器件的工作频率和开关速度，在提升击穿电压的同时提高了器件的可靠性。
The invention proposes a GaN-based high electron mobility transistor with a junction field plate. On the basis of a traditional GaN HEMT device, a vertical PN junction is formed above its potential barrier layer as a voltage-resistant structure modulation device The surface electric field is optimized, and the transverse electric field distribution is optimized to achieve the purpose of improving the breakdown voltage. On the one hand, when the gate is in the blocking state, the vertical PN junction diode will assist to deplete the two-dimensional electron gas of the device channel, bear part of the drain voltage, reduce the voltage on the drain side of the gate edge, reduce The peak electric field here. In the forward conduction state, the PN junction depletion region can prevent the gate from generating excessive leakage current and ensure the forward conduction current capability of the device. Compared with the conventional metal field plate, the present invention uses the PN junction as the field plate without introducing additional parasitic capacitance, ensures the operating frequency and switching speed of the device, and improves the reliability of the device while increasing the breakdown voltage.
Description
Technical Field
The invention belongs to the technical field of microelectronic devices, and particularly relates to a gallium nitride-based high electron mobility transistor with a PN junction type field plate, which can effectively improve the breakdown voltage of the device.
Background
A GaN-based heterojunction field effect transistor (GaN HEMT) operates with a high concentration and high electron mobility 2DEG formed in an AlGaN/GaN heterojunction channel. The GaN material has excellent physicochemical properties such as large forbidden band width, high critical breakdown electric field (the critical breakdown electric field is as high as 3.4MV/cm, which is 10 times that of the Si material), good thermal conductivity and radiation resistance, and the like. The gallium nitride-based heterojunction field effect transistor can keep high reliability in high-voltage-resistance and high-power application, and has wide application space in the field of high-speed switches due to high electronic saturation speed and high carrier mobility.
The conventional GaN HEMT is a transverse device, and the structural schematic diagram of the conventional GaN HEMT is shown in fig. 1, and mainly comprises a substrate 210, a GaN buffer layer 201, a gallium nitride channel layer 202, an aluminum gallium nitride barrier layer 203, and a source 204, a gate 205 and a drain 206 which are respectively arranged on the upper surface of the aluminum gallium nitride barrier layer, wherein the source 204 and the drain 206 are in ohmic contact with the aluminum gallium nitride barrier layer 203; the gate 205 forms a schottky contact with the aluminum gallium nitride barrier layer 203; a passivation layer 209 is grown on the surface of the AlGaN barrier layer between the source 204 and the drain 206.
For a normal GaN HEMT, when a voltage is applied at the drain, the channel 2DEG between the gate and the drain cannot be completely depleted, so that there is a phenomenon of electric field concentration near the drain end at the gate edge. The electric field concentration can lead the device to break down in advance and generate a leakage channel when a lower drain voltage is applied, so that the buffer layer is leaked, the advantage of the GaN material cannot be fully exerted, and the application of the gallium nitride-based heterojunction high electron mobility transistor in the aspect of high voltage is limited.
In order to fully exert the high critical breakdown electric field characteristics of the GaN material, researchers have proposed many technical measures for improving the voltage endurance of the device, wherein typical measures mainly include: field plate technology (e.g., gate field plate, source field plate, drain field plate), substrate transfer technology, ion implantation, buffer layer doping, superlattice buffer layer and back barrier technology, etc.
In 2001, Li J et al, in the literature (Li J, Cai S J, Pan G Z, et al. high breakdown voltage GaN HFET with field plate [ J ]. Electronics Letters,2001,37(3): 196) -197.), disclosed for the first time that a field plate shorted to the gate was used, the introduction of the gate field plate could effectively reduce the electric field peak at the gate edge, expand the channel 2DEG depletion region between the gate and the drain, make the electric field distribution between the gate and the drain more uniform, and thus improve the withstand voltage. But an additional capacitance is formed between the field plate and the channel, which degrades the frequency characteristics and switching characteristics of the device.
The proposal of the substrate transfer technology provides more possibilities for the improvement of the breakdown voltage of the GaN device. The traditional Si substrate device has the advantages that the forbidden bandwidth of the substrate is narrow, the withstand voltage of the traditional Si substrate device obviously cannot meet the increasing requirements, and the substrate transfer technology can effectively eliminate the early breakdown caused by insufficient withstand voltage of the Si substrate. In 2010, Bin Liu et al in the literature (Bin Lu, Tom s Palacios. high Breakdown: (B,)>1500V)AlGaN/GaN HEMTs by Substrate-Transfer Technology[J]The reports on the substrate transfer technique in IEEE Electron Device Letters,2010,31(9):951-500V (gate-drain pitch 20 μm) and an on-resistance of only 5.3 m.OMEGA.cm2. The process of the substrate transfer technique has not yet fully matured and its cost is greatly increased relative to Si substrates.
The buffer layer doping technology is also one of the methods for reducing the leakage current and increasing the withstand voltage, and impurities such as the buffer layer doping C, Fe and the like form a deep level trap to trap electrons leaked into the buffer layer, so that the value of the buffer layer leakage current is obviously reduced, and the breakdown voltage of the device is improved. However, the buffer layer doped with deep level acceptor impurities such as C, Fe can cause current collapse, so that the direct current characteristics of the device are degraded.
The AlGaN back barrier buffer layer structure can increase the barrier height from the channel two-dimensional electron gas to the buffer layer, limit the leakage of the channel two-dimensional electron gas to the buffer layer, reduce the leakage current and improve the breakdown voltage. However, the method has limited improvement of breakdown voltage, and on one hand, the AlGaN back barrier can introduce traps between the buffer layer and the channel layer due to the problem of lattice mismatch; on the other hand, the AlGaN barrier layer and the AlGaN back barrier have opposite polarization effects, thereby lowering the two-dimensional electron gas concentration of the channel, so that the on-resistance increases.
In summary, these technical measures introduce various problems while improving the withstand voltage, and how to improve the withstand voltage without affecting other performances of the device becomes a problem to be solved in the current gan-based high electron mobility transistor.
Disclosure of Invention
The invention aims to reduce the electric field peak at the edge of the grid electrode by introducing the junction type field plate structure, modulate the channel electric field to ensure that the distribution is more uniform, reduce the leakage current of the buffer layer and improve the breakdown voltage. The invention provides a gallium nitride-based heterojunction field effect transistor with a junction field plate.
In order to solve the technical problem, the invention adopts the following technical scheme:
a gallium nitride-based high electron mobility transistor with a junction field plate sequentially comprises the following structures from bottom to top: a substrate 210, a GaN buffer layer 201, a gallium nitride channel layer 202, an aluminum gallium nitride barrier layer 203, and a source 204, a passivation layer 209, a gate 205, a P-type doped gallium nitride semiconductor 207, an N-type doped gallium nitride semiconductor 208, and a drain 206, which are respectively disposed above the aluminum gallium nitride barrier layer 203; the source electrode 204 and the drain electrode 206 are in ohmic contact with the AlGaN barrier layer 203; the gate 205 forms a schottky contact with the aluminum gallium nitride barrier layer 203; an N-type semiconductor layer 208 is grown on the surface of the aluminum gallium nitride barrier layer 203 between the grid electrode 205 and the drain electrode 206, a P-type semiconductor layer 207 is grown on the surface of the N-type semiconductor layer 208, and the P-type semiconductor 207 and the N-type semiconductor 208 form a PN junction type field plate; a passivation layer 209 is grown on the surface of the AlGaN barrier layer 203 between the source electrode 204 and the drain electrode 206.
Preferably, the N-type doped semiconductor 208 is positioned above the AlGaN barrier layer 203 between the gate and the drain, and the P-type doped semiconductor 207 is positioned above the N-type doped semiconductor 208 between the gate and the drain; the length of the N-type doped semiconductor 208 does not exceed the distance between the grid and the drain, and the length of the P-type doped semiconductor 207 does not exceed the length of the N-type doped semiconductor 208; the difference between the doping concentrations of the P-type doped semiconductor 207 and the N-type doped semiconductor 208 is 10 to 104。
Preferably, the PN junction field plate composed of the P-type doped semiconductor 207 and the N-type doped semiconductor 208 is repeatedly grown in a plurality of numbers between the gate metal 205 and the drain metal 206, and the sum of the lengths of the plurality of PN junction field plates does not exceed the spacing between the gate and the drain.
Preferably, the P-type doped semiconductor 207 has a slope shape, and the thickness of one end of the slope shape is greater than that of the other end; the length of the P-type doped semiconductor 207 does not exceed the length of the N-type doped semiconductor 208, neither of which exceeds the gap between the gate and the drain, and a passivation layer 209 is grown over the P-type doped semiconductor 207.
Preferably, the middle portion of the P-type doped semiconductor 207 is provided with a protrusion having a thickness and length smaller than those of the N-type doped semiconductor 208, and a passivation layer 209 is grown over the P-type doped semiconductor 207.
Preferably, the width of the P-type doped semiconductor 207 in the xoz plane decreases from the gate 205 to the drain 206, and the width of the N-type doped semiconductor 208 in the xoz plane does not change.
Preferably, the width of the P-type doped semiconductor 207 increases in the xoz plane from the gate 205 to the drain 206, and the width of the N-type doped semiconductor 208 does not change in the xoz plane.
Preferably, the material of the N-type doped semiconductor 208 is selected from any one or a combination of several of GaN, Si, GaAs, GaN, SiC, AlN, AlGaN and InGaN; the material of the P-type doped semiconductor 207 is selected from any one or a combination of several of GaN, Si, GaAs, GaN, SiC, AlN, AlGaN and InGaN; the material of the passivation layer 209 is selected from SiO2、HfO2、Al2O3、Si3N4And La2O3Any one or more of the above-mentioned materials; the material of the substrate 210 is selected from any one of sapphire, Si, and SiC.
The invention has the beneficial effects that: the invention aims to overcome the problems that the voltage resistance of a gallium nitride-based high electron mobility transistor (GaN HEMT) is insufficient and the high critical breakdown electric field and the high electron saturation mobility of a GaN material cannot be fully exerted, and provides a gallium nitride-based high electron mobility transistor with a PN junction type field plate. On one hand, when the grid is in a blocking state, the longitudinal PN junction diode can assist in depleting two-dimensional electron gas of a device channel, bear a part of drain voltage, reduce the voltage borne by the drain side at the edge of the grid, and reduce the peak electric field at the position. In a forward conduction state, the PN junction depletion region can prevent the grid from generating overlarge leakage current, and the forward conduction current capability of the device is ensured. Meanwhile, compared with a conventional metal field plate, the field plate provided by the invention does not introduce additional parasitic capacitance, so that the working frequency and the switching speed of the device are ensured, the breakdown voltage is improved, and the reliability of the device is improved.
Drawings
Fig. 1 is a schematic structural view of a general gallium nitride high electron mobility transistor (GaN HEMT).
Fig. 2 is a schematic structural diagram of a GaN HEMT having a PN junction field plate according to embodiment 1 of the present invention.
Fig. 3 is a schematic structural view of a GaN HEMT having a PN junction field plate according to embodiment 2 of the present invention.
Fig. 4 is a schematic structural diagram of a GaN HEMT having a PN junction field plate according to embodiment 3 of the present invention.
Fig. 5 is a schematic structural view of a GaN HEMT having a PN junction field plate according to embodiment 4 of the present invention.
Fig. 6 is a schematic structural view of a GaN HEMT having a PN junction field plate according to embodiment 5 of the present invention.
Fig. 7 is a comparison of the breakdown characteristics of the inventive example 1 and a general GaN HEMT.
Fig. 8 is a comparison of the channel electric field of the embodiment 1 of the present invention and a general GaN HEMT.
210 is a substrate, 201 is a GaN buffer layer, 202 is a gallium nitride channel layer, 203 is an aluminum gallium nitride barrier layer, 204 is a source, 205 is a gate, 206 is a drain, 207 is a P-type semiconductor layer, 208 is an N-type semiconductor layer, and 209 is a passivation layer.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited to these examples.
Fig. 1 is a schematic structural view of a general gallium nitride high electron mobility transistor (GaN HEMT), which sequentially includes, from bottom to top: the substrate 210, the GaN buffer layer 201, the gallium nitride channel layer 202, the aluminum gallium nitride barrier layer 203, and the source electrode 204, the gate electrode 205, the drain electrode 206 and the passivation layer 209 formed above the aluminum gallium nitride barrier layer, wherein the source electrode 204 and the drain electrode 206 respectively form ohmic contact with the aluminum gallium nitride barrier layer 203, and the gate electrode 205 forms schottky contact with the aluminum gallium nitride barrier layer 203.
Example 1
The present embodiment provides a gallium nitride-based high electron mobility transistor, as shown in fig. 2, the structure of which sequentially includes, from bottom to top: a substrate 210, a GaN buffer layer 201, a gallium nitride channel layer 202, an aluminum gallium nitride barrier layer 203, and a source 204, a passivation layer 209, a gate 205, a P-type doped gallium nitride semiconductor 207, an N-type doped gallium nitride semiconductor 208, and a drain 206, which are respectively disposed above the aluminum gallium nitride barrier layer 203; the source electrode 204 and the drain electrode 206 are in ohmic contact with the AlGaN barrier layer 203; the gate 205 forms a schottky contact with the aluminum gallium nitride barrier layer 203; an N-type semiconductor layer 208 is grown on the surface of the aluminum gallium nitride barrier layer 203 between the grid electrode 205 and the drain electrode 206, a P-type semiconductor layer 207 is grown on the surface of the N-type semiconductor layer 208, and the P-type semiconductor 207 and the N-type semiconductor 208 form a PN junction type field plate; a passivation layer 209 is grown on the surface of the AlGaN barrier layer 203 between the source electrode 204 and the drain electrode 206.
An N-type doped semiconductor 208 is positioned above the AlGaN barrier layer 203 between the grid and the drain, and a P-type doped semiconductor 207 is positioned above the N-type doped semiconductor 208 between the grid and the drain; the length of the N-type doped semiconductor 208 does not exceed the distance between the grid and the drain, and the length of the P-type doped semiconductor 207 does not exceed the length of the N-type doped semiconductor 208; the difference between the doping concentrations of the P-type doped semiconductor 207 and the N-type doped semiconductor 208 is 10 to 104。
Table 1 shows simulation structure parameters of a general HEMT and embodiment 1 of the present invention:
TABLE 1 comparison of device simulation parameters and results
| Device parameters | Common HEMT | PN junction type field plate HEMT |
| Doping concentration of P-type semiconductor | -- | 3×1018cm-3 |
| Doping concentration of N-type semiconductor | -- | 3×1016cm-3 |
| Thickness of P-type semiconductor | -- | 0.1μm |
| Thickness of N-type semiconductor | -- | 0.1μm |
| Length of P-type semiconductor | -- | 3μm |
| Length of N-type semiconductor | -- | 3μm |
| Thickness of source-gate passivation layer | 0.2μm | 0.2μm |
| Source gate passivation layer length | 1μm | 1μm |
| Thickness of passivation layer at drain | 0.2μm | 0.2μm |
| Length of passivation layer at drain | 2μm | 2μm |
| Gate source spacing | 1μm | 1μm |
| Gate to drain spacing | 5μm | 5μm |
| Length of grid | 0.5μm | 0.5μm |
| AlGaN barrier layer thickness | 20nm | 20nm |
| Al composition of AlGaN barrier layer | 0.28 | 0.28 |
| GaN channel layer thickness | 30nm | 30nm |
| Thickness of GaN buffer layer | 1μm | 1μm |
| Breakdown Voltage (@ I)DS＝1μA/mm) | 760V | 425V |
Fig. 7 and 8 are comparison results of simulation results of this example 1 and a conventional HEMT, which fully show the advantage of the invention of improving the breakdown voltage. As can be seen from the simulation result fig. 7, the breakdown voltage of the general HEMT device is 425V (breakdown current criterion is 1 μ a/mm), while the breakdown voltage of the embodiment 1 of the present invention is 760V (breakdown current criterion is 1 μ a/mm). Fig. 8 is a comparison graph of channel electric field intensity distribution, and it is apparent from fig. 8 that embodiment 1 can significantly reduce the electric field peak at the edge of the gate, so that the channel electric field distribution is more uniform, thereby improving the breakdown voltage of the device.
Example 2
As shown in fig. 3, the present embodiment is different from embodiment 1 in that: between the gate metal 205 and the drain metal 206 are 3P-doped semiconductor 207 and N-doped semiconductor 208 PN junction field plates with a passivation layer 209 between them. The sum of the lengths of the plurality of PN junction field plates does not exceed the spacing between the gate and the drain.
Example 3
As shown in fig. 4, the present embodiment is different from embodiment 1 in that the P-type doped semiconductor 207 has a slope shape, and the thickness of one end of the slope shape is greater than that of the other end; the length of the P-type doped semiconductor 207 does not exceed the length of the N-type doped semiconductor 208, neither of which exceeds the gap between the gate and the drain, and a passivation layer 209 is grown over the P-type doped semiconductor 207.
Example 4
As shown in fig. 5, the present embodiment is different from embodiment 1 in that a protrusion is provided at the middle portion of a P-type doped semiconductor 207, the thickness and length of the protrusion portion are smaller than those of an N-type doped semiconductor 208, and a passivation layer 209 is grown over the P-type doped semiconductor 207.
Example 5
As shown in fig. 6, the present embodiment is different from embodiment 1 in that the width of the P-type doped semiconductor 207 in the xoz plane is sequentially reduced from the gate 205 to the drain 206, and the width of the N-type doped semiconductor 208 in the xoz plane is unchanged.
Example 6
The present embodiment is different from embodiment 1 in that the width of the P-type doped semiconductor 207 in the xoz plane increases in order from the gate 205 to the drain 206, and the width of the N-type doped semiconductor 208 in the xoz plane does not change.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and any simple modifications and equivalent variations of the above embodiments according to the technical spirit of the present invention are within the scope of the present invention.
Claims (8)
1. A gallium nitride-based high electron mobility transistor having a junction field plate, comprising: its structure includes from bottom to top in proper order: the GaN-based light-emitting diode comprises a substrate (210), a GaN buffer layer (201), a gallium nitride channel layer (202), an aluminum gallium nitride barrier layer (203), and a source electrode (204), a passivation layer (209), a gate electrode (205), a P-type doped gallium nitride semiconductor (207), an N-type doped gallium nitride semiconductor (208) and a drain electrode (206) which are respectively arranged above the aluminum gallium nitride barrier layer (203); the source (204) and the drain (206) both form ohmic contacts with the AlGaN barrier layer (203); the gate (205) forms a Schottky contact with the AlGaN barrier layer (203); an N-type doped gallium nitride semiconductor (208) is grown on the surface of the aluminum gallium nitride barrier layer (203) between the grid electrode (205) and the drain electrode (206), a P-type doped gallium nitride semiconductor (207) is grown on the upper surface of the N-type doped gallium nitride semiconductor (208), and the P-type doped gallium nitride semiconductor (207) and the N-type doped gallium nitride semiconductor (208) form a PN junction type field plate; a passivation layer (209) is grown on the surface of the AlGaN barrier layer (203) between the source electrode (204) and the drain electrode (206).
2. The gallium nitride-based high electron mobility transistor with a junction field plate according to claim 1, wherein: an N-type doped gallium nitride semiconductor (208) is positioned above the aluminum gallium nitride barrier layer (203) between the grid electrode and the drain electrode, and a P-type doped gallium nitride semiconductor (207) is positioned above the N-type doped gallium nitride semiconductor (208) between the grid electrode and the drain electrode; the length of the N-type doped gallium nitride semiconductor (208) does not exceed the distance between the grid and the drain, and the length of the P-type doped gallium nitride semiconductor (207) does not exceed the length of the N-type doped gallium nitride semiconductor (208); the P-type GaN semiconductor (207) and the N-type N-dopedThe difference between the doping concentrations of the gallium nitride semiconductor (208) is 10 to 104cm-3。
3. The gallium nitride-based high electron mobility transistor with a junction field plate according to claim 1, wherein: a PN junction type field plate formed by the P type doped gallium nitride semiconductor (207) and the N type doped gallium nitride semiconductor (208) grows repeatedly between the grid electrode (205) and the drain electrode (206), and the sum of the lengths of the PN junction type field plates does not exceed the distance between the grid electrode and the drain electrode.
4. The gallium nitride-based high electron mobility transistor with a junction field plate according to claim 1, wherein: the P-type doped gallium nitride semiconductor (207) is in a slope shape, and the thickness of one end of the slope shape is larger than that of the other end of the slope shape; the length of the P-type doped gallium nitride semiconductor (207) does not exceed the length of the N-type doped gallium nitride semiconductor (208), and neither of the P-type doped gallium nitride semiconductor and the N-type doped gallium nitride semiconductor exceeds the distance between the grid electrode and the drain electrode, and a passivation layer (209) is grown above the P-type doped gallium nitride semiconductor (207).
5. The gallium nitride-based high electron mobility transistor with a junction field plate according to claim 1, wherein: the middle part of the P-type doped gallium nitride semiconductor (207) is provided with a bulge, the thickness and the length of the bulge part are smaller than those of the N-type doped gallium nitride semiconductor (208), and a passivation layer (209) grows above the P-type doped gallium nitride semiconductor (207).
6. The gallium nitride-based high electron mobility transistor with a junction field plate according to claim 1, wherein: the width of the P-type doped gallium nitride semiconductor (207) on the xoz plane is reduced from the gate (205) to the drain (206), and the width of the N-type doped gallium nitride semiconductor (208) on the xoz plane is unchanged.
7. The gallium nitride-based high electron mobility transistor with a junction field plate according to claim 1, wherein: the width of the P-type doped gallium nitride semiconductor (207) on the xoz plane increases from the gate (205) to the drain (206), and the width of the N-type doped gallium nitride semiconductor (208) on the xoz plane does not change.
8. The gallium nitride-based high electron mobility transistor with a junction field plate according to any one of claims 1 to 7, wherein: the N-type doped gallium nitride semiconductor (208) material is replaced by any one or a combination of more of Si, GaAs, SiC, AlN, AlGaN and InGaN; the material of the P-type doped gallium nitride semiconductor (207) is replaced by any one or a combination of more of Si, GaAs, SiC, AlN, AlGaN and InGaN; the material of the passivation layer (209) is selected from SiO2、HfO2、Al2O3、Si3N4And La2O3Any one or more of the above-mentioned materials; the material of the substrate (210) is selected from any one of sapphire, Si and SiC.
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