CN111726104B - Decision feedback equalizer - Google Patents

Abstract

The present invention discloses a decision feedback equalizer, which has a first path and a second path. The first path includes a first sampling circuit and a first latch circuit, wherein the first sampling circuit is used to generate a first setting signal and a first reset signal according to an input signal, a second setting signal and a second reset signal, and the first latch circuit is used to generate a first digital signal according to the output of the first sampling circuit. The second path includes a second sampling circuit and a second latch circuit, wherein the second sampling circuit is used to generate the second setting signal and the second reset signal according to the input signal, the first setting signal and the first reset signal, and the second latch circuit is used to generate a second digital signal according to the output of the second sampling circuit.

Description

Decision Feedback Equalizer

Technical Field

The present invention relates to a decision feedback equalizer.

Background Art

The decision feedback equalizer (DFE) is a technology commonly used at the receiving end of high-speed wired transmission systems to compensate for channel loss or channel reflection caused by various transmission processes. Its main operating principle is to eliminate the inter-symbol interference (ISI) that is known to affect the next signal through the currently received digital signal and a set of tap coefficients obtained through an adaptive algorithm. In the analog circuit of a high-speed decision feedback equalizer, the most difficult part to implement is the feedback of the first tap, because in principle, the feedback signal must be prepared before the next data arrives after the delay of the sampler, the transmission delay of the feedback path, and the summer delay. Especially at higher speeds, the timing constraints will be tighter.

In order to solve this problem, some patent technologies (e.g., U.S. Patents US7869498 and US8477833) and papers have proposed related decision feedback equalization circuit architectures. However, these technologies have the problem of temperature drift in the design of connector parameters, so background calibration must be relied upon to adjust the connector parameters, thereby increasing the instability and complexity of the circuit.

Summary of the invention

Therefore, one of the objectives of the present invention is to propose a decision feedback equalizer, which has the advantages of high speed, low temperature effect, low power consumption, no need for background correction to adjust connector parameters, etc., so as to solve the problems in the prior art.

In one embodiment of the present invention, a decision feedback equalizer is disclosed, which has a first path and a second path. The first path includes a first sampling circuit and a first latch circuit, wherein the first sampling circuit is used to generate a first setting signal and a first reset signal according to an input signal, a second setting signal and a second reset signal, and the first latch circuit is used to generate a first digital signal according to the first setting signal and the first reset signal. The second path includes a second sampling circuit and a second latch circuit, wherein the second sampling circuit is used to generate the second setting signal and the second reset signal according to the input signal, the first setting signal and the first reset signal, and the second latch circuit is used to generate a second digital signal according to the second setting signal and the second reset signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a decision feedback equalizer according to an embodiment of the present invention.

FIG. 2 is a timing diagram of multiple signals in a decision feedback equalizer.

FIG. 3 is a circuit structure diagram of a first path and a second path according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of a sampling circuit according to a first embodiment of the present invention.

FIG. 5 is a timing diagram of multiple signals of the sampling circuit of FIG. 4 .

FIG. 6 is a schematic diagram of a sampling circuit according to a second embodiment of the present invention.

FIG. 7 is a timing diagram of multiple signals of the sampling circuit of FIG. 6 .

Explanation of symbols

100 Decision Feedback Equalizer

102, 112, 122 summing circuit

108 Multiplexer

110 First Path

114, 124, 314, 324 sampling circuit

120 Second Path

316, 326 Latch Circuit

410, 610 Sense Amplifier

412, 414, 612, 614 Inverters

420, 620 adjustment circuit

CK, CKB clock signals

D_odd The first digital signal

D_even Second digital signal

Dout output digital signal

M1～M13 transistor

S_odd First setting signal

S_even Second setting signal

R_odd First reset signal

R_even Second reset signal

Vin Input Signal

Vin’, Vin’+, Vin’- Adjusted input signal

VFB1_even, VFB1_odd, VFB2 feedback signals

Vh1 voltage

VCM Common Mode Voltage

DETAILED DESCRIPTION

FIG1 is a schematic diagram of a decision feedback equalizer 100 according to an embodiment of the present invention. As shown in FIG1 , the decision feedback equalizer 100 includes a summing circuit 102, a first path 110, a second path 120, and a multiplexer 108, wherein the first path 110 includes a summing circuit 112 and a sampling circuit 114, and the second path 120 includes a summing circuit 122 and a sampling circuit 124.

The decision feedback equalizer 100 shown in FIG1 adopts two paths and half-rate multiplexing switching to achieve the purpose of reducing operation delay. Specifically, referring to the timing diagram shown in FIG2, in the operation of the decision feedback equalizer 100, the summing circuit 102 subtracts a feedback signal VFB2 from the input signal Vin to generate an adjusted input signal Vin', then the summing circuit 112 in the first path 110 subtracts a feedback signal VFB1_even from the adjusted input signal Vin', and samples it through the sampling circuit 114 using a clock signal CK to generate a first digital signal D_odd; and the summing circuit 122 in the second path 120 subtracts a feedback signal VFB1_odd from the adjusted input signal Vin', and samples it through the sampling circuit 124 using a clock signal CKB to generate a second digital signal D_even. Afterwards, the multiplexer 108 outputs the first digital signal D_odd and the second digital signal D_even in an alternating manner under the control of the clock signal CKB, so as to serve as the output digital signal Dout of the decision feedback equalizer 100. For example, assuming that the input signal Vin includes bits A, B, C, D, and E in sequence, and the frequencies of the clock signals CK and CKB are respectively half of the frequency of the input signal Vin, then the first digital signal D_odd generated by the sampling circuit 114 includes A, C, and E, and the second digital signal D_even generated by the sampling circuit 124 includes B and D, that is, the first digital signal D_odd is the odd bit of the output digital signal Dout, and the second digital signal D_even is the even bit of the output digital signal Dout.

In FIG1 , the feedback signal VFB2 is generated by adjusting the output digital signal Dout according to the connector parameter h2, the feedback signal VFB1_even is generated by adjusting the second digital signal D_even according to the connector parameter h1, and the feedback signal VFB1_odd is generated by adjusting the first digital signal D_odd according to the connector parameter h1. As described in the prior art, in a high-speed decision feedback equalizer, the most difficult part to implement is the feedback of the first connector (that is, the related operations of the feedback signal VFB1_even and the feedback signal VFB1_odd). Therefore, in order to reduce the feedback delay, the present invention embeds the feedback function in the sampling circuit, and its specific implementation is described as follows.

FIG3 is a circuit diagram of the first path 110 and the second path 120 according to an embodiment of the present invention. In FIG3, the first path 110 includes a sampling circuit 314 and a latch circuit (SR latch) 316, wherein the sampling circuit 314 is a sampling circuit with built-in feedback function, that is, the sampling circuit 314 includes the summing circuit 112, the joint parameter h1, and part of the functions of the sampling circuit 114 shown in FIG1; similarly, the second path 120 includes a sampling circuit 324 and a latch circuit 326, wherein the sampling circuit 324 is a sampling circuit with built-in feedback function, that is, the sampling circuit 324 includes the summing circuit 122, the joint parameter h1, and part of the functions of the sampling circuit 124 shown in FIG1. In the embodiment shown in FIG3 , the sampling circuit 314 generates a first setting signal S_odd and a first reset signal R_odd according to the adjusted input signal Vin’, a second setting signal S_even and a second reset signal R_even, and the latch circuit 316 generates the first digital signal D_odd according to the first setting signal S_odd and the first reset signal R_odd; similarly, the sampling circuit 324 generates the second setting signal S_even and the second reset signal R_even according to the adjusted input signal Vin’, the first setting signal S_odd and the first reset signal R_odd, and the latch circuit 326 generates the second digital signal D_even according to the second setting signal S_even and the second reset signal R_even. In FIG3 , the first setting signal S_odd and the first reset signal R_odd may correspond to the feedback signal VFB1_odd shown in FIG1 , and the second setting signal S_even and the second reset signal R_even may correspond to the feedback signal VFB1_even shown in FIG1 .

FIG4 is a schematic diagram of a sampling circuit 314 according to a first embodiment of the present invention. As shown in FIG4 , the sampling circuit 314 includes a sense amplifier 410 and an adjustment circuit 420, wherein the sense amplifier 410 includes transistors M1 and M2 for receiving an adjusted input signal Vin’ (including differential signals Vin’+, Vin’-), a transistor M3 as a sense amplifier switch, a plurality of transistors M4-M9 coupled to a supply voltage VDD, and two inverters 412 and 414; the adjustment circuit 420 includes two transistors M10 and M11 as a first differential amplifier, two transistors M12 and M13 as a second differential amplifier, and two switches SW1 and SW2. In this embodiment, transistors M1 and M2 are used to receive the adjusted input signal Vin' to generate amplified input signals at terminals N1 and N2, and the drains of transistors M4 and M5 are used to output signals S' and R', wherein the signals S' and R' are respectively operated by inverters 412 and 414 to generate a first setting signal S_odd and a first reset signal R_odd. The drains of the transistors of the first differential amplifier are directly connected to the terminals of the sense amplifier, and the drains of the transistors of the second differential amplifier are directly connected to the terminals of the sense amplifier. In addition, in the adjustment circuit 420, the first differential amplifier (i.e., transistors M10 and M11) is connected to the transistor M3 as a sensing amplifier switch through the switch SW1, wherein the switch SW1 is controlled by the second setting signal S_even, that is, the first differential amplifier is selectively enabled according to the second setting signal S_even to generate a first adjustment signal to the terminals N1 and N2 according to a differential voltage signal (VCM+Vh1, VCM-Vh1) to adjust the voltage level of the amplified input signal (i.e., the voltage Vh1 is added or subtracted from the terminals N1 and N2 to the corresponding voltage level of the input signal). ); in addition, the second differential amplifier (i.e., transistors M12 and M13) is connected to transistor M3 as a sensing amplifier switch through switch SW2, wherein switch SW2 is controlled by a second reset signal R_even, i.e., the second differential amplifier is selectively enabled according to the second reset signal R_even to generate a second adjustment signal to terminals N1 and N2 according to a differential voltage signal (VCM+Vh1, VCM-Vh1) to adjust the voltage level of the amplified input signal (i.e., adding or subtracting the component corresponding to voltage Vh1 at terminals N1 and N2). The source of the transistor of the first differential amplifier is connected to the sensing amplifier switch through a first switch, and the source of the transistor of the second differential amplifier is connected to the sensing amplifier switch through a second switch, wherein the first switch and the second switch are controlled by the second setting signal and the second reset signal, respectively.

The architecture of the sampling circuit 324 is similar to the sampling circuit 314 shown in FIG. 4 , except that the output of the sampling circuit 324 needs to be changed from the first setting signal S_odd and the first reset signal R_odd to the second setting signal S_even and the second reset signal R_even, and the switches SW1 and SW2 are respectively changed to be controlled by the first setting signal S_odd and the first reset signal R_odd. Since those skilled in the art should be able to understand how to implement the sampling circuit 324 after reading the above embodiments, the relevant details are not repeated here.

As described in the circuit architectures of FIG. 3 and FIG. 4 , since the first setting signal S_odd and the first reset signal R_odd generated by the sampling circuit 314 can be immediately used by the sampling circuit 324 to quickly adjust the output of the sampling circuit 324, and similarly, the second setting signal S_even and the second reset signal R_even generated by the sampling circuit 324 can also be immediately used by the sampling circuit 314 to quickly adjust the output of the sampling circuit 314, and the delay in the overall circuit is almost only the amplification time of the sense amplifier 410 and the delay time of the inverters 412 and 414, the feedback delay problem in the traditional architecture can be effectively reduced. 5 is used to illustrate that after the sampling circuit 324 generates the second setting signal S_even and the second reset signal R_even to determine the bit B, the second setting signal S_even and the second reset signal R_even can be quickly input to the adjustment circuit 420 in the sampling circuit 314 of FIG. 4 so that the sampling circuit 314 can generate the first setting signal S_odd and the first reset signal R_odd to determine the bit C.

In this example, the common mode voltage VCM of the differential signal received by the first differential amplifier (i.e., transistors M10, M11) and the second differential amplifier (i.e., transistors M12, M13) in the adjustment circuit 420 is the same as the common mode voltage of the adjusted input signal Vin' (including the differential signals Vin'+, Vin'-). Therefore, the sensing amplifier 410 and the adjustment circuit 420 will have the same/similar changes under the process, temperature, and voltage variations, that is, the adjustment signal generated by the adjustment circuit 420 can actually reflect the voltage Vh1 and will not change with the temperature. On the other hand, since the voltage Vh1 will not change with the temperature, the adaptive algorithm of the connector parameter h1 can only be started when the electronic device is turned on without the need for background execution, which indirectly reduces the system complexity.

FIG6 is a schematic diagram of a sampling circuit 314 according to a second embodiment of the present invention. As shown in FIG6 , the sampling circuit 314 includes a sense amplifier 610 and an adjustment circuit 620, wherein the sense amplifier 610 includes transistors M1 and M2 for receiving an adjusted input signal Vin’ (including differential signals Vin’+, Vin’-), a transistor M3 as a sense amplifier switch, a plurality of transistors M4-M9 coupled to a supply voltage VDD, and two inverters 612 and 614; the adjustment circuit 620 includes two transistors M10 and M11 as a first differential amplifier, two transistors M12 and M13 as a second differential amplifier, and two switches SW1 and SW2. In this embodiment, transistors M1 and M2 are used to receive the adjusted input signal Vin’ to generate amplified input signals at terminals N1 and N2, and the drains of transistors M4 and M5 are used to output signals S’ and R’, wherein the signals S’ and R’ are respectively operated by inverters 612 and 614 to generate a first setting signal S_odd and a first reset signal R_odd. In addition, in the adjustment circuit 620, the first differential amplifier (i.e., transistors M10 and M11) is connected to the ground voltage through the switch SW1, wherein the switch SW1 is controlled by the second setting signal S_even and the clock signal CK (e.g., the output of the AND gate after receiving the second setting signal S_even and the clock signal CK), that is, the first differential amplifier is selectively enabled according to the second setting signal S_even and the clock signal to generate a first adjustment signal to the terminals N1 and N2 according to a differential voltage signal (VCM+Vh1, VCM-Vh1) to adjust the voltage level of the amplified input signal (i.e., the component corresponding to the voltage Vh1 is added or subtracted from the terminals N1 and N2); in addition, the second differential amplifier (i.e., transistors M12 and M13) is connected to the ground voltage through the switch SW2, wherein the switch SW2 is controlled by the second reset signal R_even and the clock signal CK (e.g., the output of the AND gate after receiving the second setting signal S_even and the clock signal CK). The first differential amplifier is controlled by the output of the first differential amplifier gate after receiving the second reset signal R_even and the clock signal CK, that is, the second differential amplifier is selectively enabled according to the second reset signal R_even to generate a second adjustment signal to the terminals N1 and N2 according to a differential voltage signal (VCM+Vh1, VCM-Vh1) to adjust the voltage level of the amplified input signal (that is, the component corresponding to the voltage Vh1 is added or subtracted from the terminals N1 and N2). The source of the transistor of the first differential amplifier is connected to a reference voltage through a first switch, and the source of the transistor of the second differential amplifier is connected to the reference voltage through a second switch, wherein the first switch is controlled by the second setting signal and the clock signal at the same time, and the second switch is controlled by the second reset signal and the clock signal at the same time.

The architecture of the sampling circuit 324 is similar to the sampling circuit 314 shown in FIG. 6 , except that the output of the sampling circuit 324 needs to be changed from the first setting signal S_odd and the first reset signal R_odd to the second setting signal S_even and the second reset signal R_even, and the switches SW1 and SW2 are respectively changed to be controlled by the first setting signal S_odd and the first reset signal R_odd. Since those skilled in the art should be able to understand how to implement the sampling circuit 324 after reading the above embodiments, the relevant details are not repeated here.

As described in the circuit architectures of FIG. 3 and FIG. 6 , since the first setting signal S_odd and the first reset signal R_odd generated by the sampling circuit 314 can be immediately used by the sampling circuit 324 to quickly adjust the output of the sampling circuit 324, and similarly, the second setting signal S_even and the second reset signal R_even generated by the sampling circuit 324 can also be immediately used by the sampling circuit 314 to quickly adjust the output of the sampling circuit 314, and the delay in the overall circuit is almost only the amplification time of the sense amplifier 410 and the delay time of the inverters 412 and 414, the feedback delay problem in the traditional architecture can be effectively reduced. 7 , after the sampling circuit 324 generates the second setting signal S_even and the second reset signal R_even to determine the bit B, the second setting signal S_even and the second reset signal R_even can be quickly input to the adjustment circuit 420 in the sampling circuit 314 of FIG. 4 , so that the sampling circuit 314 can generate the first setting signal S_odd and the first reset signal R_odd to determine the bit C.

In this example, the common mode voltage VCM of the differential signal received by the first differential amplifier (i.e., transistors M10, M11) and the second differential amplifier (i.e., transistors M12, M13) in the adjustment circuit 620 is the same as the common mode voltage of the adjusted input signal Vin' (including the differential signals Vin'+, Vin'-). Therefore, the sensing amplifier 610 and the adjustment circuit 620 will have the same/similar changes under the variation of process, temperature, and voltage, that is, the adjustment signal generated by the adjustment circuit 620 can actually reflect the voltage Vh1 and will not change with the temperature. On the other hand, since the voltage Vh1 will not change with the temperature, the adaptive algorithm of the connector parameter h1 can only be started when the electronic device is turned on without the need for background execution, which indirectly reduces the system complexity.

The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims (9)

1. A decision feedback equalizer comprising:

a first path comprising:

a first sampling circuit for generating a first setting signal and a first resetting signal according to an input signal, a second setting signal and a second resetting signal; and

A first latch circuit coupled to the sampling circuit for generating a first digital signal of odd bits as an output digital signal of the decision feedback equalizer according to the first set signal and the first reset signal; and

A second path comprising:

a second sampling circuit for generating the second setting signal and the second resetting signal according to the input signal, the first setting signal and the first resetting signal; and

A second latch circuit coupled to the second sampling circuit for generating a second digital signal as even bits of the output digital signal of the decision feedback equalizer according to the second setting signal and the second resetting signal;

wherein the first sampling circuit comprises:

A sense amplifier for receiving the input signal and generating an amplified input signal at an end; and

An adjusting circuit coupled to the end point of the sense amplifier for generating an adjusting signal to the end point according to the second setting signal and the second resetting signal to adjust the voltage level of the amplified input signal;

Wherein the first setting signal and the first reset signal are generated according to the amplified input signal.

2. The decision feedback equalizer of claim 1 wherein the adjustment circuit comprises:

A first differential amplifier for selectively enabling according to the second setting signal to generate a first adjustment signal to the endpoint according to a first differential voltage signal to adjust the voltage level of the amplified input signal; and

A second differential amplifier selectively enabled according to the second reset signal to generate a second adjustment signal to the terminal according to a second differential voltage signal to adjust the voltage level of the amplified input signal.

3. The decision feedback equalizer of claim 2, wherein the input signal is a differential input signal and the differential input signal, the first differential voltage signal and the second differential voltage signal have the same common mode voltage.

4. The decision feedback equalizer of claim 2, wherein the sense amplifier comprises a sense amplifier switch controlled by a clock signal to determine whether to enable or not, the source of the transistor of the first differential amplifier is connected to the sense amplifier switch through a first switch, and the source of the transistor of the second differential amplifier is connected to the sense amplifier switch through a second switch, wherein the first switch and the second switch are controlled by the second set signal and the second reset signal, respectively.

5. The decision feedback equalizer of claim 4 wherein the drain of the transistor of the first differential amplifier is directly connected to the end point of the sense amplifier and the drain of the transistor of the second differential amplifier is directly connected to the end point of the sense amplifier.

6. The decision feedback equalizer of claim 1 wherein the adjustment circuit comprises:

A first differential amplifier for selectively enabling according to the second setting signal and a clock signal to generate a first adjustment signal to the endpoint according to a first differential voltage signal to adjust the voltage level of the amplified input signal; and

The second differential amplifier is selectively enabled according to the second reset signal and the clock signal to generate a second adjustment signal to the endpoint according to a second differential voltage signal so as to adjust the voltage level of the amplified input signal.

7. The decision feedback equalizer of claim 6 wherein the input signal is a differential input signal and the differential input signal, the first differential voltage signal and the second differential voltage signal have the same common mode voltage.

8. The decision feedback equalizer of claim 6 wherein the sense amplifier comprises a sense amplifying switch controlled by a clock signal to determine whether to enable, the source of the transistor of the first differential amplifier being connected to a reference voltage through a first switch and the source of the transistor of the second differential amplifier being connected to the reference voltage through a second switch, wherein the first switch is controlled by the second set signal and the clock signal at the same time, and the second switch is controlled by the second reset signal and the clock signal at the same time.

9. The decision feedback equalizer of claim 8 wherein the drain of the transistor of the first differential amplifier is directly connected to the endpoint of the sense amplifier and the drain of the transistor of the second differential amplifier is directly connected to the endpoint of the sense amplifier.