CN111726104A - Decision Feedback Equalizer - Google Patents

Abstract

The invention discloses a decision feedback equalizer, which is provided with a first path and a second path. The first path includes a first sampling circuit for generating a first set signal and a first reset signal according to an input signal, a second set signal and a second reset signal, and a first latch circuit for generating a first digital signal according to an output of the first sampling circuit. The second path includes a second sampling circuit and a second latch circuit, wherein the second sampling circuit is used for generating the second setting signal and the second reset signal according to the input signal, the first setting signal and the first reset signal, and the second latch circuit is used for generating a second digital signal according to the output of the second sampling circuit.

Description

Decision Feedback Equalizer

technical field

The present invention relates to decision feedback equalizers.

Background technique

Decision feedback equalizer (DFE) is a technology that is often used at the receiving end of high-speed wired transmission systems to compensate for the channel loss or channel reflection (channel loss) of the transmission signal due to various transmission processes. channel reflection), its main operating principle is to eliminate the code that is known to affect the following signal through a set of tapcoefficients obtained by the digital signal that has been received so far and through an adaptation algorithm (adaptation). Inter-symbol Interference (ISI). In the analog circuit of the high-speed decision feedback equalizer, the most difficult part to realize is the feedback of the first tap, because in principle, the feedback signal passes through the delay of the sampler, the propagation delay of the feedback path, and the addition of the feedback signal. The total device (summer) delay must be prepared before the next data arrives, especially at higher speeds, the timing constraints will be tighter.

In order to solve this problem, some patented technologies (for example, US patents US7869498 and US8477833) and papers have proposed related decision feedback equalization circuit architectures. However, these technologies have the problem of temperature drift in the design of joint parameters, so they must rely on Background calibration is used to adjust the connector parameters, thus increasing the instability and complexity of the circuit.

SUMMARY OF THE INVENTION

Therefore, one of the objectives of the present invention is to propose a decision feedback equalizer, which has the advantages of high speed, low temperature effect, low power consumption, no need for background correction to adjust joint parameters, etc., so as to solve the problems in the prior art .

In one embodiment of the present invention, a decision feedback equalizer is disclosed, which has a first path and a second path. The first path includes a first sampling circuit and a first latch circuit, wherein the first sampling circuit is used for generating a first sampling circuit according to an input signal, a second setting signal and a second reset signal The setting signal and a first reset signal, and the first latch circuit is used for generating a first digital signal according to the first setting signal and the first reset signal. The second path includes a second sampling circuit and a second latch circuit, wherein the second sampling circuit is used for generating the second sampling circuit according to the input signal, the first setting signal and the first reset signal The setting signal and the second reset signal, and the second latch circuit is used for generating a second digital signal according to the second setting signal and the second reset signal.

Description of drawings

FIG. 1 is a schematic diagram of a decision feedback equalizer according to an embodiment of the present invention.

FIG. 2 is a timing diagram of multiple signals within a decision feedback equalizer.

FIG. 3 is a circuit structure diagram of a first path and a second path according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of a sampling circuit according to a first embodiment of the present invention.

FIG. 5 is a timing diagram of a plurality of signals of the sampling circuit of FIG. 4 .

FIG. 6 is a schematic diagram of a sampling circuit according to a second embodiment of the present invention.

FIG. 7 is a timing diagram of a plurality of signals of the sampling circuit of FIG. 6 .

Symbol Description

100 Decision Feedback Equalizer

102, 112, 122 summation circuit

108 Multiplexer

110 First Path

114, 124, 314, 324 sampling circuit

120 Second Path

316, 326 latch circuit

410, 610 sense amplifier

412, 414, 612, 614 inverters

420, 620 adjustment circuit

CK, CKB clock signal

D_odd first digital signal

D_even second digital signal

Dout output digital signal

M1～M13 Transistor

S_odd first setting signal

S_even second setting signal

R_odd first reset signal

R_even second reset signal

Vin input signal

Vin’, Vin’+, Vin’- Adjusted input signal

VFB1_even, VFB1_odd, VFB2 feedback signal

Vh1 voltage

VCM common mode voltage

Detailed ways

FIG. 1 is a schematic diagram of a decision feedback equalizer 100 according to an embodiment of the present invention. As shown in FIG. 1 , the decision feedback equalizer 100 includes a summation circuit 102 , a first path 110 , a second path 120 and a multiplexer 108 , wherein the first path 110 includes a summation circuit 112 and A sampling circuit 114 , and the second path 120 includes a summing circuit 122 and a sampling circuit 124 .

The decision feedback equalizer 100 shown in FIG. 1 employs two paths and half-rate multiplexing to reduce the operation delay. Specifically, referring to the timing diagram shown in FIG. 2 , during the operation of the decision feedback equalizer 100 , the summation circuit 102 subtracts a feedback signal VFB2 from the input signal Vin to generate an adjusted input signal Vin′, and then , the summation circuit 112 in the first path 110 subtracts a feedback signal VFB1_even from the adjusted input signal Vin', and uses a clock signal CK for sampling by the sampling circuit 114 to generate a first digital signal D_odd; and the second The summation circuit 122 in the path 120 subtracts a feedback signal VFB1_odd from the adjusted input signal Vin', and uses a clock signal CKB for sampling by the sampling circuit 124 to generate a second digital signal D_even. After that, the multiplexer 108 is controlled by the clock signal CKB to alternately output the first digital signal D_odd and the second digital signal D_even as the output digital signal Dout of the decision feedback equalizer 100 . For example, assuming that the input signal Vin includes bits A, B, C, D, and E in sequence, and the frequencies of the clock signals CK and CKB are respectively half of the frequency of the input signal Vin, the first output signal generated by the sampling circuit 114 The digital signal D_odd includes A, C, and E, and the second digital signal D_even generated by the sampling circuit 124 includes B and D, that is, the first digital signal D_odd is used as the odd-numbered bits of the output digital signal Dout, and the second The digital signal D_even is an even-numbered bit as the output digital signal Dout.

In FIG. 1, the feedback signal VFB2 is generated by the output digital signal Dout adjusted according to the connector parameter h2, the feedback signal VFB1_even is generated by the second digital signal D_even adjusted according to the connector parameter h1, and the feedback signal VFB1_odd is generated by the first digital signal D_odd is generated according to the adjustment of the joint parameter h1. As described in the prior art, in a high-speed decision feedback equalizer, the most difficult part to implement is the feedback of the first joint (that is, the related operation of the feedback signal VFB1_even and the feedback signal VFB1_odd). Therefore, in order to reduce the feedback delay , the present invention embeds the feedback function in the sampling circuit, and its specific implementation is as follows.

FIG. 3 is a circuit structure diagram of the first path 110 and the second path 120 according to an embodiment of the present invention. In FIG. 3 , the first path 110 includes a sampling circuit 314 and a latch circuit (SR latch) 316 , wherein the sampling circuit 314 is a sampling circuit with an embedded feedback function, that is, the sampling circuit 314 includes the sampling circuit 314 shown in FIG. 1 . The shown summation circuit 112, the connector parameter h1 and some functions of the sampling circuit 114; similarly, the second path 120 includes the sampling circuit 324 and a latch circuit 326, wherein the sampling circuit 324 is a sampling circuit with an embedded feedback function, That is, the sampling circuit 324 includes the summing circuit 122 shown in FIG. 1 , the joint parameter h1 and some functions of the sampling circuit 124 . In the embodiment shown in FIG. 3 , the sampling circuit 314 generates a first setting signal S_odd and a first reset signal according to the adjusted input signal Vin′, a second setting signal S_even and a second reset signal R_even Set the signal R_odd, and the latch circuit 316 generates the first digital signal D_odd according to the first setting signal S_odd and the first reset signal R_odd; similarly, the sampling circuit 324 generates the first digital signal D_odd according to the adjusted input signal Vin', the first setting signal S_odd and the first reset signal R_odd generate the second set signal S_even and the second reset signal R_even, and the latch circuit 326 generates the second digital signal D_even according to the second set signal S_even and the second reset signal R_even . In FIG. 3 , the first setting signal S_odd and the first reset signal R_odd may correspond to the feedback signal VFB1_odd shown in FIG. 1 , and the second setting signal S_even and the second reset signal R_even may correspond to the feedback signal VFB1_odd shown in FIG. 1 . The feedback signal VFB1_even shown.

FIG. 4 is a schematic diagram of the sampling circuit 314 according to a first embodiment of the present invention. As shown in FIG. 4 , the sampling circuit 314 includes a sense amplifier 410 and an adjustment circuit 420 , wherein the sense amplifier 410 includes a sensor for receiving the adjusted input signal Vin' (including the differential signals Vin'+, Vin'-). The transistors M1 and M2, the transistor M3 as a sense amplifying switch, a plurality of transistors M4-M9 coupled to the supply voltage VDD, and two inverters 412 and 414; the adjustment circuit 420 includes a first differential amplifier as a two transistors M10 and M11, two transistors M12 and M13 as a second differential amplifier, and two switches SW1 and SW2. In this embodiment, the transistors M1, M2 are used for receiving the adjusted input signal Vin' to generate the amplified input signal on the terminals N1, N2, and the drains of the transistors M4, M5 are used for outputting the signals S', R', The signals S' and R' are respectively operated by the inverters 412 and 414 to generate the first setting signal S_odd and the first reset signal R_odd. The drain of the transistor of the first differential amplifier is directly connected to the terminal of the sense amplifier, and the drain of the transistor of the second differential amplifier is directly connected to the terminal of the sense amplifier. In addition, in the adjustment circuit 420, the first differential amplifier (ie, the transistors M10, M11) is connected to the transistor M3 as a sense amplification switch through a switch SW1, wherein the switch SW1 is controlled by the second setting signal S_even, that is The first differential amplifier is selectively enabled according to the second setting signal S_even to generate a first adjustment signal to the terminals N1 and N2 according to a differential voltage signal (VCM+Vh1, VCM-Vh1) to adjust the amplified The voltage level of the input signal (that is, adding or subtracting the components corresponding to the voltage Vh1 at the terminals N1 and N2); in addition, the second differential amplifier (that is, the transistors M12 and M13) is connected to the The transistor M3 of the sense amplifying switch, wherein the switch SW2 is controlled by the second reset signal R_even, that is, the second differential amplifier is selectively enabled according to the second reset signal R_even to be based on a differential voltage signal (VCM+ Vh1, VCM-Vh1) to generate a second adjustment signal to the terminals N1, N2 to adjust the voltage level of the amplified input signal (that is, add or subtract the components corresponding to the voltage Vh1 at the terminals N1, N2 ). The source of the transistor of the first differential amplifier is connected to the sense amplifier switch through a first switch, and the source of the transistor of the second differential amplifier is connected to the sense amplifier switch through a second switch, wherein The first switch and the second switch are controlled by the second setting signal and the second reset signal, respectively.

The structure of the sampling circuit 324 is similar to the sampling circuit 314 shown in FIG. 4 , the only difference is that the output of the sampling circuit 410 needs to be changed from the first setting signal S_odd and the first reset signal R_odd to the second setting signal S_even and the first setting signal S_odd. The dual reset signal R_even, and the switches SW1 and SW2 are respectively controlled by the first set signal S_odd and the first reset signal R_odd. Since those skilled in the art should be able to understand how to implement the sampling circuit 324 after reading the above embodiments, the relevant details will not be repeated.

As described in the circuit structures of FIGS. 3 and 4 , since the first setting signal S_odd and the first reset signal R_odd generated by the sampling circuit 314 can be immediately used by the sampling circuit 324 to quickly adjust the output of the sampling circuit 324 , Similarly, the second setting signal S_even and the second reset signal R_even generated by the sampling circuit 324 can also be immediately used by the sampling circuit 314 to quickly adjust the output of the sampling circuit 314, plus the delay in the overall circuit is almost Only the amplification time of the sense amplifier 410 and the delay time of the inverters 412 and 414 can effectively reduce the feedback delay problem in the conventional architecture. Referring to the timing diagram shown in FIG. 5 , after the sampling circuit 324 generates the second setting signal S_even and the second reset signal R_even to determine the bit B, the second setting signal S_even and the second reset signal R_even It can be quickly input to the adjustment circuit 420 in the sampling circuit 314 of FIG. 4 for the sampling circuit 314 to generate the first set signal S_odd and the first reset signal R_odd to determine the bit C for use.

In this example, the common mode voltage VCM of the differential signal received by the first differential amplifier (ie, transistors M10, M11) and the second differential amplifier (ie, transistors M12, M13) in the adjustment circuit 420 is the same as the adjusted input The common mode voltage of the signal Vin' (including the differential signal Vin'+, Vin'-), therefore, the sense amplifier 410 and the adjustment circuit 420 will be the same under the variation of process, temperature, voltage (process, temperature, voltage). /Similar variation, that is, the adjustment signal generated by the adjustment circuit 420 can actually reflect the voltage Vh1 without changing with temperature. On the other hand, since the voltage Vh1 does not change with temperature, the adaptive algorithm of the connector parameter h1 can only be activated when the electronic device is turned on without background execution, which indirectly reduces the system complexity.

FIG. 6 is a schematic diagram of the sampling circuit 314 according to a second embodiment of the present invention. As shown in FIG. 6 , the sampling circuit 314 includes a sense amplifier 610 and an adjustment circuit 620 , wherein the sense amplifier 610 includes a sensor for receiving the adjusted input signal Vin' (including the differential signals Vin'+, Vin'-). The transistors M1 and M2, the transistor M3 as a sense amplifying switch, a plurality of transistors M4-M9 coupled to the supply voltage VDD, and two inverters 612 and 614; the adjustment circuit 620 includes a first differential amplifier as a two transistors M10 and M11, two transistors M12 and M13 as a second differential amplifier, and two switches SW1 and SW2. In this embodiment, the transistors M1, M2 are used for receiving the adjusted input signal Vin' to generate the amplified input signal on the terminals N1, N2, and the drains of the transistors M4, M5 are used for outputting the signals S', R', The signals S' and R' are respectively operated by the inverters 612 and 614 to generate the first setting signal S_odd and the first reset signal R_odd. In addition, in the adjustment circuit 620, the first differential amplifier (ie, the transistors M10, M11) is connected to the ground voltage through the switch SW1, which is controlled by the second setting signal S_even and the clock signal CK (eg, and gate (AND) gate, the AND gate) is controlled by the output after receiving the second setting signal S_even and the clock signal CK), that is, the first differential amplifier is selectively enabled according to the second setting signal S_even and the clock signal, so as to be based on a Differential voltage signals (VCM+Vh1, VCM-Vh1) to generate a first adjustment signal to the terminals N1, N2 to adjust the voltage level of the amplified input signal (that is, adding or subtracting the voltage at the terminals N1, N2 The component corresponding to Vh1); in addition, the second differential amplifier (ie, transistors M12, M13) is connected to the ground voltage through the switch SW2, wherein the switch SW2 is controlled by the second reset signal R_even and the clock signal CK (eg, and gate (AND gate) is controlled by the output after receiving the second reset signal R_even and the clock signal CK), that is, the second differential amplifier is selectively enabled according to the second reset signal R_even to be based on a differential voltage signal ( VCM+Vh1, VCM-Vh1) to generate a second adjustment signal to the terminals N1, N2 to adjust the voltage level of the amplified input signal (that is, adding or subtracting the voltage Vh1 at the terminals N1, N2 corresponds to ingredients). The source of the transistor of the first differential amplifier is connected to a reference voltage through a first switch, and the source of the transistor of the second differential amplifier is connected to the reference voltage through a second switch, wherein the first switch It is controlled by the second setting signal and the clock signal at the same time, and the second switch is controlled by the second reset signal and the clock signal at the same time.

The structure of the sampling circuit 324 is similar to the sampling circuit 314 shown in FIG. 6 , the only difference is that the output of the sampling circuit 410 needs to be changed from the first setting signal S_odd and the first reset signal R_odd to the second setting signal S_even and the first setting signal S_odd. The dual reset signal R_even, and the switches SW1 and SW2 are respectively controlled by the first set signal S_odd and the first reset signal R_odd. Since those skilled in the art should be able to understand how to implement the sampling circuit 324 after reading the above embodiments, the relevant details will not be repeated.

3 and 6 , since the first setting signal S_odd and the first reset signal R_odd generated by the sampling circuit 314 can be immediately used by the sampling circuit 324 to quickly adjust the output of the sampling circuit 324 , Similarly, the second setting signal S_even and the second reset signal R_even generated by the sampling circuit 324 can also be immediately used by the sampling circuit 314 to quickly adjust the output of the sampling circuit 314, plus the delay in the overall circuit is almost Only the amplification time of the sense amplifier 410 and the delay time of the inverters 412 and 414 can effectively reduce the feedback delay problem in the conventional architecture. Referring to the timing diagram shown in FIG. 7 , after the sampling circuit 324 generates the second setting signal S_even and the second reset signal R_even to determine the bit B, the second setting signal S_even and the second reset signal R_even It can be quickly input to the adjustment circuit 420 in the sampling circuit 314 of FIG. 4 for the sampling circuit 314 to generate the first set signal S_odd and the first reset signal R_odd to determine the bit C for use.

In this example, the common mode voltage VCM of the differential signal received by the first differential amplifier (ie, transistors M10, M11) and the second differential amplifier (ie, transistors M12, M13) in the adjustment circuit 620 is the same as the adjusted input The common mode voltage of the signal Vin' (including the differential signals Vin'+, Vin'-), therefore, the sense amplifier 610 and the adjustment circuit 620 will have the same/similar changes under the variation of process, temperature, and voltage, that is, The adjustment signal generated by the adjustment circuit 620 can actually reflect the voltage Vh1 without changing with temperature. On the other hand, since the voltage Vh1 does not change with temperature, the adaptive algorithm of the connector parameter h1 can only be activated when the electronic device is turned on without background execution, which indirectly reduces the system complexity.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (10)

1. A decision feedback equalizer, comprising: A first path, including: a first sampling circuit for generating a first setting signal and a first reset signal according to an input signal, a second setting signal and a second reset signal; and a first latch circuit, coupled to the sampling circuit, for generating a first digital signal according to the first setting signal and the first reset signal; and A second path, including: a second sampling circuit for generating the second setting signal and the second reset signal according to the input signal, the first setting signal and the first reset signal; and a second latch circuit, coupled to the second sampling circuit, for generating a second digital signal according to the second setting signal and the second reset signal; The first sampling circuit includes: a sense amplifier for receiving the input signal and generating an amplified input signal at a terminal; and an adjustment circuit, coupled to the terminal of the sense amplifier, and according to the second setting signal and the second reset signal to generate an adjustment signal to the terminal to adjust the voltage level of the amplified input signal; The first setting signal and the first reset signal are generated according to the amplified input signal. 2. The decision feedback equalizer as claimed in claim 1, wherein the first digital signal is used as an odd-numbered bit of an output digital signal of the decision feedback equalizer, and the second digital signal is used as the output digital signal of the decision feedback equalizer. The even-numbered bits of the output digital signal. 3. The decision feedback equalizer of claim 1, wherein the adjustment circuit comprises: a first differential amplifier selectively enabled according to the second setting signal to generate a first adjustment signal to the terminal according to a first differential voltage signal to adjust the voltage level of the amplified input signal bits; and a second differential amplifier selectively enabled according to the second reset signal to generate a second adjustment signal to the terminal according to a second differential voltage signal to adjust the voltage level of the amplified input signal bit. 4. The decision feedback equalizer of claim 3, wherein the input signal is a differential input signal, and the differential input signal, the first differential voltage signal and the second differential voltage signal have the same common mode voltage. 5. The decision feedback equalizer of claim 3, wherein the sense amplifier comprises a sense amplifier switch, the sense amplifier switch is controlled by a clock signal to determine whether to enable or not, the first differential amplifier The source of the transistor is connected to the sense amplifier switch through a first switch, and the source of the transistor of the second differential amplifier is connected to the sense amplifier switch through a second switch, wherein the first switch is connected to the sense amplifier switch. The second switches are controlled by the second setting signal and the second reset signal, respectively. 6. The decision feedback equalizer of claim 5, wherein the drain of the transistor of the first differential amplifier is directly connected to the terminal of the sense amplifier, and the drain of the transistor of the second differential amplifier is directly connected to the terminal of the sense amplifier. 7. The decision feedback equalizer of claim 1, wherein the adjustment circuit comprises: a first differential amplifier for selectively enabling according to the second setting signal and a clock signal to generate a first adjustment signal to the terminal according to a first differential voltage signal to adjust the amplified input the voltage level of the signal; and a second differential amplifier selectively enabled according to the second reset signal and the clock signal to generate a second adjustment signal to the terminal according to a second differential voltage signal to adjust the amplified input The voltage level of the signal. 8. The decision feedback equalizer of claim 7, wherein the input signal is a differential input signal, and the differential input signal, the first differential voltage signal and the second differential voltage signal have the same common mode voltage. 9. The decision feedback equalizer of claim 7, wherein the sense amplifier comprises a sense amplifier switch, the sense amplifier switch is controlled by a clock signal to determine whether to enable or not, the first differential amplifier The source of the transistor is connected to a reference voltage through a first switch, and the source of the transistor of the second differential amplifier is connected to the reference voltage through a second switch, wherein the first switch is also connected by the second device. The second switch is controlled by the second reset signal and the clock signal at the same time. 10. The decision feedback equalizer of claim 9, wherein the drain of the transistor of the first differential amplifier is directly connected to the terminal of the sense amplifier, and the drain of the transistor of the second differential amplifier is directly connected to the terminal of the sense amplifier.

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