CN111711449A - Parasitic capacitance digital compensation method and device - Google Patents
Parasitic capacitance digital compensation method and device Download PDFInfo
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- CN111711449A CN111711449A CN202010615554.8A CN202010615554A CN111711449A CN 111711449 A CN111711449 A CN 111711449A CN 202010615554 A CN202010615554 A CN 202010615554A CN 111711449 A CN111711449 A CN 111711449A
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Abstract
The invention discloses a method and a device for compensating parasitic capacitance digitally. The method comprises the following steps: obtaining digital code words through analog-to-digital conversion, wherein the digital code words comprise sign bit code words, L-bit high-end code words and L-bit low-end code words, the L-bit high-end code words are code words obtained through capacitance conversion of L high-end bits, and the L-bit low-end code words are code words obtained through capacitance conversion of L low-end bits; compensating the L-bit low-end code word to obtain a compensated low-end code word; combining the compensated low-end code words with the sign-position code words and the high-end code words to obtain intermediate code words; and compensating the intermediate code word to obtain a compensated full code word. The invention achieves the effect of improving the analog-to-digital conversion accuracy.
Description
Technical Field
The invention relates to the technical field of analog-to-digital conversion, in particular to a parasitic capacitance digital compensation method and a parasitic capacitance digital compensation device.
Background
In the global digital information wave, the position of the analog-to-digital converter in the integrated circuit and information industry is very important and rapidly developed as a bridge for connecting the objective analog world and the digital signal. The load distribution type successive approximation analog-to-digital converter (SAR ADC) has been widely introduced in the fields of consumer electronics and medical equipment due to its characteristics of medium speed, low power consumption and low cost. Typically, a SAR ADC consists of a digital-to-analog converter (DAC), a comparator, digital comparison and control logic, and other analog circuitry. The conversion precision of the SAR ADC is determined by the number of capacitors of the binary capacitor array of the DAC, and the more the number of bits is, the more the number of capacitors is needed. Since the capacitance value in the binary capacitor array of the DAC increases by a multiple of 2, the capacitance of the most significant bit is usually larger, for example, the capacitance of the most significant bit of the DAC capacitor array of the SAR ADC with 10-bit precision is 1024 times the capacitance value of the least significant bit.
Because the capacitance value of the high-order capacitor of the capacitor array is usually very large, the power consumption generated in the charging and discharging process of conversion is also very large, and the power consumption of the high-precision SAR ADC is very large. Therefore, people put forward the design of the segmented capacitor array, namely, the original capacitor array can be segmented into at least two segments, so that the maximum capacitance value of each segment of the capacitor array is much smaller than that of the original capacitor array, for the case that the 10-bit capacitor array is segmented into two 5-bit capacitor arrays, the original highest-bit capacitor is 1024 times of the lowest-bit capacitance value, and the highest-bit capacitor of each segment after segmentation is 32 times of the lowest-bit capacitance value, so that the power consumption is greatly reduced.
However, since the parasitic capacitance between the metal layers during the production process has a large influence on the conversion accuracy in the low-end portion after the segmentation, the parasitic capacitance must be calibrated or compensated for to achieve a high accuracy. At present, most of the calibration or compensation methods for parasitic capacitance are analog circuit methods, manual adjustment is needed, and operation is difficult.
Aiming at the problem that the parasitic capacitance influences the analog-to-digital conversion precision in the related technology, an effective solution is not provided at present.
Disclosure of Invention
The invention mainly aims to provide a parasitic capacitance digital compensation method and a parasitic capacitance digital compensation device, so as to solve the problem that the parasitic capacitance influences the analog-to-digital conversion precision.
In order to achieve the above object, according to one aspect of the present invention, there is provided a method for compensating for parasitic capacitance in a successive approximation type analog-to-digital converter, wherein the SAR ADC includes a DAC and a comparator, the DAC is divided into a high-end bit capacitance and a low-end bit capacitance according to a distance from the comparator, and the number of bits is divided into a sign bit codeword, a high-end codeword and a low-end codeword, the method including: obtaining digital code words through analog-to-digital conversion, wherein the digital code words comprise sign bit code words, L-bit high-end code words and L-bit low-end code words, the L-bit high-end code words are code words obtained through conversion of L high-end capacitor, the L-bit low-end code words are code words obtained through conversion of L low-end capacitor, and capacitors of the high-end bit and the low-end bit are distinguished according to a discharge sequence; compensating the L-bit low-end code word to obtain a compensated low-end code word; combining the compensated low-end code word with the sign bit code word and the high-end code word to obtain a middle code word; and compensating the intermediate code word to obtain a compensated full code word.
Further, compensating the L-bit low-end codeword to obtain a compensated low-end codeword includes: acquiring a parasitic capacitance value of a low-end capacitance section; obtaining an amplitude factor according to the parasitic capacitance value; and multiplying the L-bit low-end code word by the amplitude factor to obtain the compensated low-end code word.
Further, obtaining the amplitude factor according to the parasitic capacitance value comprises: the amplitude factor is calculated by the formula a ═ Cp/(Cp +2^ L), where Cp is in units of the minimum capacitance of the low-side capacitance segment.
Further, combining the compensated low-end codeword with the sign-bit codeword and the high-end codeword to obtain an intermediate codeword includes: compensated low-end code word CLOriginal L-bit high-end code word CHSign bit CSThe three are combined together to form a middle code word CMWherein, CM＝{CS,CH,CL}。
Further, obtaining a primary comparison result of the comparator; and obtaining a sign bit code word according to the primary comparison result.
In order to achieve the above object, according to another aspect of the present invention, there is also provided a parasitic capacitance digital compensation apparatus applied to a successive approximation type analog-to-digital converter, wherein the SAR ADC includes a DAC and a comparator, the DAC is divided into a high-end bit capacitance and a low-end bit capacitance according to a distance from the comparator, the apparatus includes: the digital code words comprise sign bit code words, L-bit high-end code words and L-bit low-end code words, the L-bit high-end code words are code words obtained by capacitance conversion of L high-end bits, and the L-bit low-end code words are code words obtained by capacitance conversion of L low-end bits; a first compensation unit, configured to compensate the L-bit low-end codeword to obtain a compensated low-end codeword; a combining unit, configured to combine the compensated low-end codeword with the sign-position codeword and the high-end codeword to obtain an intermediate codeword; and the second compensation unit is used for compensating the intermediate code word to obtain a compensated full code word.
Further, the first compensation unit includes: the acquisition module is used for acquiring the parasitic capacitance value of the low-end capacitance section; the first calculation module is used for obtaining an amplitude factor according to the parasitic capacitance value; and the second calculation module is used for multiplying the L-bit low-end code word by the amplitude factor to obtain the compensated low-end code word.
Further, the first computing module is to: the amplitude factor is calculated by the formula a ═ Cp/(Cp +2^ L), where Cp is in units of the minimum capacitance of the low-side capacitance segment.
In order to achieve the above object, according to another aspect of the present invention, there is also provided a computer-readable storage medium, characterized in that the computer-readable storage medium includes a stored program, wherein when the program is executed by a processor, the program controls an apparatus in which the storage medium is located to execute the parasitic capacitance digital compensation method according to the present invention.
In order to achieve the above object, according to another aspect of the present invention, there is also provided an apparatus at least including a processor, and at least one memory and a bus connected to the processor, wherein the processor and the memory are configured to communicate with each other through the bus, and the processor is configured to call program instructions in the memory to execute the parasitic capacitance digital compensation method according to the present invention.
The digital code words are obtained through analog-to-digital conversion, wherein the digital code words comprise sign bit code words, L-bit high-end code words and L-bit low-end code words, the L-bit high-end code words are code words obtained through conversion of L high-end capacitor, and the L-bit low-end code words are code words obtained through conversion of L low-end capacitor; compensating the L-bit low-end code word to obtain a compensated low-end code word; combining the compensated low-end code words with the sign-position code words and the high-end code words to obtain intermediate code words; the intermediate code words are compensated to obtain the compensated full code words, so that the problem that the parasitic capacitance influences the analog-to-digital conversion precision is solved, and the effect of improving the analog-to-digital conversion precision is achieved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a flow chart of a method of parasitic capacitance digital compensation according to an embodiment of the present invention;
FIG. 2 is a circuit block diagram of a SAR ADC according to an embodiment of the present invention;
fig. 3 is a flow chart of digital compensation of parasitic capacitance of the present embodiment;
FIG. 4 is a schematic diagram of a parasitic capacitance digital compensation apparatus according to an embodiment of the present invention;
fig. 5 is a block diagram of an alternative digital compensation apparatus for parasitic capacitance of SAR ADC according to an embodiment of the present invention.
Detailed Description
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The embodiment of the invention provides a parasitic capacitance digital compensation method.
Fig. 1 is a flowchart of a parasitic capacitance digital compensation method according to an embodiment of the present invention, as shown in fig. 1, the method including the steps of:
step S102: and obtaining a digital code word through analog-to-digital conversion, wherein the digital code word comprises a sign bit code word, an L-bit high-end code word and an L-bit low-end code word, the L-bit high-end code word is a code word obtained by converting L high-end capacitors, the L-bit low-end code word is a code word obtained by converting L low-end capacitors, the SAR ADC comprises a DAC and a comparator, and the DAC is divided into a high-end capacitor and a low-end capacitor according to the distance from the DAC to the comparator.
Step S104: compensating the L-bit low-end code word to obtain a compensated low-end code word;
step S106: combining the compensated low-end code words with the sign-position code words and the high-end code words to obtain intermediate code words;
step S108: and compensating the intermediate code word to obtain a compensated full code word.
The technical scheme of the embodiment is applied to a successive approximation type analog-to-digital converter, and the embodiment obtains digital code words through analog-to-digital conversion, wherein the digital code words comprise sign bit code words, L-bit high-end code words and L-bit low-end code words, the L-bit high-end code words are code words obtained through capacitance conversion of L high-end bits, and the L-bit low-end code words are code words obtained through capacitance conversion of L low-end bits; compensating the L-bit low-end code word to obtain a compensated low-end code word; combining the compensated low-end code words with the sign-position code words and the high-end code words to obtain intermediate code words; the intermediate code words are compensated to obtain the compensated full code words, so that the problem that the parasitic capacitance influences the analog-to-digital conversion precision is solved, and the effect of improving the analog-to-digital conversion precision is achieved.
In this embodiment, the low end portion and the high end portion each include L capacitors having capacitance values gradually increased by 2 times, the capacitance value of the lowest capacitor is a unit capacitor, the low end portion and the high end portion of the DAC are connected by a bridge capacitor having a capacitance value of a unit capacitor, the DAC is divided into a high end capacitor and a low end capacitor according to a distance from the comparator, the high end capacitor is closer to the input terminal of the comparator than the low end capacitor, upper plates of the L capacitors of the low end portion are connected to one end of the bridge capacitor, upper plates of the L capacitors of the high end portion are connected to the other end of the bridge capacitor and one input terminal of the comparator, lower plates of the L capacitors of the low end portion and the L capacitors of the high end portion are respectively connected to the analog signal input terminal, the voltage reference terminal or the ground, and the other end of the comparator is connected to the same DAC, including the high end portion, the DAC, A low-side portion and a bridge capacitor.
Dividing the normally converted code words into sign bit code words, high-end code words and low-end code words according to the bit number; the code word obtained by normal conversion is the code word obtained by adopting the conversion method in the prior art, and the low-end code word is compensated to obtain the compensated low-end code word; combining the compensated low-end code word with the original sign bit code word and the original high-end code word to obtain a middle code word; the method can be executed by a plurality of modules, and comprises a low-end code multiplication module, a low-end code quantization module, a middle code combination module, a full code multiplication module and a full code quantization module, wherein the normally converted obtained code can complete the digital compensation of the parasitic capacitance through the operation of the modules, and the compensated code with higher conversion precision is obtained.
Optionally, the compensating the L-bit low-end codeword, and the obtained low-end codeword includes: acquiring a parasitic capacitance value of a low-end capacitance section; obtaining an amplitude factor according to the parasitic capacitance value; and multiplying the L-bit low-end code word by the amplitude factor to obtain the compensated low-end code word. The amplitude factor is a preset value and can be set according to a specific application scene.
Optionally, obtaining the amplitude factor according to the parasitic capacitance value comprises: by the formula a ═ Cp/(Cp+2^ L) to obtain an amplitude factor, wherein CpIs given in units of the minimum capacitance of the low-side capacitance section.
Optionally, combining the compensated low-end codeword with the sign-bit codeword and the high-end codeword to obtain an intermediate codeword includes: compensated low-end code word CLOriginal L-bit high-end code word CHSign bit CSThe three are combined together to form a middle code word CMWherein, CM＝{CS,CH,CL}。
Optionally, obtaining a primary comparison result of the comparator; and obtaining the sign bit code word according to the primary comparison result.
The normally converted digital code words comprise 2L +1 bit code words which are respectively a sign bit, a high end code word L bit and a low end code word L bit, the sign bit is obtained by initial comparison of a comparator, the high end code word L bit is obtained by high end part of a DAC, the low end code word L bit is obtained by low end part of the DAC, compensation is carried out on the low end L bit code word, the compensation is carried out by multiplying the low end L bit code word by an amplitude factor a and still quantizing the low end code word into L bit, the result after L bit quantization is the compensated low end code word, the combination of the compensated low end code word and the sign bit and the high end code word means that the original L bit low end code word is converted into the compensated L bit low end code word, the code words of other bits are kept unchanged, the formed new 2L +1 bit code word is a middle code word, the compensation of the middle code word by multiplying the middle code word by the amplitude factor b and still quantizing the middle code word into 2L +1 bit, the result after quantization to 2L +1 bits is the full codeword after compensation of claim 1.
The embodiment of the invention also provides a preferred implementation mode.
Fig. 2 is a circuit structure diagram of a SAR ADC according to an embodiment of the present invention, as shown in fig. 2, the circuit includes a comparator, two DACs, and a SAR logic unit.
The p end and the n end of the comparator are respectively connected with a DAC, the output of the comparator is 0 or 1, and when the voltage of the p end is greater than that of the n end, 1 is output; when the p terminal voltage is less than the n terminal voltage, 0 is output.
The DAC is divided into two sections, each section is provided with L capacitors, and the middle parts of the two sections are connected by a bridging capacitor; the capacitor section close to the input end of the comparator is a high-end capacitor, and is totally L, and the capacitor section far away from the input end of the comparator is a low-end capacitor, and is also totally L; in each section of capacitor, the capacitance value is gradually increased from far to near from the input end of the comparator by 2 times, specifically, in the high-end capacitor section, the capacitance value of the capacitor farthest from the input end of the comparator is assumed to be C, and the capacitance values of other capacitors toward the input end of the comparator are sequentially 2C, 4C, … and 2CL-1C, in the low-end capacitor section, the capacitance value of the capacitor farthest from the input end of the comparator, namely the capacitor farthest from the bridging capacitor is assumed to be C, and the capacitance values of other capacitors towards the input end of the comparator are sequentially 2C, 4C, … and 2L-1C; the upper polar plates of the L capacitors of the high-end capacitor section are connected with the input end of the comparator, connected with the right end of the bridging capacitor and also connected with the reference voltage Vref through a switch, and the lower polar plates of the L capacitors of the high-end capacitor section can be respectively connected with the input signal, the reference voltage Vref or the ground through the switch; the upper polar plates of the L capacitors of the low-end capacitor section are connected with the right end of the bridging capacitor and can also be connected with a reference voltage Vref through a switch, and the lower polar plates of the L capacitors of the low-end capacitor section can be respectively connected with an input signal, the reference voltage Vref or the ground through the switch; the bridge capacitor is used for connecting the high-end capacitor section and the low-end capacitor end, the left end of the bridge capacitor is connected with the upper polar plates of the L capacitors of the low-end capacitor section, the right end of the bridge capacitor is connected with the upper polar plates of the L capacitors of the high-end capacitor section, and the left end and the right end of the bridge capacitor can be connected with a reference voltage Vref through a switch; the left-most parasitic capacitance Cp in the figure, which is not added in the design but is due to the parasitic capacitance generated between the chip metal layers, is shown here for the purpose of illustrating its effect.
One end of the SAR logic unit is connected with the output end of the comparator, and the other end of the SAR logic unit is connected with the switch connected with the lower polar plate of the capacitor; the SAR logic unit is used for controlling the on-off of the switch according to the output result of the comparator so as to obtain the conversion code word of the SAR ADC; specifically, one optional control and decision logic is: firstly, sampling input signals at a p end and an n end of a DAC, then carrying out first comparison, if the voltage of the p end is greater than that of the n end, outputting the signals as 1, connecting a switch of a lower polar plate of a highest-order capacitor of a high-end capacitor section of the DAC at the n end to Vref, connecting switches of lower polar plates of other capacitors to the ground, and connecting lower polar plates of all capacitors at the p end to the ground; if the voltage of the p end is smaller than that of the n end, the output is 0, the switch of the lower polar plate of the highest capacitor of the high-end capacitor section of the DAC of the p end is connected to Vref, the switches of the lower polar plates of the other capacitors are connected to the ground, and the lower polar plates of all the capacitors of the n end are connected to the ground.
For the second comparison, if the result of the second comparator is that the p-terminal voltage is greater than the n-terminal voltage, the output is 1, and the lower pole plate of the n-terminal secondary high-order capacitor is connected to Vref; if the second comparison shows that the voltage at the p end is smaller than that at the n end, the output is 0, and the lower pole plate of the secondary high-order capacitor at the p end is connected to Vref. If the current result is that the p end voltage is larger than the n end voltage, the output is 1, and the lower polar plate of the next capacitor at the n end is connected to Vref; if the current result is that the p end voltage is smaller than the n end voltage, the output is 0, and the lower pole plate of the capacitor at the next bit of the n end is connected to Vref until all the capacitors are judged to be finished.
When all the capacitance decisions are completed, i.e. all the converted codewords are obtained, then the digital compensation of the parasitic capacitance can be started.
Fig. 3 is a flow chart of digital compensation of parasitic capacitance of the present embodiment, which includes the following steps: first, the digital code word is obtained through normal conversion in the step S1, that is, according to the SAR ADC circuit structure of this embodiment, 2L +1 bit code words can be obtained in total through the conversion code word, L high-end capacitors, and L low-end capacitors obtained through successive comparison.
Next, in step S2, the digital code word is divided into a sign bit, a high-end code word L bit and a low-end code wordThe word L bits. The 2L +1 bit code word, as stated in step S1, is numbered from high to low as b0，b1，…，b2L. Highest bit b0Sign bit, next L bit, b1～bLFor the high-end code word, the next L bits, bL+1～b2LIs a low-end codeword.
And thirdly, in the step S3, compensating the low-end code word to obtain a compensated low-end code word. Specifically, the low-end codeword obtained at S2 is denoted as CLCalculating an amplitude factor a, a ═ C according to the magnitude of the parasitic capacitancep/(Cp+2^ L), wherein CpThe unit of (a) is the minimum capacitance of the low-end capacitance section, and the compensation process is CLMultiplying with a to obtain a product result with more bits than L bits, quantizing into L bits again, and recording the result as CL’，CL' is the compensated low-end codeword.
And step S4, combining the compensated low-end codeword with the original high-end codeword to obtain an intermediate codeword. The compensated low-end codeword obtained in S3 is CL', is L bit, the high end code word of the original L bit is marked as CHPlus sign bit CSThe three are combined together to form a middle code word CM，CM＝{CS,CH,CL'}. Intermediate code word CMThe number of bits is 2L +1 bits.
And finally, in the step S5, compensating the intermediate codeword to obtain a compensated full codeword. Specifically, the step of S4 obtains the intermediate codeword C of 2L +1 bitsMCalculating an amplitude factor b according to the magnitude of the parasitic capacitance, wherein b is 1/(1-C)p/(Cp+2^ L)/2^ L), wherein CpThe unit of (a) is the minimum capacitance of the low-end capacitance section, and the compensation process is CMMultiplying b to obtain product result with more bits than 2L +1 bits, quantizing to 2L +1 bits, and recording the result as Cc。CcI.e. the compensated full codeword, i.e. the full codeword compensated for the parasitic capacitance deviation.
In summary, the above steps from S1 to S5 result in a full codeword with the parasitic capacitance deviation compensated for from the original converted codeword. The compensated full code word has higher precision than the original converted code word and better performance for a subsequent digital processing system.
It should be noted that the steps illustrated in the flowcharts of the figures may be performed in a computer system such as a set of computer-executable instructions and that, although a logical order is illustrated in the flowcharts, in some cases, the steps illustrated or described may be performed in an order different than presented herein.
Embodiments of the present invention provide a parasitic capacitance digital compensation apparatus, which may be used to perform the parasitic capacitance digital compensation method of the embodiments of the present invention.
Fig. 4 is a schematic diagram of a parasitic capacitance digital compensation apparatus according to an embodiment of the present invention, as shown in fig. 4, the apparatus including:
a conversion unit 10, configured to obtain a digital codeword through analog-to-digital conversion, where the digital codeword includes a sign bit codeword, an L-bit high-end codeword, and an L-bit low-end codeword, the L-bit high-end codeword is a codeword obtained by converting capacitances of L high-end bits, the L-bit low-end codeword is a codeword obtained by converting capacitances of L low-end bits, and capacitances of the high-end bits and the low-end bits are distinguished according to a discharge order;
a first compensation unit 20, configured to compensate the L-bit low-end codeword to obtain a compensated low-end codeword;
a combining unit 30, configured to combine the compensated low-end codeword with the sign-bit codeword and the high-end codeword to obtain an intermediate codeword;
and a second compensation unit 40, configured to compensate the intermediate codeword to obtain a compensated full codeword.
The digital compensation device for the parasitic capacitance is applied to a successive approximation type analog-to-digital converter, the SAR ADC comprises a DAC and a comparator, and the DAC is divided into sign bit code words, high-end code words and low-end code words according to the number of bits.
The embodiment adopts a conversion unit 10, configured to obtain digital code words through analog-to-digital conversion, where the digital code words include sign bit code words, L-bit high-end code words and L-bit low-end code words, the L-bit high-end code words are code words obtained by converting capacitances of L high-end bits, the L-bit low-end code words are code words obtained by converting capacitances of L low-end bits, and capacitances of the high-end bits and the low-end bits are distinguished according to a discharge order; a first compensation unit 20, configured to compensate the L-bit low-end codeword to obtain a compensated low-end codeword; a combining unit 30, configured to combine the compensated low-end codeword with the sign-bit codeword and the high-end codeword to obtain an intermediate codeword; the second compensation unit 40 is configured to compensate the intermediate codeword to obtain a compensated full codeword, so as to solve a problem that the parasitic capacitance affects the analog-to-digital conversion accuracy, and further achieve an effect of improving the analog-to-digital conversion accuracy.
Optionally, the first compensation unit 20 includes: the acquisition module is used for acquiring the parasitic capacitance value of the low-end capacitance section; the first calculation module is used for obtaining an amplitude factor according to the parasitic capacitance value; and the second calculation module is used for multiplying the L-bit low-end code word by the amplitude factor to obtain a compensated low-end code word.
Optionally, the first calculation module is configured to: by the formula a ═ Cp/(Cp+2^ L) to obtain an amplitude factor, wherein CpIs given in units of the minimum capacitance of the low-side capacitance section.
Fig. 5 is a structural diagram of an optional digital compensation apparatus for a parasitic capacitance of a SAR ADC according to an embodiment of the present invention, as shown in fig. 5, the apparatus includes the following components:
a low-end codeword multiplication module 31, one input of which is the low-end L bits of the normal conversion codeword, e.g. the normal conversion codeword of the SAR ADC of the previous embodiment is 2L +1 bits, which are numbered from high to low as b0，b1，…，b2L. Highest bit b0Sign bit, next L bit, b1～bLFor the high-end code word, the next L bits, bL+1～b2LIs a low-end codeword. The input of the low-end codeword multiplication module is bL+1～b2LIs marked as CL. The other input of the module is an amplitude factor a calculated according to the magnitude of the parasitic capacitance, and the bit width of the amplitude factor a can be determined according to the requirement on precisionAnd, here, is optionally set to M bits. CLAnd a, completing multiplication operation in the low-end code word multiplication module, and recording the obtained product result as product result 1 which is L + M bits. The output of this block is the product result 1 of the L + M bits.
The low-end codeword quantization module 32 has as its input the output product result 1 of the S31 module. Since the bit width of the product result 1 has L + M bits, which is more than L bits of the bit width of the low-end codeword, the quantization operation needs to be performed in this module, and the quantization operation is still performed to L bits. Specifically, a rounding method is adopted, according to the situation of the L +1 th bit, if the L +1 th bit is 0, the L +1 to L + M bits are directly abandoned, and the 1 st to L th bits are taken out; if the L +1 th bit is 1, the 1 st to L th bits are added with 1, and as a result, the L +1 to L + M bits are discarded. The resulting quantized L bit result is output, i.e. the compensated low-end codeword.
An intermediate codeword combining module 33, one input of which is the compensated low-end codeword output by the S32 module, and is L bits; the other input is the original normally converted codeword, which is 2L +1 bits. Within this module the combining operation is performed. Specifically, the low L bits of the original normal transform codeword with 2L +1 bits are replaced with the compensated low-end codeword with L bits, and the result of the new 2L +1 bits is the middle codeword. The resulting intermediate codeword is the output of the module.
A full codeword multiplication module 34, one input of which is the intermediate codeword output by the S33 module, being 2L +1 bits; the other input is a magnitude factor b calculated according to the magnitude of the parasitic capacitance, and the bit width of b may depend on the requirement for precision, and is optionally set to be N bits. The intermediate code word and the amplitude factor b complete multiplication operation in the full code word multiplication module, and the obtained product result is recorded as a product result 2 which is 2L + N +1 bits. The output of this block is the product result 2 of 2L + N +1 bits.
The input of the full codeword quantization module 35 is the product result 2 output by the S34 module, which is 2L + N +1 bits. Since the bit width of the product result 2 has 2L + N +1 bits, and the original transform codeword is 2L +1 bits, the quantization operation needs to be performed in this module, and the product result 2 is still quantized to 2L +1 bits. Specifically, a rounding method is adopted, according to the condition of the 2L +2 bit, if the 2L +2 bit is 0, the 2L + 2-2L + N +1 bit is directly abandoned, and the 1-2L + 1 bit is taken out; if the 2L +2 th bit is 1, the 1 st to 2L +1 st bits are added with 1, and the 2L +2 nd to 2L + N +1 st bits are discarded. The resulting quantized 2L +1 bit result is output, i.e. the compensated full codeword.
In summary, the normally converted low-end L-bit codeword is processed by the multiplication module of the low-end codeword S31 to obtain product result 1; the product result 1 and the amplitude factor a are subjected to the operation of an S32 low-end code word quantization module to obtain a compensated low-end code word; the compensated low-end code word and the original normal conversion code word are operated by an intermediate code word combination module of S33 to obtain an intermediate code word; the intermediate code word and the amplitude factor b are operated by an S34 full code word multiplication module to obtain a product result 2; the product result 2 is processed by the full codeword quantization module of S35 to obtain a compensated full codeword. The whole transposition obtains a full codeword with the parasitic capacitance deviation compensated from the original conversion codeword. The compensated full code word has higher precision than the original conversion code word, can be connected with various subsequent digital processing systems to further process digital information, has better performance than directly processing the original conversion code word, and can output the conversion code word with higher precision.
The parasitic capacitance digital compensation device comprises a processor and a memory, wherein the conversion unit, the first compensation unit and the like are stored in the memory as program units, and the processor executes the program units stored in the memory to realize corresponding functions.
The processor comprises a kernel, and the kernel calls the corresponding program unit from the memory. The kernel can be set to be one or more, and the analog-to-digital conversion accuracy is improved by adjusting the kernel parameters.
The memory may include volatile memory in a computer readable medium, Random Access Memory (RAM) and/or nonvolatile memory such as Read Only Memory (ROM) or flash memory (flash RAM), and the memory includes at least one memory chip.
An embodiment of the present invention provides a computer-readable storage medium on which a program is stored, which, when executed by a processor, implements the parasitic capacitance digital compensation method.
The embodiment of the invention provides a processor, which is used for running a program, wherein the parasitic capacitance digital compensation method is executed when the program runs.
The embodiment of the invention provides equipment, which comprises at least one processor, at least one memory and a bus, wherein the memory and the bus are connected with the processor; the processor and the memory complete mutual communication through a bus; the processor is used for calling the program instructions in the memory to execute the parasitic capacitance digital compensation method. The device herein may be a server, a PC, a PAD, a mobile phone, etc.
The present application further provides a computer program product adapted to perform a program for initializing the following method steps when executed on a data processing device: obtaining digital code words through analog-to-digital conversion, wherein the digital code words comprise sign bit code words, L-bit high-end code words and L-bit low-end code words, the L-bit high-end code words are code words obtained through conversion of L high-end capacitor, the L-bit low-end code words are code words obtained through conversion of L low-end capacitor, and capacitors of the high-end bit and the low-end bit are distinguished according to a discharge sequence; compensating the L-bit low-end code word to obtain a compensated low-end code word; combining the compensated low-end code words with the sign-position code words and the high-end code words to obtain intermediate code words; and compensating the intermediate code word to obtain a compensated full code word.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). The memory is an example of a computer-readable medium.
Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (10)
1. A parasitic capacitance digital compensation method is applied to a successive approximation type analog-to-digital converter, and is characterized in that an SAR ADC comprises a DAC and a comparator, the DAC is divided into a high-end capacitor and a low-end capacitor according to the distance from the comparator, and the method comprises the following steps:
obtaining digital code words through analog-to-digital conversion, wherein the digital code words comprise sign bit code words, L-bit high-end code words and L-bit low-end code words, the L-bit high-end code words are code words obtained through conversion of L high-end capacitor, and the L-bit low-end code words are code words obtained through conversion of L low-end capacitor;
compensating the L-bit low-end code word to obtain a compensated low-end code word;
combining the compensated low-end code word with the sign bit code word and the high-end code word to obtain a middle code word;
and compensating the intermediate code word to obtain a compensated full code word.
2. The method of claim 1, wherein compensating the L-bit low-end codeword, and wherein obtaining the compensated low-end codeword comprises:
acquiring a parasitic capacitance value of the low-end position capacitor;
obtaining an amplitude factor according to the parasitic capacitance value;
and multiplying the L-bit low-end code word by the amplitude factor to obtain the compensated low-end code word.
3. The method of claim 2, wherein deriving an amplitude factor from the parasitic capacitance value comprises:
by the formula a ═ Cp/(Cp+2^ L) to obtain the amplitude factor, wherein CpIs given in units of the minimum capacitance of the low-side capacitance section.
4. The method of claim 1, wherein combining the compensated low-end codeword with the sign-bit codeword and the high-end codeword to obtain an intermediate codeword comprises:
compensated low-end code word CLOriginal L-bit high-end code word CHSign bit CSThe three are combined together to form a middle code word CMWherein, CM＝{CS,CH,CL}。
5. The method of claim 1,
acquiring a primary comparison result of a comparator;
and obtaining a sign bit code word according to the primary comparison result.
6. A parasitic capacitance digital compensation device is applied to a successive approximation type analog-to-digital converter, and is characterized in that an SAR ADC comprises a DAC and a comparator, the DAC is divided into a high-end capacitor and a low-end capacitor according to the distance from the comparator, and the device comprises:
the digital code words comprise sign bit code words, L-bit high-end code words and L-bit low-end code words, the L-bit high-end code words are code words obtained by capacitance conversion of L high-end bits, and the L-bit low-end code words are code words obtained by capacitance conversion of L low-end bits;
a first compensation unit, configured to compensate the L-bit low-end codeword to obtain a compensated low-end codeword;
a combining unit, configured to combine the compensated low-end codeword with the sign-position codeword and the high-end codeword to obtain an intermediate codeword;
and the second compensation unit is used for compensating the intermediate code word to obtain a compensated full code word.
7. The apparatus of claim 6, wherein the first compensation unit comprises:
the acquisition module is used for acquiring the parasitic capacitance value of the low-end-bit capacitor;
the first calculation module is used for obtaining an amplitude factor according to the parasitic capacitance value;
and the second calculation module is used for multiplying the L-bit low-end code word by the amplitude factor to obtain the compensated low-end code word.
8. The apparatus of claim 7, wherein the first computing module is configured to:
by the formula a ═ Cp/(Cp+2^ L) to obtain the amplitude factor, wherein CpIs given in units of the minimum capacitance of the low-side capacitance section.
9. A computer-readable storage medium, comprising a stored program, wherein the program, when executed by a processor, controls an apparatus in which the storage medium is located to perform the parasitic capacitance digital compensation method of any one of claims 1 to 5.
10. An apparatus, characterized in that the apparatus comprises at least a processor, and at least a memory and a bus connected with the processor, wherein the processor and the memory are in communication with each other through the bus, and the processor is configured to call program instructions in the memory to execute the parasitic capacitance digital compensation method according to any one of claims 1 to 5.
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