CN109802675A

CN109802675A - A kind of SAR ADC high-accuracy capacitor array correcting method

Info

Publication number: CN109802675A
Application number: CN201910053180.2A
Authority: CN
Inventors: 冯尧; 周雄; 李强
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2019-01-21
Filing date: 2019-01-21
Publication date: 2019-05-24

Abstract

A SAR ADC high-precision capacitance array correction method belongs to the technical field of analog integrated circuits. The invention is based on the all-digital on-chip capacitance calibration technology of the traditional SAR ADC. There are several correction capacitor arrays in the SAR ADC, each correction capacitor array includes several small capacitors distributed in a binary relationship, the number of correction capacitor arrays and the size of each correction capacitor array and its corresponding main capacitor array The size of the capacitor is related. The working mode of SAR ADC is divided into calibration mode and normal working mode. After power-on, the calibration mode is entered first, and the calibration is completed within several clock cycles through the built-in calibration logic, and the calibration array obtains its corresponding calibration information. After the calibration is completed, the chip enters the normal working mode, and the calibration capacitor array carries the calibration information and turns simultaneously with the main capacitor array to compensate the DAC output voltage, improve the output linearity of the DAC, and achieve the purpose of improving the accuracy and linearity of the ADC.

Description

A kind of SAR ADC high-accuracy capacitor array correcting method

Technical field

The invention belongs to field of analog integrated circuit, and in particular to a kind of SAR ADC high-accuracy capacitor array correcting method, For calibrating in high-precision gradual approaching A/D converter (hereinafter referred to as SAR ADC) capacitor in charge redistribution type DAC Size, to improve the linearity of SAR ADC.

Background technique

For analog circuit, the features such as digital circuit possesses strong antijamming capability, high reliablity, high integrated level. Therefore digital circuit is extremely extensive in the application of field of signal processing.Digital circuit processing is digital signal, and in nature Most of signals are analog signal, and the module that analog signal is converted into digital signal is called analog-digital converter (hereinafter referred to as ADC).Common ADC points are flash-type ADC, production by assembly line, sigma-delta type ADC and Approach by inchmeal (SAR) type ADC, user Suitable ADC can be selected according to speed and precision demand.In high-precision, low speed ADC, more commonly used type is usually Σ- Δ type ADC and Approach by inchmeal (SAR) type ADC.High-precision SAR ADC is because of its feature low in energy consumption, just more and more extensive Used.

In high-precision SAR ADC, high-precision DAC is important component part, usually by binary capacitor array The features such as composition realizes different output voltages by the overturning of different capacitors, has structure simple, low in energy consumption, easily controllable. And for high-accuracy capacitor array, the mismatch between the difference capacitor as caused by technological reason is to cause output linear The main reason for degree deterioration, this directly limits the linearity of high-precision SAR ADC.In order to improve the line of high-precision SAR ADC Property degree, the present invention propose a kind of bearing calibration of SAR ADC high-accuracy capacitor array.

Summary of the invention

A kind of SAR ADC high-accuracy capacitor array correcting method corrects high-precision in such a way that corrective capacity array compensates Spend the output linearity degree for the DAC that charge redistribution formula main capacitance array is constituted in SAR ADC.The purpose of the present invention is to solve High-accuracy capacitor array Capacitor Mismatch Effect as caused by process deviation employed in high-precision SAR ADC

Wherein, the corrective capacity array of the SAR ADC shares several, and each corrective capacity array includes several again With the small-sized capacitor that binary relationship is distributed, the capacitance size of the number of corrective capacity array and each corrective capacity array with Capacitance size in its corresponding main capacitance array is related, and the maximum capacitor of capacitance is remembered in the correction array and main capacitance array For high-order capacitor, the smallest capacitor of capacitance is denoted as bit capacitor.

The operating mode of SAR ADC is divided into correction mode and normal mode of operation, and chip initially enters correction after powering on Mode, correction is completed by built-in correcting logic within several clock cycle, and each correction array obtains its corresponding correction Information.

After completing correction course, chip enters normal mode of operation, and corrective capacity array carries to be obtained under correction mode Control information follow the main capacitance array while overturning, to main capacitance array overturn when voltage value compensate, improve The output linearity degree of whole DAC.

It is characterized in that, the high-accuracy capacitor array correcting method is the following steps are included: Step 1: from correction array Lowest order starts, and the corrective capacity array, main capacitance array is resetted, while carrying out a pre-quantization, records turn at this time Change result；Step 2: main capacitance array calibration position capacitor and the incorgruous overturning of its bit capacitor are obtained into corresponding residual error voltage, This voltage is the voltage domain value of the difference of correction bit capacitor and bit capacitor；Step 3: the information of voltage that step 2 is obtained into Row quantization, quantized result are stored in register corresponding to current correction array；Step 4: step 2 and step 3 are repeated, Average value processing, while the pre-quantization value ratio obtained with step 1 are carried out by shift register after obtained value is gradually added up Compared with taking its difference as the final result of current correction capacitor；Step 5: step 4 obtains the correction of main capacitance lowest order at this time As a result, and result is stored in correction array register, correct more high-order capacitor immediately, will be less than current school when overturning capacitor Correction array after the load register result of normotopia be corrected capacitor and overturn simultaneously, corrected voltage can be obtained Information, while repeating to obtain high bit correction as a result, knowing that highest order capacitive calibration terminates Step 2: three, four；Step 6: at this time Correction course has been completed, and SAR ADC enters normal mode of operation.

Beneficial effects of the present invention are mainly the mismatch condition for improving high-accuracy capacitor array capacitor in SAR ADC, thus The linearity for the high-precision DAC institute output voltage being made of high-accuracy capacitor array is improved, the SNDR of SAR ADC is finally improved, The indexs such as INL, DNL, SFDR.

Detailed description of the invention

Fig. 1 is the structural diagram of the present invention.

Specific embodiment

In the following with reference to the drawings and specific embodiments, the present invention is described in detail.

SAR ADC high-accuracy capacitor array correcting method proposed by the present invention is suitable for having used high-accuracy capacitor array SAR ADC, gives a kind of 14bit SAR ADC overall structure as shown in Figure 1, as example, including 14 in this embodiment Position high precision electro loading distribution formula capacitor array, i.e., main array, weight is respectively 4096,2048 ... ..., and 1,1, remembered respectively For C₁₃-C₀；According to the first to the 7th DAC corrective capacity array that binary capacitor arranges, respectively correspond maximum in main array Seven capacitors, digit are respectively 9,8,8,7,6,5,5, this seven corrective capacity arrays are denoted as T₁₃-T₇, and correct array list Position capacitor's capacity is the half of main capacitor array；Correcting logic includes that reusable 16 adder and displacement are posted Storage；ADC further includes the SAR logic controller and comparator on basis simultaneously.

Step 1: the corrective capacity array, main capacitance array are resetted, owned since the lowest order of correction array Capacitor charging carries out a pre-quantization to Vcm level, transformation result at this time is recorded, as comparator offset Information record；Step 2: by main capacitance array calibration position capacitor, it is assumed that be C_nPosition capacitor, with its bit capacitor, i.e. C_n-1To C₀, Incorgruous overturning, according to charge redistribution formula, C_nWith C_n-1To C₀Deviation caused by being adapted between the sum of capacitor's capacity due to technique, It can be formed on capacitor top crown and arrive corresponding residual error voltage；Step 3: the information of voltage that step 2 is obtained quantifies, amount Change result to be stored in register corresponding to current correction array, corresponding T₁₃-T₇；Step 4: step 2 and step 3 are repeated, Average value processing is carried out by shift register after obtained value is gradually added up, is stored again after shifting processing to T₁₃-T₇Institute In corresponding register, while the pre-quantization value obtained with step 1 compares, and takes its difference as the final of current correction capacitor As a result；Step 5: step 4 obtains main capacitance and needs lowest order in corrective capacity, i.e. C at this time₇, correction as a result, and by result It is stored in correction array register T₇In, more high-order capacitor is corrected immediately, will be less than the load of current correction position when overturning capacitor Correction array after register result be corrected capacitor and overturn simultaneously, corrected information of voltage can be obtained, simultaneously It repeats to obtain high bit correction as a result, until highest order capacitor C Step 2: three, four₁₃Correction terminates；Step 6: correcting at this time Journey has been completed, and SAR ADC enters normal mode of operation.

Those skilled in the art should understand that modification and variation combination can be made to the present invention, but do not taking off In range from the spirit of this programme, it should all cover within the scope of the present invention.

Claims

1. a kind of SAR ADC high-accuracy capacitor array correcting method, in such a way that corrective capacity array compensates, correction high-precision The output linearity degree for the DAC that charge redistribution formula main capacitance array is constituted in SAR ADC；

Wherein, the corrective capacity array of the SAR ADC shares several, and each corrective capacity array includes several with two again The small-sized capacitor of system relationship distribution, the number of corrective capacity array and the capacitance size of each corrective capacity array are right with it Capacitance size in the main capacitance array answered is related, and the maximum capacitor of capacitance is denoted as height in the correction array and main capacitance array Position capacitor, the smallest capacitor of capacitance are denoted as bit capacitor；

The operating mode of SAR ADC is divided into correction mode and normal mode of operation, and chip initially enters correction mode after powering on, Correction is completed within several clock cycle by built-in correcting logic, each correction array obtains its corresponding control information；

After completing correction course, chip enters normal mode of operation, and corrective capacity array carries the school obtained under correction mode Positive information follows the main capacitance array while overturning, and voltage value when overturning to main capacitance array compensates, and improves whole The output linearity degree of DAC；

It is characterized in that, the high-accuracy capacitor array correcting method is the following steps are included: Step 1: from the minimum of correction array Position starts, and the corrective capacity array, main capacitance array is resetted, while carrying out a pre-quantization, records Change-over knot at this time Fruit；Step 2: main capacitance array calibration position capacitor and the incorgruous overturning of its bit capacitor are obtained into corresponding residual error voltage, this electricity Pressure is the voltage domain value of the difference of correction bit capacitor and bit capacitor；Step 3: the information of voltage amount of progress that step 2 is obtained Change, quantized result is stored in register corresponding to current correction array；Step 4: step 2 and step 3 are repeated, will The value arrived gradually add up after by shift register progress average value processing, while the pre-quantization value obtained with step 1 compares, Take its difference as the final result of current correction capacitor；Step 5: step 4 obtains the correction knot of main capacitance lowest order at this time Fruit, and result is stored in correction array register, more high-order capacitor is corrected immediately, will be less than current correction when overturning capacitor Correction array after the load register result of position be corrected capacitor and overturn simultaneously, corrected voltage can be obtained and believe Breath, while repeating to obtain high bit correction as a result, knowing that highest order capacitive calibration terminates Step 2: three, four；Step 6: school at this time Positive process has been completed, and SAR ADC enters normal mode of operation.

2. a kind of SAR ADC high-accuracy capacitor array correcting method according to claim 1, which is characterized in that described Correcting mode has used SAR ADC to work normally the overturning logic for being, does not need using special overturning logic, while after overturning Result map directly in correction array, avoid in traditional SAR ADC capacitor array correcting mode using small-sized capacitor battle array The inconsistent bring correction error of capacitance error in array when being mapped to correction array after column quantization residual error.

3. a kind of SAR ADC high-accuracy capacitor array correcting method according to claim 1, which is characterized in that described Correcting mode carries out rollover before correction starts and turns, and without purpose that capacitor is hanging and carrying out capacitor plus-minus, reduces circuit Complexity.