CN113810052B - Successive approximation analog-to-digital converter based on capacitance mismatch calibration circuit - Google Patents

Abstract

The invention discloses a successive approximation analog-to-digital converter based on a capacitance mismatch calibration circuit, which comprises: the comparator comprises a first input end, a second input end and an output end, and a bottom plate switch is arranged between the first input end and the second input end; the sampling hold unit comprises a first capacitor, a first switch array, a second capacitor and a second switch array; the capacitor mismatch calibration circuit comprises a low-order capacitor calibration array, a low-order switch array, a high-order capacitor calibration array, a high-order switch array, and a bridge capacitor with a capacitance value of alpha C _{c_cal} Alpha is more than 1, alpha is redundancy coefficient, C _{c_cal} The capacitance value of the ideal bridging capacitor; and the control logic unit is used for outputting the first control logic and the second control logic. The invention introduces the redundancy coefficient alpha into the bridging capacitor to increase the total weight of the low-order capacitor, ensure that the total weight of the low-order capacitor is larger than the weight of the lowest-order capacitor of the high-order capacitor, and solve the problem that the low-order capacitor cannot be calibrated under the condition of capacitor mismatch.

Description

Successive approximation analog-to-digital converter based on capacitance mismatch calibration circuit

Technical Field

The invention belongs to the technical field of analog-to-digital converters, and particularly relates to a successive approximation analog-to-digital converter based on a capacitance mismatch calibration circuit.

Background

A basic successive approximation analog-to-digital converter (SAR ADC) is shown in fig. 1. The device performs the conversion on command, and in order to process the ac signal, the SAR ADC must have an input sample-and-hold (SHA) function to achieve that the signal is kept unchanged during the conversion period.

At the transition period, the sample-and-hold (SHA) circuit is placed in hold mode, while the internal DAC is set to an intermediate level. The comparator determines whether the SHA output is greater or less than the DAC output and stores the result (bit 1, the most significant bit of the transition) in a Successive Approximation Register (SAR). The DAC is then set to either 1/4 range or 3/4 range (depending on the value of bit 1), and the comparator determines bit 2 of the conversion, the result is also stored in the register, and the process continues until the values of all bits are determined. After all bits are set, tested and reset as needed, the contents of the SAR are converted to this completion, corresponding to the value of the analog input. These bits "test" form the basis of a serial output SAR ADC.

In high precision analog to digital conversionIn the device, the capacitance mismatch is an important cause of the linearity degradation. Usually, only 10-12 bit precision can be achieved through layout matching, and if an analog-digital converter with higher precision needs to be realized, a Trim calibration method is needed. As shown in FIG. 2, the conventional method is to calibrate the capacitor mismatch by using a binary capacitor calibration array CDAC_cal, and the capacitor to be calibrated is C ₀ The goal is C after calibration ₀ Equal to C _TARGET Ncal is the total number of capacitors in the capacitor calibration array. This conventional calibration has mainly the following drawbacks:

1. calibration can only increase capacitance C _TARGET But if C _TARGET Inherent specific capacitance C ₀ If the calibration is large, the specific Trim value cannot be found, so that the calibration fails;

2. if the number of bits of the Ncal is large, the calibration capacitor itself has a problem of nonlinearity. To ensure linearity of the calibration cdac_cal, the area of the calibration CDAC needs to be increased. If the number of Ncal bits is greater than 10 bits, the linearity of the calibration CDAC_cal may also not be satisfactory, resulting in a failure to find a particular Trim value, with a high probability of calibration failure.

Therefore, in view of the above-mentioned technical problems, it is necessary to provide a successive approximation analog-to-digital converter based on a capacitance mismatch calibration circuit.

Disclosure of Invention

The invention aims to provide a successive approximation analog-to-digital converter based on a capacitance mismatch calibration circuit so as to solve the problem of capacitance mismatch in the analog-to-digital converter.

In order to achieve the above object, an embodiment of the present invention provides the following technical solution:

a successive approximation analog-to-digital converter based on a capacitance mismatch calibration circuit, the analog-to-digital converter comprising:

the comparator comprises a first input end, a second input end and an output end, wherein a bottom plate switch S is arranged between the first input end and the second input end _{w_bottom} ；

The sampling hold unit comprises a first capacitor connected with the first input end of the comparator, a first switch array connected with the first capacitor, a second capacitor connected with the first input end of the comparator and a second switch array connected with the second capacitor;

the capacitance mismatch calibration circuit comprises a low-order capacitance calibration array, a low-order switch array connected with the low-order capacitance calibration array, a high-order switch array connected with the high-order calibration array, and a bridge capacitor, wherein the high-order capacitance calibration array is connected with a first input end of the comparator, the bridge capacitor is electrically connected between the low-order capacitance calibration array and the high-order capacitance calibration array, and the capacitance value of the bridge capacitor is alpha x C _{c_cal} Alpha is more than 1, alpha is redundancy coefficient, C _{c_cal} The capacitance value of the ideal bridging capacitor;

the control logic unit is used for outputting first control logic for controlling the first switch array and outputting second control logic for controlling the low-order switch array and the high-order switch array so as to calibrate the low-order capacitance calibration array and the high-order capacitance calibration array.

In one embodiment, the first switch array is used for controlling the first capacitor and the input voltage signal V _IN Or a reference voltage high level V _REFP Or reference voltage low level V _REFN The second switch array is used for controlling the second capacitor and the input voltage signal V _IN Or a reference voltage high level V _REFP Or reference voltage low level V _REFN Are connected.

In an embodiment, the low-order calibration capacitor array includes a plurality of third capacitors, and the high-order calibration capacitor array includes a plurality of fourth capacitors;

the first polar plate of the third capacitor is respectively connected with the first polar plate of the bridging capacitor, the second polar plate is respectively connected with the low-level switch array, the first polar plate of the fourth capacitor is respectively connected with the second polar plate of the bridging capacitor and the first input end of the comparator, and the second polar plate is respectively connected with the high-level switch array;

the low-level switch array is used for controlling the third capacitor and the high level V of the reference voltage _REFP Or reference voltage low level V _REFN The high-order switch array is used for controlling the fourth capacitor to be connected withHigh level V of reference voltage _REFP Or reference voltage low level V _REFN Are connected.

In one embodiment, the low order calibration capacitor array and the high order calibration capacitor array are binary capacitor arrays.

In one embodiment, the capacitance value of the third capacitor in the low-order calibration capacitor array is 2 ^L-1 C _{u_cal} The capacitance value of the fourth capacitor in the high-order calibration capacitor array is 2 ^M-1 C _{u_cal} L and M are the numbers of the third capacitor and the fourth capacitor respectively.

In one embodiment, the bridge capacitor has a capacitance ofWherein C is _{tota4_Lside} Is the equivalent weight of all third capacitances.

In one embodiment, the successive approximation analog-to-digital converter comprises:

sampling phase, bottom plate switch S _{w_bottom} Closing, the first switch array controls the first capacitor and the reference voltage to be at a high level V _REFP The second switch array controls the second capacitor to be connected with the reference voltage low level V _REFN The second control logic is a first preset configuration of the low-level switch array and the high-level switch array;

phase conversion, bottom plate switch S _{w_bottom} The first switch array controls the first capacitor to be disconnected with the low level V of the reference voltage _REFN The second switch array controls the second capacitor to be connected with the high level V of the reference voltage _REFP The control logic unit outputs a second control logic to control the low-order switch array and the high-order switch array under the conversion phase, and the output voltage V of the comparator is enabled based on a successive approximation control algorithm _X Approaching 0, a calibration configuration is obtained.

In one embodiment, the switching phase includes:

high-order calibration, fixing the low-order capacitance calibration array to a second preset configuration, wherein the second preset configuration is the sum of ideal configuration and preset offset, and setting 1 and 1 to the high-order capacitance calibration array bit by bit based on a successive approximation control algorithmAccording to the output voltage V of the comparator _X Obtaining corresponding high-order calibration configuration bit by bit;

low-order calibration, fixing the high-order capacitance calibration array in high-order calibration configuration, setting 1 for the low-order capacitance calibration array bit by bit based on successive approximation control algorithm, and according to the output voltage V of the comparator _X And acquiring the corresponding low-order calibration configuration bit by bit.

In an embodiment, the control logic unit is further configured to:

obtaining a final high-order calibration configuration after taking an average value according to the multiple high-order calibration configurations; and/or the number of the groups of groups,

and obtaining a final low-order calibration configuration after taking an average value according to the multiple low-order calibration configurations.

Compared with the prior art, the invention has the following advantages:

the invention introduces the redundancy coefficient alpha into the bridge capacitor to increase the total weight of the low-order capacitor, ensure that the total weight of the low-order capacitor is larger than the weight of the lowest-order capacitor of the high-order capacitor, and solve the problem that the capacitor cannot be calibrated under the condition of mismatch;

and a preset offset is introduced in the calibration process, so that the compensation is performed through low bits under the condition that the high-bit calibration is wrong, and the requirements on nonlinearity and noise in the calibration process are reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and other drawings may be obtained according to the drawings without inventive effort to those skilled in the art.

FIG. 1 is a circuit diagram of a successive approximation type analog-to-digital converter according to the prior art;

FIG. 2 is a circuit diagram of a prior art successive approximation analog-to-digital converter based on a binary capacitive calibration array;

FIG. 3 is a circuit diagram of a successive approximation analog-to-digital converter based on a binary capacitive calibration array according to the present invention;

FIG. 4 is an equivalent circuit diagram of the binary capacitor calibration array of FIG. 3 and first and second capacitors;

FIG. 5 is a circuit diagram of a successive approximation analog-to-digital converter based on a capacitance mismatch calibration circuit (with redundancy coefficient α) according to the present invention;

FIG. 6 is a circuit diagram of a successive approximation analog-to-digital converter based on a capacitance mismatch calibration circuit (without redundancy factor α, CDAC bit number 4+4bit) according to the present invention;

fig. 7 is a circuit diagram of a successive approximation analog-to-digital converter based on a capacitance mismatch calibration circuit (with redundancy factor α, CDAC bit number 4+4bit) according to the present invention.

Detailed Description

The present invention will be described in detail below with reference to the embodiments shown in the drawings. The embodiments are not intended to limit the invention, but structural, methodological, or functional modifications of the invention from those skilled in the art are included within the scope of the invention.

Referring to FIG. 2, there is shown a successive approximation analog-to-digital converter of the binary-based capacitor calibration array CDAC_cal of the present invention, illustrating its calibration principle by the simplest 4-bit binary CDAC, wherein the capacitor to be calibrated is C ₀ The goal is C after calibration ₀ Equal to C _TARGET 。

During calibration, the sampling phase, S1 switch is connected to the reference voltage at high level V _REFP S0 switch is connected to reference voltage low level V _REFN =0, reference voltage low level V _REFN Typically ground potential (0V), bottom plate switch S _{w_bottom} Closing. The capacitor calibration array CDAC_cal is connected to the intermediate level 4' b1000 output by the control logic module, corresponding to S3_cal connected to V _REFP S2_cal, s1_cal, s0_cal connect V _REFN 。

Then enter into the phase conversion, bottom plate switch S _{w_bottom} First break, S1 switch is connected to V _REFN S0 switch is connected to V _REFP . Ideally, if C ₀ Equal to C _TARGET Output voltage V of the comparator after switching _X ＝0；V _X Is proportional to the magnitude of the mismatch of the two capacitances. Thus, V can be dequantized by calibrating CDAC _X By successive approximation to change the input of CDAC such that V _X The voltage approaches 0.

As shown in fig. 3, the capacitor calibration array cdac_cal is equivalent to a capacitor having a size of c_cal_eq as a whole, and the input voltage is 0 at the time of sampling and the vcal_eq voltage is input at the time of switching.

C _{cal_eq} ＝(2 ^L -1)C _{u_cal} ＝15C _{u_cal} ；

Where dout_samp=4' b1000=8, dout_conv is the control input signal value of the transfer phase switch. Thus, it can be seen that V_cal_eq may be greater than 0, less than 0, or equal to 0, corresponding to C ₀ Greater than C _TARGET 、C ₀ Less than C _TARGET And C ₀ Equal to C _TARGET In this case, calibration can be performed.

It can be calculated that if the switch of the capacitor calibration array cdac_cal is not switched, dout_conv=dout_samp=4' b1000, v at the switching phase _COMP The voltage seen is Vx:

C _total ＝C _target +C ₀ +C _{cal_eq}

changing the input code of the capacitive calibration array CDAC_cal so that the capacitive calibration array CDAC_cal is at V _COMP A voltage is generated to cancel the voltage difference created by the previous capacitance mismatch.

The input to the switch is recorded as Dout cal trim at this time.

In the normal working state of the analog-digital converter, C ₀ When the voltage is turned from 0 to 1, the voltage input by the corresponding comparator is:

at this time, a step voltage-V is also generated at the comparator input by the capacitor calibration array CDAC_cal _{CDAC_cal} Then the voltage at the comparator input changes to:

thus, through calibration, let C ₀ Voltage and C at 0 to 1 inversion _TARGET Is the same.

The specific operation method is as follows:

1. sampling phase, calibrating CDAC input code to intermediate code 4' b1000;

2. calibrating the input code of CDAC to sum C ₀ Is flipped in synchronization with the input code of (a). When C ₀ When input is connected to 1, calibrate CDAC input to 4' b1000; when C ₀ When the input is 0, the calibration CDAC input is Dout_cal_trim; then when C ₀ When flipped from 0 to 1, the equivalent calibrated CDAC produces-V _{CDAC_cal} A voltage.

As described in the background, the calibration of the prior art only increases the capacitance C _TARGET But if C _TARGET Inherent specific capacitance C ₀ If the calibration is large, the specific Trim value cannot be found, so that the calibration fails; in addition, if the number of bits of the capacitance calibration array is relatively large, the calibration capacitance itself has a problem of nonlinearity, and there is a high probability of calibration failure.

Referring to fig. 4, a successive approximation analog-to-digital converter based on a capacitance mismatch calibration circuit according to the present invention includes:

the Comparator (COMP) comprises a first input end (-), a second input end (+) and an output end, wherein a bottom is arranged between the first input end and the second input endPolar plate switch S _{w_bottom} ；

A sample-and-hold unit including a first capacitor C connected to the first input terminal of the comparator ₀ And a first capacitor C ₀ A first switch array S1 connected with the first input end of the comparator and a second capacitor C connected with the first input end of the comparator _TARGET And a second capacitor C _TARGET A second switch array S0 connected;

the capacitance mismatch calibration circuit comprises a low-order capacitance calibration array, a low-order switch array connected with the low-order capacitance calibration array, a high-order switch array connected with the high-order calibration array, and a bridge capacitor, wherein the high-order capacitance calibration array is connected with a first input end of the comparator, the bridge capacitor is electrically connected between the low-order capacitance calibration array and the high-order capacitance calibration array, and the capacitance value of the bridge capacitor is alpha x C _{c_cal} Alpha is more than 1, alpha is redundancy coefficient, C _{c_cal} The capacitance value of the ideal bridging capacitor;

the control logic unit is used for outputting first control logic for controlling the first switch array S1 and outputting second control logic for controlling the low-order switch array and the high-order switch array so as to calibrate the low-order capacitance calibration array and the high-order capacitance calibration array.

Specifically, the first switch array S1 is used to control the first capacitor C ₀ And input voltage signal V _IN Or a reference voltage high level V _REFP Or reference voltage low level V _REFN A second switch array S0 for controlling the second capacitor C _TARGET And input voltage signal V _IN Or a reference voltage high level V _REFP Or reference voltage low level V _REFN Are connected.

The low-order calibration capacitor array comprises a plurality of third capacitors, and the high-order calibration capacitor array comprises a plurality of fourth capacitors. The first polar plate of the third capacitor is connected with the first polar plate of the bridging capacitor respectively, the second polar plate is connected with the low-order switch array respectively, the first polar plate of the fourth capacitor is connected with the second polar plate of the bridging capacitor and the first input end of the comparator respectively, and the second polar plate is connected with the high-order switch array respectively. The low-level switch array is used for controlling the third capacitor and the referenceHigh voltage level V _REFP Or reference voltage low level V _REFN The high-order switch array is used for controlling the fourth capacitor to be high-level V with reference voltage _REFP Or reference voltage low level V _REFN Are connected.

In this embodiment, the low-order calibration capacitor array and the high-order calibration capacitor array are binary capacitor arrays, and the capacitance value of the third capacitor in the low-order calibration capacitor array is 2 ^L-1 C _{u_cal} C, i.e _{u_cal} 、2C _{u_cal} 、4C _{u_cal} 、…2 ^L-1 C _{u_cal} The capacitance value of the fourth capacitor in the high-order calibration capacitor array is 2 ^M-1 C _{u_cal} C, i.e _{u_cal} 、2C _{u_cal} 、4C _{u_cal} 、…2 ^M-1 C _{u_cal} L and M are the numbers of the third capacitor and the fourth capacitor respectively.

The capacitance of the bridging capacitor in this embodiment isWherein C is _{total_Lside} Is the equivalent weight of all third capacitances.

As shown in fig. 5, the binary calibration capacitor array CDAC without redundancy coefficients can be equivalent to a binary CDAC array of l+mbit, but the following conditions are satisfied:

first, if it is necessary to ensure that the equivalent weight of the capacitance of the low-order Lside has an exact binary relationship with the high-order capacitance, C can be calculated _{c_cal} The conditions that the capacitance needs to satisfy:

C _{total_Lside} ＝(2 ^L -1)C _{u_cal} ；

can calculate C under ideal condition _{c_cal} ＝C _{u_cal} . But actually due to the presence of parasitic capacitance C _p1 And C _p2 Thus, the actual C can be calculated _{c_cal} The method comprises the following steps:

C _{total_Lside} ＝(2 ^L -1)C _{u_cal} +C _P1 ；

when the values of L and M are large, for example, L >5 and l+m >10, the non-ideal factor of the calibration capacitor itself is difficult to be realized through layout matching, so that the linearity of the analog-to-digital converter is poor, and the calibration yield is affected.

Because, to ensure that a code is correctly generated within the entire calibration code, it is necessary to find a code corresponding to the correct V _{CDAC_cal} By modifying the calibrated CDAC to a CDAC that is not binary with redundancy. The method is to modify C _{c_cal} So that it is larger than the ideal C _{c_cal} Alpha times (alpha)>1, ex: α=1.3). Thus, the total weight of the CDAC of the low-order L bit is increased by alpha times, thereby ensuring that even if the high-order capacitor has mismatch, the part of the weight of the low-order capacitor with more low-order capacitor can be complemented, namely the capacitance value of the bridge capacitor is

The calibration process of the successive approximation analog-to-digital converter in the invention is divided into a sampling phase and a conversion phase:

sampling phase, bottom plate switch S _{w_bottom} Closing, the first switch array controls the first capacitor and the reference voltage to be at a high level V _REFP The second switch array controls the second capacitor to be connected with the reference voltage low level V _REFN The second control logic is a first preset configuration of the low-level switch array and the high-level switch array;

phase conversion, bottom plate switch S _{w_bottom} The first switch array controls the first capacitor to be disconnected with the low level V of the reference voltage _REFN The second switch array controls the second capacitor to be connected with the high level V of the reference voltage _REFP The control logic unit outputs a second control logic to control the low-order switch array and the high-order switch array under the conversion phase, and the output of the comparator is enabled based on a successive approximation control algorithmVoltage V _X Approaching 0, a calibration configuration is obtained.

The switching phase includes:

high-order calibration, fixing the low-order capacitance calibration array to a second preset configuration, wherein the second preset configuration is the sum of ideal configuration and preset offset, setting 1 for the high-order capacitance calibration array bit by bit based on a successive approximation control algorithm, and according to the output voltage V of a comparator _X Obtaining corresponding high-order calibration configuration bit by bit;

low-order calibration, fixing the high-order capacitance calibration array in high-order calibration configuration, setting 1 for the low-order capacitance calibration array bit by bit based on successive approximation control algorithm, and according to the output voltage V of the comparator _X And acquiring the corresponding low-order calibration configuration bit by bit.

The control logic unit is further configured to:

obtaining a final high-order calibration configuration after taking an average value according to the multiple high-order calibration configurations; and/or the number of the groups of groups,

and obtaining a final low-order calibration configuration after taking an average value according to the multiple low-order calibration configurations.

Referring to FIG. 6, in this embodiment, the capacitance values of the low-order capacitors are C respectively, taking 4+4bit CDAC as an example _{u_cal} 、2C _{u_cal} 、4C _{u_cal} 、8C _{u_cal} The capacitance values of the high-order capacitors are respectively C by the control of the low-order switches S0_cal, S1_cal, S2_cal and S3_cal _{u_cal} 、2C _{u_cal} 、4C _{u_cal} 、8C _{u_cal} Controlled by low-level switches s4_cal, s5_cal, s6_cal, s7_cal, respectively.

The calibration process is divided into sampling phase and conversion phase:

sampling phase, bottom plate switch S _{w_bottom} The first switch array S1 is closed to control the first capacitor C0 and the reference voltage high level V _REFP Connected with the second switch array S0 to control the second capacitor C _TARGET Low level V with reference voltage _REFN The second control logic is a first preset configuration of the low-order switch array and the high-order switch array, in this embodiment, the intermediate level is 8' b10000000, corresponding to S7_cal connected to V _REFP S6_cal to s0_cal are connected to V _REFN 。

Phase conversion, bottom plate switch S _{w_bottom} The first switch array S1 controls the first capacitor C to be disconnected ₀ Low level V with reference voltage _REFN Connected with the second switch array S0 to control the second capacitor C _TARGET High level V with reference voltage _REFP Are connected. Under the conversion phase, the control logic unit outputs a second control logic to control the low-order switch array and the high-order switch array, the CDAC is calibrated bit by bit based on a successive approximation control algorithm, and then the output voltage V is judged by the comparator _X Whether the voltage is greater than 0. According to the output of the comparator, the input bit of the CDAC is sequentially determined from high order to low order, and the output voltage V of the comparator is finally made through continuous approximation _X Approaching 0.

For the first comparison, calibrate CDAC switch unchanged, S7_cal connects V _REFP S6_cal to s0_cal are each connected to V _REFN Then, the output voltage V of the comparator is judged _X Whether greater than 0. Suppose V _X Greater than 0, the comparator outputs 1'b0, representing the CDAC most significant bit connected to 1' b0, recording Dout_cal<7>=1' b0, the control logic controls the switch s7_cal of the calibration CDAC, switching s7_cal to V _REFN 。

Then to set 1' b1 for bit 2 of CDAC, control logic controls and calibrates switch S6_cal of CDAC to switch S6_cal to V _REFP Then, the output voltage V of the comparator is judged _X Whether greater than 0. If V is _X Less than 0, the comparator outputs 1'b1, representing CDAC next higher order 1' b1, record Dout_cal<6>=1' b1, the control logic controls the switch s6_cal of the calibration CDAC, switching s6_cal to V _REFP 。

Next, 1' b1 is set for the 3 rd bit of the CDAC, and the control logic controls the switch s5_cal of the CDAC to switch s5_cal to V _REFP Then, the output voltage V of the comparator is judged _X Whether greater than 0. Suppose V _X Less than 0, comparator outputs 1' b1, record dout_cal<5>=1' b1, the control logic controls the switch s5_cal of the calibration CDAC, switching s5_cal to V _REFP 。

Finally, for CDAC position 4, 1' b1, the control logic controls the switch S4_cal of the calibration CDAC to switch S4_cal to V _REFP Then, the output voltage V of the comparator is judged _X Whether greater than 0. Suppose V _X Less than 0, comparator outputs 1' b1, record dout_cal<4>=1' b1, the control logic controls the switch s4_cal of the calibration CDAC, switching s4_cal to V _REFP 。

Thus, dout_cal <7:4> =4' b0111 is obtained, which is the calibration result of the high-order capacitance calibration array.

And then, continuing to calibrate the low-order capacitance calibration array by adopting the same process, and obtaining the Dout_cal <7:0> calibration result of the CDAC after the calibration is completed.

When the capacitance calibration accuracy requirement is high, noise in the circuit will become a major factor limiting the calibration accuracy. Therefore, the calibration accuracy can be improved by a method of averaging by calibration a plurality of times. During calibration, the high level and the low level are separately calibrated, the high level is calibrated for N times, N times of results of Dout_cal <7:4> are recorded, the final high level calibration result is obtained by averaging, the low level is calibrated for M times, M times of results of Dout_cal <3:0> are recorded, and the final low level calibration result is obtained by averaging.

During calibration, the low order bits are first fixed at the second predetermined configuration (ideal code 4' b 0000) plus a predetermined offset. For example, taking the preset offset as 2LSB, the lower bit inputs 4' b0010. Because of this offset, even in the case of an error in the high-order calibration, the low-order can be compensated as long as the error is within the offset.

For example, if the correct calibration result should be 8' b1001,1111. But the high order comparison is wrong, becomes 4' b1010, then the low order can be only 4' b0000 at minimum, so the final result 8' b1010,0000 produces an error of 1 LSB.

And after the low order bit adds the offset of 2LSB, if the high order bit has errors, because the low order bit is 4' b0010 at first, the low order bit can be adjusted to 4' b0001 or 4' b0000 to equivalently generate the effect of-1 LSB or-2 LSB, and the errors introduced by the comparison errors of the high order bit at first are compensated. The larger the offset value, the larger the range that can be compensated for. However, the offset cannot be too large, if the value of α is multiplied by the total low weight, then when there is mismatch in the capacitance, the added redundancy of α cannot be used, and linearity errors occur in CDAC.

The specific calibration procedure after the offset is introduced is as follows:

capacitance to be calibrated is C ₀ The goal is C after calibration ₀ Equal to C _TARGET 。

In calibration, the S1 switch is connected to V _REFP S0 switch is connected to V _REFN =0, bottom plate switch S _{w_bottom} Closing. The CDAC calibration array receives the intermediate level 8' b10000010 of the CDAC output corresponding to S7_cal, S1_cal receiving V _REFP S6_cal to s2_cal, s0_cal is connected to V _REFN 。

In the high-order calibrated switching phase, bottom plate switch S _{w_bottom} First break, S1 switch is connected to V _REFN S0 switch is connected to V _REFP 。

First comparison, calibrate CDAC switch unchanged, S7_cal and S1_cal are connected with V _REFP S6_cal to s2_cal, s0_cal to V _REFN . Then judging the output voltage V of the comparator _X Whether greater than 0. Suppose V _X Greater than 0, the comparator outputs 1'b0, representing the CDAC most significant bit connected to 1' b0, recording Dout_cal<7>=1' b0, the control logic controls the switch s7_cal of the calibration CDAC, switching s7_cal to V _REFN 。

Then the 1' b1 is set for the 2 nd bit of the high-order CDAC, the control logic controls the switch S6_cal of the calibration CDAC, and the switch S6_cal is switched to V _REFP Then, the output voltage V of the comparator is judged _X Whether greater than 0. If V is _X Less than 0, the comparator outputs 1'b1, representing CDAC next higher order 1' b1, record Dout_cal<6>=1' b1, the control logic controls the switch s6_cal of the calibration CDAC, switching s6_cal to V _REFP 。

Next, for the 3 rd bit of the high-order CDAC, the 1' b1 is set, and the control logic controls the switch S5_cal of the calibration CDAC to switch S5_cal to V _REFP Then, the output voltage V of the comparator is judged _X Whether greater than 0. Suppose V _X Less than 0, comparator outputs 1' b1, record dout_cal<5>=1' b1, control logic controls calibrationSwitch s5_cal of CDAC, switch s5_cal to V _REFP 。

Finally, for the 4 th position 1' b1 of the high-order CDAC, the control logic controls the switch S4_cal of the calibration CDAC to switch S4_cal to V _REFP Then, the output voltage V of the comparator is judged _X Whether greater than 0. Suppose V _X Less than 0, comparator outputs 1' b1, record dout_cal<4>=1' b1, the control logic controls the switch s4_cal of the calibration CDAC, switching s4_cal to V _REFP 。

Thus, dout_cal <7:4> =4' b0111 is obtained. This value, averaged, is then repeated N times, the calibration result of the higher CDAC.

The low calibration procedure is similar, except that in low calibration, dout_cal <7:4> obtained by high calibration is substituted into the conversion stage.

Capacitance to be calibrated is C ₀ The goal is C after calibration ₀ Equal to C _TARGET 。

In calibration, the S1 switch is connected to V _REFP S0 switch is connected to V _REFN =0, bottom plate switch S _{w_bottom} Closing. The CDAC calibration array receives the intermediate level 8' b10000010 of the CDAC output corresponding to S7_cal and S1_cal receiving V _REFP S6_cal to s2_cal, s0_cal to V _REFN 。

In the low-level calibrated switching phase, bottom plate switch S _{w_bottom} First break, S1 switch is connected to V _REFN S0 switch is connected to V _REFP . S7_cal-S4_cal input the Dout_cal obtained by the high-order calibration before<7:4>。

For the first comparison, the 1 st bit of the low-order CDAC is set to 1' b1, the control logic controls the switch S3_cal of the calibration CDAC, and the switch S3_cal is switched to V _REFP S2_cal to s0_cal are connected to V _REFN . Then judging the output voltage V of the comparator _X Whether greater than 0. Suppose V _X Greater than 0, the comparator outputs 1'b0, representing the CDAC most significant bit connected to 1' b0, recording Dout_cal<3>=1' b0, the control logic controls the switch s3_cal of the calibration CDAC, switching s3_cal to V _REFN 。

Then the 1' b1 is set for the 2 nd bit of the low-order CDAC, and the control logic controlsCalibrating switch S2_cal of CDAC, switching S2_cal to V _REFP Then, the output voltage V of the comparator is judged _X Whether greater than 0. Suppose V _X Less than 0, the comparator outputs 1'b1, representing CDAC next higher order 1' b1, record Dout_cal<2>=1' b1, the control logic controls the switch s2_cal of the calibration CDAC, switching s2_cal to V _REFP 。

Next, for the 3 rd bit of the low-order CDAC, the 1' b1 is set, and the control logic controls the switch S1_cal of the calibration CDAC to switch S1_cal to V _REFP Then, the output voltage V of the comparator is judged _X Whether greater than 0. Assuming that Vx is less than 0, the comparator outputs 1' b1, recording dout_cal<1>=1' b1, the control logic controls the switch s1_cal of the calibration CDAC, switching s1_cal to V _REFP 。

Finally, for the 4 th position 1' b1 of the low-order CDAC, the control logic controls the switch S0_cal of the calibration CDAC to switch S0_cal to V _REFP Then, the output voltage V of the comparator is judged _X Whether greater than 0. Suppose V _X Less than 0, comparator outputs 1' b1, record dout_cal<0>=1' b1, the control logic controls the switch s0_cal of the calibration CDAC, switching s0_cal to V _REFP 。

Thus, dout_cal <3:0> =4' b0111 is obtained. This value, averaged, is then repeated M times, the calibration result of the lower CDAC.

And finally, combining the high-order CDAC calibration result and the low-order CDAC calibration result to obtain a final calibration result.

The technical scheme shows that the invention has the following beneficial effects:

the invention introduces the redundancy coefficient alpha into the bridge capacitor to increase the total weight of the low-order capacitor, ensure that the total weight of the low-order capacitor is larger than the weight of the lowest-order capacitor of the high-order capacitor, and solve the problem that the capacitor cannot be calibrated under the condition of mismatch;

and a preset offset is introduced in the calibration process, so that the compensation is performed through low bits under the condition that the high-bit calibration is wrong, and the requirements on nonlinearity and noise in the calibration process are reduced.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment contains only one independent technical solution, and that such description is provided for clarity only, and that the technical solutions of the embodiments may be appropriately combined to form other embodiments that will be understood by those skilled in the art.

Claims (8)

1. A successive approximation analog-to-digital converter based on a capacitance mismatch calibration circuit, the analog-to-digital converter comprising:

the comparator comprises a first input end, a second input end and an output end, wherein a bottom plate switch S is arranged between the first input end and the second input end _{w_bottom} ；

The sampling hold unit comprises a first capacitor connected with the first input end of the comparator, a first switch array connected with the first capacitor, a second capacitor connected with the first input end of the comparator and a second switch array connected with the second capacitor;

the capacitance mismatch calibration circuit comprises a low-order capacitance calibration array, a low-order switch array connected with the low-order capacitance calibration array, a high-order switch array connected with the high-order capacitance calibration array, and a bridge capacitor, wherein the high-order capacitance calibration array is connected with a first input end of the comparator, the bridge capacitor is electrically connected between the low-order capacitance calibration array and the high-order capacitance calibration array, and the capacitance value of the bridge capacitor is alpha x C _{c_cal} Alpha is more than 1, alpha is redundancy coefficient, C _{c_cal} The capacitance value of the ideal bridging capacitor;

the control logic unit is used for outputting first control logic for controlling the first switch array and outputting second control logic for controlling the low-order switch array and the high-order switch array so as to calibrate the low-order capacitance calibration array and the high-order capacitance calibration array;

the successive approximation analog-to-digital converter comprises:

sampling phase, bottom plate switch S _{w_bottom} Closing, the first switch array controls the first capacitor and the reference voltage to be at a high level V _REFP The second switch array controls the second capacitor to be connected with the reference voltage low level V _REFN The second control logic is a first preset configuration of the low-level switch array and the high-level switch array;

phase conversion, bottom plate switch S _{w_bottom} The first switch array controls the first capacitor to be disconnected with the low level V of the reference voltage _REFN The second switch array controls the second capacitor to be connected with the high level V of the reference voltage _REFP The control logic unit outputs a second control logic to control the low-order switch array and the high-order switch array under the conversion phase, and the output voltage V of the comparator is enabled based on a successive approximation control algorithm _X Approaching 0, a calibration configuration is obtained.

2. The successive approximation analog-to-digital converter based on the capacitance mismatch calibration circuit according to claim 1, wherein the first switch array is configured to control the first capacitance and the input voltage signal V _IN Or a reference voltage high level V _REFP Or reference voltage low level V _REFN The second switch array is used for controlling the second capacitor and the input voltage signal V _IN Or a reference voltage high level V _REFP Or reference voltage low level V _REFN Are connected.

3. The successive approximation analog-to-digital converter based on a capacitance mismatch calibration circuit according to claim 1, wherein the low-order capacitance calibration array comprises a number of third capacitances and the high-order capacitance calibration array comprises a number of fourth capacitances;

the first polar plate of the third capacitor is respectively connected with the first polar plate of the bridging capacitor, the second polar plate is respectively connected with the low-level switch array, the first polar plate of the fourth capacitor is respectively connected with the second polar plate of the bridging capacitor and the first input end of the comparator, and the second polar plate is respectively connected with the high-level switch array;

the low-level switch array is used for controlling the third capacitor and the high level V of the reference voltage _REFP Or reference voltage low level V _REFN The high-order switch array is used for controlling the fourth capacitor to be high-level V with reference voltage _REFP Or reference voltage low level V _REFN Are connected.

4. A successive approximation analog-to-digital converter based on a capacitance mismatch calibration circuit according to claim 3, wherein the low-order capacitance calibration array and the high-order capacitance calibration array are both binary capacitance arrays.

5. The successive approximation analog-to-digital converter based on the capacitance mismatch calibration circuit according to claim 4, wherein the capacitance value of the third capacitor in the low-order capacitance calibration array is C in turn _{u_cal} 、2C _{u_cal} 、4C _{u_cal} 、…2 ^L-1 C _{u_cal} The capacitance value of the fourth capacitor in the high-order capacitor calibration array is C in turn _{u_cal} 、2C _{u_cal} 、4C _{u_cal} 、…2 ^M-1 C _{u_cal} L and M are the numbers of the third capacitor and the fourth capacitor respectively.

6. The successive approximation analog-to-digital converter based on a capacitance mismatch calibration circuit according to claim 5, wherein the capacitance of the bridge capacitor is。

7. The successive approximation analog-to-digital converter based on a capacitance mismatch calibration circuit according to claim 1, wherein the conversion phase comprises:

high-order calibration, fixing the low-order capacitance calibration array to a second preset configuration, wherein the second preset configuration is the sum of ideal configuration and preset offset, setting 1 for the high-order capacitance calibration array bit by bit based on a successive approximation control algorithm, and according to the output voltage V of a comparator _X Obtaining corresponding high-order calibration configuration bit by bit;

low-order calibration, fixing the high-order capacitance calibration array in high-order calibration configuration, setting 1 for the low-order capacitance calibration array bit by bit based on successive approximation control algorithm, and according to the output voltage V of the comparator _X And acquiring the corresponding low-order calibration configuration bit by bit.

8. The capacitance mismatch calibration circuit based successive approximation analog to digital converter according to claim 7, wherein the control logic unit is further configured to:

obtaining a final high-order calibration configuration after taking an average value according to the multiple high-order calibration configurations; and/or the number of the groups of groups,

and obtaining a final low-order calibration configuration after taking an average value according to the multiple low-order calibration configurations.