CN111627923A - Semiconductor structure - Google Patents

Abstract

A semiconductor structure, comprising a first metal layer in which a first source-drain region, a first gate region, a second gate region, and a second source-drain region, which are sequentially arranged in a longitudinal direction, are patterned in the first metal layer , the patterned gate and the source and drain are in the same horizontal position, and also includes a first insulating layer, the first insulating layer is covered on the patterned gate layer and the source and drain layers, and the first insulating layer also includes Through holes, the through holes of the first insulating layer include a first through hole on the first source and drain regions, a second through hole on the second gate region, and a third through hole on the second source and drain regions and fourth through hole. The above technical solution combines the gate metal and the source-drain metal in the same layer, performs patterned wiring in the first metal layer, and connects the second metal layer on the first metal layer through through holes and via holes. gate and source drain. Thereby, the effect of reducing the number of masks in the manufacturing process is achieved.

Description

a semiconductor structure

technical field

The invention relates to a design scheme of a thin film transistor, in particular to a light-emitting semiconductor structure and a fabrication method capable of integrating a gate layer and a source and drain layer to save a mask process.

Background technique

The basic structure of a thin film transistor (TFT) currently used in a display panel generally includes a first metal layer gate GE, a first insulating layer GI, a semiconductor active layer SE, a second metal layer source and drain SD, a second insulating layer PV, And the pixel electrode PE, a total of 6 masks. In order to improve device stability, designers also add an etch stop layer ESL after SE patterning to protect it from additional damage during SD process.

On this basis, TFT has derived many improved directions, including adding additional layers to obtain other functions or improve device performance. There is also a reduction in the number of masks to reduce production costs and shorten the construction period. The most common is to remove the film layer with the ESL structure to make it a BCE structure to reduce costs, but the performance is usually reduced, or the same mask is used. or self-alignment to reduce the number of reticle, but the number of layers is usually unchanged.

SUMMARY OF THE INVENTION

To this end, it is necessary to provide a new TFT process design to solve the problem of complex processes in the prior art.

In order to achieve the above object, the inventor provides a semiconductor structure, which includes a first metal layer, in which a first source-drain region, a first gate region, and a second gate are patterned longitudinally and sequentially arranged in the first metal layer. region, and the second source and drain regions, the patterned gate and the source and drain are at the same horizontal position, and also includes a first insulating layer, the first insulating layer wraps the patterned gate layer and the source and drain layers Above, the first insulating layer further includes a through hole, and the through hole of the first insulating layer includes a first through hole on the first source and drain regions, a second through hole on the second gate region, and a second source and drain the third through hole and the fourth through hole on the pole region;

The first insulating layer also includes a semiconductor layer, including a first semiconductor region on the first gate region and a second semiconductor region on the second gate region, and a second insulating layer is also provided above the semiconductor layer, and the second insulating layer It also includes a via hole, the via hole on the second insulating layer includes a first via hole connecting the first source and drain regions and the first semiconductor region, and a second via hole connecting the first semiconductor region and the first gate region. The third via hole and the fourth via hole on the two semiconductor regions; and the fifth and sixth via holes on the second source and drain regions, wherein the first via hole covers the first via hole, and the second via hole covers the second via hole through holes, the fifth through hole covers the third through hole, and the sixth through hole covers the fourth through hole, all of which expose the first metal layer and the semiconductor layer;

A second metal layer is further disposed above the second insulating layer, and the second metal layer includes a part of the film layer covering the first source-drain region, the second source-drain region and the third via hole on the second semiconductor region; Another part of the film layer includes an area covering the first via hole and another area covering the second via hole; another film layer covers the second gate area and the sixth via hole; another part of the film layer covers the fourth via hole hole and fifth via.

Further, the second metal layer is a metal and ITO composite film layer.

Further, the first insulating layer is coated on the first metal layer.

Different from the prior art, the above technical solution combines the gate metal and the source-drain metal in the same layer, performs patterned wiring in the first metal layer, and the second metal layer on it through through holes and via holes. The gate and the source and drain of the first metal layer are connected. Thereby, the effect of reducing the number of masks in the manufacturing process is achieved. The ultimate goal is to save costs and reduce the economic burden.

Description of drawings

FIG. 1 is a schematic diagram of a first metal layer according to the embodiment 1;

FIG. 2 is a schematic diagram of the first insulating layer GI according to the scheme one of the specific embodiments;

FIG. 3 is a schematic diagram of the semiconductor layer SE of the scheme 1 described in the specific embodiment;

FIG. 4 is a schematic diagram of the second insulating layer PV according to the scheme one of the specific embodiments;

FIG. 5 is a schematic diagram of a second metal layer according to the embodiment 1;

6 is a schematic diagram of the first metal layer of the second solution according to the specific embodiment;

Fig. 7 is the schematic diagram of scheme 2 GI and SE described in the specific embodiment;

FIG. 8 is a schematic diagram of the second insulating layer PV of the second solution according to the specific embodiment.

FIG. 9 is a schematic diagram of the second metal layer according to the second embodiment of the invention.

Detailed ways

In order to describe in detail the technical content, structural features, achieved objectives and effects of the technical solution, the following detailed description is given in conjunction with specific embodiments and accompanying drawings.

Please refer to FIG. 1 , a transistor structure includes a first metal layer. The gate GE and the source and drain SD are patterned in the first metal layer. Since the metal layer of the same layer is patterned, the patterned gate At the same level as the source and drain. Please refer to Figure 2 here, which also includes a first insulating layer GI. The first insulating layer can be coated on the patterned gate layer and the source and drain layers by means of evaporation or electroplating, so it is not reflected in the figure. . Then, the first insulating layer further includes a through hole (the circular portion DChole in the figure), and as shown in FIG. 3 , we can further set a semiconductor active layer SE on the first insulating layer GI, which can also be called a semiconductor layer. The portion of the semiconductor layer vertically above the gate layer needs to be set slightly wider than the gate traces. A second insulating layer PV is also arranged above the semiconductor layer as shown in FIG. 4 , and the second insulating layer also includes via holes. (block part in the figure). Further as shown in FIG. 5 , a second metal layer is further disposed above the second insulating layer, and the second metal layer is connected to the gate metal or the source-drain metal wiring through the through hole and the via hole. The second metal layer is a metal and ITO composite film layer.

Hereinafter, we will introduce the first solution structure in detail with the examples of Figs. 1-5. Fig. 1 to Fig. 5 are the first embodiment of this patent.

FIG. 1 is a schematic diagram of the patterning of the first metal layer in the first solution, and the plane of the paper is parallel to the plane of the substrate. Including GE traces and SD traces, GE and SD are patterns etched from the same metal layer, and the trace functions are only distinguished by different grayscales, including the first source and drain regions SD1 arranged in sequence along the longitudinal direction of the paper, the first The gate region GE, the third source-drain region and the second source-drain region SD2. The film can be made of Mo, Al, Ti, Cu, Ag, W and other metals or their composite films.

Figure 2 shows the GI coating and patterning of the first insulating layer in the first solution, that is, opening a DC hole, which is represented by a black circle. We can see that the first source and drain regions and the second source and drain regions in the figure are respectively A first through hole and a second through hole are opened, and a third through hole and a fourth through hole are opened in the third source and drain regions. The film layer can use SiOx, SiNx, AlOx or other insulating substances and their composite films as the insulating layer.

Figure 3 shows the SE coating and patterning of the semiconductor active layer in Scheme 1, wherein the SE width on the GE should cover the lower GE, and the film layer can be a-Si, MOS (metal oxide semiconductor), LTPS, etc. as the active layer. The semiconductor active layer in the source and drain regions should cover the second through hole and the third through hole.

Fig. 4 shows the PV coating and patterning of the second insulating layer of the first solution, which are represented by black rectangles and squares. The corresponding positions of the PV are opened to ensure that the second metal layer can contact the first metal layer or the active layer, specifically , the vias on the second insulating layer include the first vias connecting the first vias and the semiconductor layer on the gate region; and the second vias on the semiconductor layer on the gate region; and the fourth vias the third via. The film layer can use SiOx, SiNx, AlOx, organic film layer or other insulating material and its composite film layer as the insulating layer.

FIG. 5 shows the coating and patterning of the second metal layer PE of the first solution, including bridge wiring, capacitors and pixel electrodes. Usually, the film layer is ITO or a composite film layer of metal and ITO or other metals and alloys. As shown in the semi-transparent structure on the right side of Figure 5: a is the pixel electrode part, this part of the film layer is connected to the third via hole and covers the first source and drain regions and the first gate region; b is the bottom gate structure TFT1, which Part of the film layer covers the first via. The PV hole (first via hole) and the DC hole (first via hole) are respectively connected to the SD1 (first source and drain region) line and the TFT2 and the PE electrode of the capacitor; c is the capacitor, and this part of the film layer covers the second The source-drain region and the second via hole simultaneously cover the semiconductor active layer in the source-drain region covering the second via hole and the third via hole, and the dielectric film layers are GI and PV; d is the top gate structure TFT2, That is, the above-mentioned semiconductor active layer in the source and drain regions. Its GE is the metal of the PE film layer, the source and drain are connected to the SD2 wiring, and the SD2 bridge is connected to the pixel electrode.

Next, we will introduce the second scheme structure in detail with the example of Fig. 6-9. Fig. 6 to Fig. 9 are the second embodiment of this patent.

Figure 6 is a schematic diagram of the patterning of the first metal layer of the second solution, including GE traces and SD traces. GE and SD are patterns etched from the same metal layer, and the trace functions are only distinguished by different grayscales, including the traces along the paper surface. The first source-drain region SD1, the first gate region GE1, the second gate region GE2, and the second source-drain region SD2 are arranged in sequence in the longitudinal direction. The film layer can be made of Mo, Al, Ti, Cu, Ag, W and other metals or their composite film layer metals.

FIG. 7 shows the first insulating layer GI of the second solution, and GI is also formed on the gate region and the source and drain regions. At this time, the SE is patterned, wherein the width of the SE on the GE should cover the underlying GE, which can be seen to include the first semiconductor region on the first gate region and the second semiconductor region on the second gate region. The GI film can use SiOx, SiNx, AlOx or other insulating substances and their composite films as the insulating layer, and the SE film can use a-Si, MOS (metal oxide semiconductor), LTPS, etc. as the active layer. It can also be seen from the figure that the through holes of the first insulating layer include the first through holes on the first source and drain regions, the second through holes on the second gate region, and the second through holes on the second source and drain regions. The third through hole and the fourth through hole.

Fig. 8 shows the PV coating and patterning of the second insulating layer of the second solution, which is represented by black rectangles and squares. Via holes are opened at the corresponding positions of the PV to ensure that the second metal layer can contact the first metal layer or the active layer. The film layer can use SiOx, SiNx, AlOx, organic film layer or other insulating material and its composite film layer as the insulating layer. As can be seen from the figure, the via holes on the second insulating layer include a first via hole connecting the first source and drain regions and the first semiconductor region, and a second via hole connecting the first semiconductor region and the first gate region. holes, third via holes and fourth via holes on the second semiconductor region; and fifth and sixth via holes on the second source and drain regions. The first via hole covers the first via hole, the second via hole covers the second via hole, the fifth via hole covers the third via hole, and the sixth via hole covers the fourth via hole. exposed.

9 shows the coating and patterning of the second metal layer PE of the second solution, including bridge wiring, capacitors and pixel electrodes. Usually, the film layer is ITO or a composite film layer of metal and ITO or other metals and alloys. As shown in the semi-transparent structure on the right side of FIG. 9: a is the pixel electrode part, and this part of the film layer covers the first source-drain region, the second source-drain region and the third via hole on the second semiconductor region; b is the bottom The gate structure TFT1 is connected to the SD1 line and TFT2 and the GE electrode of the capacitor through the PV hole, where the PE film layer includes an area covering the first via hole and another area covering the second via hole; c is the capacitor, its The metal film layers are GE and PE respectively, and the PE electrode is connected to the SD2 line through the PV hole, where the PE film layer covers the second gate area and the sixth via hole, and the dielectric film layers are GI and PV; d is the bottom gate In the structure TFT2, the source and drain are connected to the SD2 wiring and the pixel electrode, and the PE film layer covering the fourth via hole and the fifth via hole is also included here.

Through the above design, the structure uses the semiconductor active layer and the second metal layer to form the wiring in a bridging manner. Compared with the traditional TFT, a metal film layer can be omitted, so the number of masks required and the process time will also be reduced. The number of basic masks required for one is 5, and the number of basic masks required for program two is 4.

In this patent, the film layers formed before and after the semiconductor active layer SE are all insulating layers. Compared with the common BCE structure, the number of masks can not only be reduced, but the insulating layer can also protect the SE from the metal film layer similar to ESL. The role of etching damage.

The design can be applied to the design of combining multiple TFTs and capacitors, and is also compatible with the design of driving a single TFT. The scheme 1 is also compatible with the implementation of the top-gate structure and the bottom-gate structure.

The main conductive traces in this design are 2 layers, so there is no need to consider the effect of electrodes other than GE and SD on SE.

e. By adjusting the material and structure of the pixel electrode film layer, this design can be compatible with LCD, OLED, QLED and other types of panels. When the PE film layer only uses ITO and the main display area is outside the metal traces, it can be suitable for backlight display panels, such as LCD and light-excited OLED and QLED, etc.; when the PE film layer uses a metal and ITO composite film layer, due to The pixel electrode has good reflectivity, so it can be applied to display devices such as self-luminous OLED and QLED or used as a sensing TFT.

A method for fabricating a transistor, comprising the steps of: patterning a gate and a source and drain in a first metal layer, wherein the gate and the source and drain are at the same horizontal position, and setting a first insulation on the gate and the source and drain layer, through holes are arranged at the first insulating layer, and then a semiconductor layer is arranged, the semiconductor layer is vertically above the gate layer, a second insulating layer is arranged above the semiconductor layer, and via holes are arranged in the second insulating layer and a second metal layer is arranged on the second insulating layer, and the second metal layer is connected to the gate metal and the source-drain metal wiring through the through hole and the via hole.

Specifically, the second metal layer is a metal and ITO composite film layer.

Further, the first insulating layer is coated on the first metal layer.

It should be noted that, although the above embodiments have been described herein, it does not limit the scope of the patent protection of the present invention. Therefore, based on the innovative concept of the present invention, changes and modifications to the embodiments described herein, or equivalent structures or equivalent process transformations made by using the contents of the description and drawings of the present invention, directly or indirectly apply the above technical solutions In other related technical fields, all are included within the scope of patent protection of the present invention.

Claims (3)

1. A semiconductor structure is characterized by comprising a first metal layer, a first source drain region, a first gate region, a second gate region and a second source drain region which are patterned in the first metal layer and longitudinally arranged in sequence, wherein the patterned gate and the source drain are positioned at the same horizontal position;

the first insulating layer further comprises a semiconductor layer, the semiconductor layer comprises a first semiconductor region on the first gate region and a second semiconductor region on the second gate region, a second insulating layer is further arranged above the semiconductor layer, the second insulating layer further comprises a through hole, the through hole on the second insulating layer comprises a first through hole communicated with the first source-drain region and the first semiconductor region, a second through hole communicated with the first semiconductor region and the first gate region, a third through hole and a fourth through hole on the second semiconductor region; the first through hole covers the first through hole, the second through hole covers the second through hole, the fifth through hole covers the third through hole, and the sixth through hole covers the fourth through hole, so that the first layer of metal and the semiconductor layer are exposed;

a second metal layer is further arranged above the second insulating layer, and the second metal layer comprises a part of film layer which covers the first source drain region, the second source drain region and a third through hole on the second semiconductor region; a part of the film layer comprises an area covering the first via hole and another area covering the second via hole; a film layer covers the second gate region and the sixth via hole; and partial film layers cover the fourth via hole and the fifth via hole.

2. The semiconductor structure of claim 1, wherein the second metal layer is a metal and ITO composite film layer.

3. The semiconductor structure of claim 1, wherein the first insulating layer is plated on the first metal layer.

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