CN111611101B - Method and device for adjusting flash memory read data throughput rate - Google Patents
Method and device for adjusting flash memory read data throughput rate Download PDFInfo
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- CN111611101B CN111611101B CN202010322810.4A CN202010322810A CN111611101B CN 111611101 B CN111611101 B CN 111611101B CN 202010322810 A CN202010322810 A CN 202010322810A CN 111611101 B CN111611101 B CN 111611101B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
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- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The technical scheme of the invention comprises a method and a device for adjusting the throughput rate of flash memory read data, which are applied to the stability of flash memory data storage and erasing, and comprise the following steps: the LDPC decoding unit is monitored in real time, iteration thresholds of the LDPC decoding unit for different data types are set, and real-time iteration times are acquired; comparing the obtained iteration times with the threshold iteration times of the LDPC, and adjusting the error distribution and the number of the flash memory based on different data types. The beneficial effects of the invention are as follows: the stability of the flash memory reading efficiency is ensured; and the LDPC iteration times are prevented from increasing to influence the system throughput rate.
Description
Technical Field
The invention relates to the field of data storage, in particular to a method and a device for adjusting the throughput rate of flash memory read data.
Background
At present, many flash memory controllers use LDPC error correction codes, and the decoding algorithm of LDPC is an iterative algorithm, and the iteration times are not fixed, so the decoding speed is not fixed. Generally, the number of iterations is related to the distribution and the number of errors, and the more the errors are, the more the number of iterations is, but for a certain number of errors, the error distribution can cause the change of the number of iterations, and the difference is not small. Errors with the use of flash memory, the errors are increasing, resulting in slower and slower decoding speeds.
Disclosure of Invention
The invention aims to at least solve one of the technical problems in the prior art, and provides a method for adjusting the throughput rate of flash memory read data, so as to stabilize the read rate of flash memory equipment.
The technical scheme of the invention comprises a method for adjusting the throughput rate of flash memory read data, which is characterized in that: s100, performing real-time monitoring on the LDPC decoding unit, setting iteration thresholds of the LDPC decoding unit for different data types, and collecting real-time iteration times; s200, comparing the iteration times obtained in the S100 with the threshold iteration times of LDPC, and adjusting error distribution and quantity of the flash memory based on different data types.
According to the method for adjusting the flash memory read data throughput rate, wherein S100 specifically comprises S110, setting the iteration number threshold of the LDPC decoding unit, and setting the iteration threshold of the key data and the common data; s120, if the decoded data is key data, executing the step S200 on the flash memory when the iteration number threshold is exceeded; if the decoded data is normal data, taking average decoding times of a plurality of normal data, comparing the average decoding times with an iteration time threshold, and executing the S200 on the flash memory when the average decoding times exceed the iteration time threshold.
The method for adjusting the data throughput rate of flash memory includes, but is not limited to, rewriting the flash memory and changing the comparison voltage during flash memory reading.
The invention also comprises a device for adjusting the throughput rate of flash memory read data, for implementing the method of any one of claims 1-4, characterized in that: the flash memory device is used for storing and erasing data; the flash memory controller comprises an LDPC control unit, an LDPC encoding unit, an LDPC decoding unit and an interface; the LDPC decoding unit is used for performing iterative error correction when the flash memory device stores and erases data; the LDPC control unit is used for monitoring the LDPC decoding unit in real time, setting iteration thresholds of the LDPC decoding unit for different data types, collecting real-time iteration times, comparing the iteration times with the threshold iteration times of the LDPC, adjusting error distribution and quantity of the flash memory based on the different data types, and sending error correction instructions to the flash memory device; the interface comprises one or more data transmission channels and completes data interaction among the LDPC decoding unit, the LDPC control unit, the LDPC encoding unit and the flash memory device.
According to the device for adjusting the flash memory read data throughput rate, the monitoring unit and the control unit are arranged on a data storage page and/or a data storage block of the flash memory device.
The device for adjusting the flash memory read data throughput rate according to the above, wherein the LDPC decoding unit further comprises: and if the data is detected to be required to be rewritten, the data is encoded by the LDPC encoding unit and is retransmitted to the flash memory device.
The beneficial effects of the invention are as follows: the stability of the flash memory reading efficiency is ensured; and the LDPC iteration times are prevented from increasing to influence the system throughput rate.
Drawings
The invention is further described below with reference to the drawings and examples;
FIG. 1 is a schematic view of a device according to an embodiment of the present invention;
FIG. 2 is a general flow diagram according to an embodiment of the present invention;
fig. 3a and 3b show decoding throughput and error distribution caused by different iteration numbers.
Detailed Description
Reference will now be made in detail to the present embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein the accompanying drawings are used to supplement the description of the written description so that one can intuitively and intuitively understand each technical feature and overall technical scheme of the present invention, but not to limit the scope of the present invention.
In the description of the present invention, the description of the first and second is only for the purpose of distinguishing technical features, and should not be construed as indicating or implying relative importance or implying the number of technical features indicated or the precedence of the technical features indicated.
In the description of the present invention, unless explicitly defined otherwise, terms such as arrangement and the like should be construed broadly, and those skilled in the art can reasonably determine the specific meaning of the terms in the present invention in combination with the specific contents of the technical scheme.
Fig. 1 is a schematic view showing the structure of an apparatus according to an embodiment of the present invention. The flash memory controller comprises an LDPC control unit, an LDPC encoding unit, an LDPC decoding unit and an interface; the LDPC decoding unit is used for performing iterative error correction when the flash memory device stores and erases data; the LDPC control unit is used for monitoring the LDPC decoding unit in real time, setting iteration thresholds of the LDPC decoding unit for different data types, collecting real-time iteration times, comparing the iteration times with the threshold iteration times of the LDPC, adjusting error distribution and quantity of the flash memory based on the different data types, and sending error correction instructions to the flash memory device; the interface comprises one or more data transmission channels and completes data interaction among the LDPC decoding unit, the LDPC control unit, the LDPC encoding unit and the flash memory device. And if the data is detected to be required to be rewritten, the data is encoded by the LDPC encoding unit and is retransmitted to the flash memory device.
Fig. 2 shows an overall flow diagram according to an embodiment of the invention. S100, performing real-time monitoring on the LDPC decoding unit, setting iteration thresholds of the LDPC decoding unit for different data types, and collecting real-time iteration times; s200, comparing the iteration times obtained in the S100 with the threshold iteration times of LDPC, and adjusting error distribution and quantity of the flash memory based on different data types.
For the flow, the technical scheme of the invention provides the following specific embodiments:
(1) Recording iteration number iter of each LDPC decoding;
(2) Setting an iteration number threshold iter_thrd;
(3) For critical data, the decoding delay is required to be short, and if item > item_thrd, measures can be initiated
(4) For other data, an average iteration number item_avg may be counted, if item_avg > item_thrd, initiating measures;
(5) The measure is defined as rewriting the flash memory, the number of errors can be reduced to a very low level after the flash memory is rewritten, even if errors exist, the error distribution is changed with high probability, and as a result, the decoding iteration times can be reduced, and the throughput rate is improved;
(6) Measures can also be defined as changing the comparison voltage during flash reading, which changes the error distribution and number.
Description: depending on the design of the flash FTL, the statistical average iteration number and overwrite may be defined on pages or blocks. The measures are not limited to the descriptions of (5) and (6), and any measures that may change the distribution and the number of errors may be used.
Fig. 3a and 3b show decoding throughput and error distribution caused by different iteration numbers.
In fig. 3a, the relationship between the decoding throughput rate and the iteration number is:
| number of iterations | Decoding throughput (MByte/2) |
| 5 | 1000 |
| 15 | 333.333333 |
| 20 | 250 |
| 25 | 200 |
| 30 | 166.666667 |
In fig. 3b, the relationship between the error distribution and the iteration number is:
| error distribution | Number of iterations |
| Error distribution 1 | 3 |
| Error distribution 2 | 5 |
| Error distribution 3 | 10 |
| Error distribution 4 | 30 |
| Error distribution 5 | 35 |
| Error distribution 6 | 40 |
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of one of ordinary skill in the art without departing from the spirit of the present invention.
Claims (5)
1. A method for adjusting flash read data throughput rate, comprising:
s100, setting iteration thresholds of the LDPC decoding unit for different data types, collecting real-time iteration times, and monitoring the LDPC decoding unit in real time;
s200, comparing the iteration times obtained in the S100 with the threshold iteration times of LDPC, and adjusting error distribution and quantity of the flash memory based on different data types;
the step S100 specifically includes:
s110, setting the iteration times threshold of the LDPC decoding unit, wherein the setting of the iteration threshold of the key data and the common data is included;
s120, if the decoded data is key data, executing the step S200 on the flash memory when the iteration number threshold is exceeded;
if the decoded data is normal data, taking average decoding times of a plurality of normal data, comparing the average decoding times with an iteration time threshold, and executing the step S200 on the flash memory when the average decoding times exceed the iteration time threshold;
the method for adjusting the error distribution and the number of the flash memory includes, but is not limited to, rewriting the flash memory and changing the comparison voltage when the flash memory is read.
2. The method of claim 1, wherein the data types include critical data and normal data.
3. An apparatus for adjusting flash read data throughput rate for implementing the method of any of claims 1-2, characterized by:
the flash memory device is used for storing and erasing data;
the flash memory controller comprises an LDPC control unit, an LDPC encoding unit, an LDPC decoding unit and an interface;
the LDPC decoding unit is used for performing iterative error correction when the flash memory device stores and erases data;
the LDPC control unit is used for monitoring the LDPC decoding unit in real time, setting iteration thresholds of the LDPC decoding unit for different data types, collecting real-time iteration times, comparing the iteration times with the threshold iteration times of the LDPC, adjusting error distribution and quantity of the flash memory based on the different data types, and sending error correction instructions to the flash memory device;
the interface comprises one or more data transmission channels and completes data interaction among the LDPC decoding unit, the LDPC control unit, the LDPC encoding unit and the flash memory device.
4. A device for adjusting the throughput rate of flash memory read data according to claim 3, wherein the control unit is arranged on a data storage page and/or a data storage block of the flash memory device.
5. The apparatus for adjusting flash read data throughput rate of claim 3, wherein the LDPC decoding unit further comprises:
and if the data is detected to be required to be rewritten, the data is encoded by the LDPC encoding unit and is retransmitted to the flash memory device.
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