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CN109660263A - A kind of LDPC code interpretation method suitable for MLC NAN flash memory - Google Patents

A kind of LDPC code interpretation method suitable for MLC NAN flash memory Download PDF

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CN109660263A
CN109660263A CN201811401607.5A CN201811401607A CN109660263A CN 109660263 A CN109660263 A CN 109660263A CN 201811401607 A CN201811401607 A CN 201811401607A CN 109660263 A CN109660263 A CN 109660263A
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decoding
data
threshold voltage
ldpc code
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CN109660263B (en
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童薇
刘景宁
冯丹
赵雨桐
覃鸿巍
赵威
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Huazhong University of Science and Technology
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
    • H03M13/1125—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms using different domains for check node and bit node processing, wherein the different domains include probabilities, likelihood ratios, likelihood differences, log-likelihood ratios or log-likelihood difference pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check

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  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Read Only Memory (AREA)

Abstract

The invention discloses a kind of LDPC code interpretation methods suitable for MLC nand flash memory, comprising: (1) type for determining page belonging to data to decode is then transferred to step (2) if low page；Otherwise, step (3) are transferred to；(2) LDPC code decoding is carried out to data to decode, and saves decoding result；Decoding terminates；(3) the low page data after decoding in same unit is obtained, the threshold voltage ranges of storage unit are determined according to low page data obtained and data to decode；Log-likelihood ratio is calculated according to identified threshold voltage ranges；It is decoding input with log-likelihood ratio calculated, LDPC code decoding is carried out to data to decode；Decoding terminates.The present invention can be improved decoding success rate, reduce decoding iteration number, to achieve the purpose that reduce decoding latency, improve flash memory reading performance.

Description

A kind of LDPC code interpretation method suitable for MLC NAN flash memory
Technical field
The invention belongs to computers to store error correcting technique field, be suitable for NAND MLC flash more particularly, to one kind LDPC code interpretation method.
Background technique
Nand flash memory is a kind of non-volatile memory medium, based on its storage density is high, unit cost is low, read or write speed is fast The advantages that, nand flash memory has become the application mainstream of field of storage.But as the diminution of flash technology size and storage are close The increase of degree, the bit error rate of nand flash memory also constantly increase, and compared to traditional BCH code, LDPC code still has under strong noise There is powerful error correcting capability, thus LDPC code is applied in nand flash memory more and more widely.However, LDPC code is in reading and writing data During additional read-write can be brought to postpone, to reduce the performance of nand flash memory.
In MLC nand flash memory, a storage unit stores two bits, this two belong to different data pages, are respectively High page and low page, according to the size of storage unit threshold voltage, storage unit is divided into four states, and this four state quilts Be encoded to corresponding data " 11 ", " 10 ", " 00 " and " 01 " left side is low page data, and the right is high page data.Peripheral electricity Road needs to be determined the data of storage unit storage by means of a series of reading reference voltages, by storage threshold voltage and reads reference voltage Compare the data that size is assured that in storage unit.After storage unit in flash memory is by the interference of noise, threshold voltage It can change, the threshold voltage distribution of two adjacent states can overlap, so that mistake occur in the data read out.
MLC nand flash memory be interfered after New Threshold Voltage Model as shown in Figure 1, solid line represent voltage value VERF1, VREF2 and VREF3 is the reading reference voltage of default, and the voltage value that dotted line represents is changeable reading reference voltage.It is existing LDPC code interpretation method is as shown in Fig. 2, read the range of the available threshold voltage of reference voltage, reading number using three of default According to rear usable LDPC Hard decision decoding.If the threshold voltage distribution of adjacent states overlaps, the data of meeting readout error. If LDPC Hard decision decoding fails, reading reference voltage should be changed, obtain more accurate threshold voltage ranges, sentenced using soft Certainly decoding obtains correct data.Reading reference voltage can be further changed after Soft decision decoding failure, the soft of next round is carried out and sentences It certainly decodes, until all available reading reference voltages are all used, reading reference voltage can not be changed again.
During the decoding of LDPC code, need first to determine corresponding threshold voltage ranges according to the data of reading, then Log-likelihood ratio (Log-Likelihood Ratio, LLR) is calculated as decoding according to identified threshold voltage ranges to input, Identified threshold voltage ranges are smaller, and the decoding input of acquisition is more accurate, then the decoding efficiency of LDPC code is higher.But it obtains Smaller threshold voltage ranges need to be varied multiple times reading reference voltage, increase so as to cause the read latency during LDPC code decoding Add.
Summary of the invention
In view of the drawbacks of the prior art and Improvement requirement, the present invention provides a kind of LDPC suitable for MLC nand flash memory Code coding method, it is intended that the decoding latency of LDPC code in MLC nand flash memory is reduced, to improve the performance of flash memory.
To achieve the above object, the present invention provides a kind of LDPC code interpretation method suitable for MLC nand flash memory, packets Include following steps:
(1) type for determining page belonging to data to decode is then transferred to step (2) if low page；Otherwise, it is transferred to step (3)；
(2) LDPC code decoding is carried out to data to decode, and saves decoding result；Decoding terminates；
(3) the low page data after decoding in same unit is obtained, and LDPC is carried out to data to decode according to low page data Code decoding；Decoding terminates.
Belong to the two bits of same storage unit, although belonging to different pages, by what is occurred after noise jamming Mistake has certain relevance, and due to the characteristic of coding, the raw Bit-Error-Rate of low page is lower than the raw Bit-Error-Rate of high page, So the decoding success rate of low page be higher than high page decoding success rate, and during decoding low page decoding prior to high page Decoding.In the present invention, when decoding to high page data, high page data is assisted using the low page decoding information of same unit Decoding, can according to the relevance between high page data and low page data reduce threshold voltage ranges, obtain more accurate translate Code input, to improve decoding success rate, reduce decoding iteration number, reaching reduces decoding latency, improves flash memory reading performance Purpose.
Further, step (3) includes:
The threshold voltage ranges of storage unit are determined according to low page data and data to decode；
Log-likelihood ratio is calculated according to threshold voltage ranges；
It is decoding input with log-likelihood ratio, LDPC code decoding is carried out to data to decode.
Further, if low page data is " 1 " and does not overturn before and after decoding, and data to decode is " 1 ", then Threshold voltage ranges be (- ∞, VREF1], and log-likelihood ratio are as follows:
If low page data is " 1 " and does not overturn before and after decoding, and data to decode is " 0 ", then threshold voltage model Enclose for (VREF1, VREF2], and log-likelihood ratio are as follows:
If low page data is " 0 " and does not overturn before and after decoding, and data to decode is " 1 ", then threshold voltage model Enclose for (VREF3, ∞], and log-likelihood ratio are as follows:
If low page data is " 0 " and does not overturn before and after decoding, and data to decode is " 0 ", then threshold voltage model Enclose for (VREF2, VREF3], and log-likelihood ratio are as follows:
If low page data is flipped before and after decoding, log-likelihood ratio are as follows:
LLR (MSB)=LLRMAX；
Wherein, corresponding when ER, P1, P2 and P3 are respectively storage unit stores data " 11 ", " 10 ", " 00 " and " 01 " to deposit Storage unit state, VREF1, VREF2 and VREF3 are that default reads reference voltage, and VREF1 < VREF2 < VREF3, p(S)(x) The probability that state of memory cells is S before data to decode generation mistake when expression threshold voltage is x, S ∈ { ER, P1, P2, P3 }, LLRMAX indicates to be greater than 50 constant.
For the high page data in storage unit, if reading data is 1, can be with threshold value voltage range (- ∞, VREF1] ∪ (VREF3 ,+∞], if reading data is 0, can be with threshold value voltage range (VREF1, VREF3], according only to The threshold voltage ranges that high page data determines are larger；According to the value of page data low in same unit, threshold value may further determine that Voltage range be (- ∞, VREF1], (VREF1, VREF2], (VREF2, VREF3] and (VREF3 ,+∞) among some range, Thus threshold voltage ranges, available more accurate decoding input are reduced.
For a code word, if decoding front and back is flipped on a certain position, show this place The threshold voltage state of storage unit is deviated, and causes to read error in data.Since threshold voltage state deviates more offsets To adjacent states, and the Gray code for being encoded to only difference one of threshold voltage adjacent states, so if threshold voltage state is inclined Moving to adjacent states causes a certain position of storage unit to be flipped, then is constant with the another one data of unit.Due to low page Error in data occurs in the overlapping region P1 and P2, so showing low if storage unit low page data decoding front and back is flipped Page data read error, threshold voltage are in P1 or P2 state.And the high page data of P1 and P2 state is all 0, so same list It is that 0, LLR can be set to a very big value LLRMAX that the high page data of member, which has very maximum probability,.
In general, contemplated above technical scheme through the invention, compared with prior art, due to high number of pages When according to being decoded, the threshold voltage ranges of storage unit can be determined in conjunction with the low page data after decoding in same unit, thus Identified threshold voltage ranges can be effectively reduced, more accurate decoding input is provided, it is successfully decoded so as to improve Rate reduces decoding iteration number, achievees the purpose that reduce decoding latency, improves flash memory reading performance.
Detailed description of the invention
Fig. 1 is the storage unit threshold voltage distribution schematic diagram of existing MLC nand flash memory；
Fig. 2 is existing LDPC code interpretation method schematic diagram；
Fig. 3 is the LDPC code interpretation method flow chart provided in an embodiment of the present invention for being used in MLC nand flash memory；
Fig. 4 is that decoding provided in an embodiment of the present invention inputs zoning schematic diagram；
Fig. 5 is the test result that decoding test is carried out using traditional decoding and interpretation method provided by the invention.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and It is not used in the restriction present invention.As long as in addition, technical characteristic involved in the various embodiments of the present invention described below Not constituting a conflict with each other can be combined with each other.
Before technical solution of the present invention is discussed in detail, first to the calculating of the log-likelihood ratio LLR as decoding input Make a brief description.Log-likelihood ratio is the probability that corresponding data is 0 and corresponding data is that the ratio between 1 probability takes logarithm again, Assuming that the threshold voltage ranges of storage unit are in (VREF1, V1,2] in, then the log-likelihood ratio LLR (LSB) and height of low page data The calculation formula of the log-likelihood ratio LLR (MSB) of page data is respectively as follows:
Threshold voltage ranges of the calculating of LLR based on storage unit, the threshold voltage ranges of reading are smaller, the decoding of acquisition Input information LLR is more accurate, then LDPC code decoding efficiency is higher.But smaller threshold voltage ranges are obtained, need repeatedly to change Become and read reference voltage, increases so as to cause the read latency during LDPC code decoding.
The present invention provides a kind of LDPC code interpretation method suitable for MLC nand flash memory, Integral Thought is, benefit With the raw Bit-Error-Rate of relevance and low page data between page data high in same storage unit and low page data lower than height This characteristic of the raw Bit-Error-Rate of page data, when being decoded to high page data, in conjunction with low page data in same storage unit It determines the threshold voltage ranges of storage unit, to reduce threshold voltage ranges, more accurate decoding input is provided, to improve Decoding success rate reduces decoding iteration number, achievees the purpose that reduce decoding latency, improves flash memory reading performance.
LDPC code interpretation method provided by the present invention suitable for MLC nand flash memory, as shown in figure 3, including following step It is rapid:
(1) type for determining page belonging to data to decode is then transferred to step (2) if low page；Otherwise, it is transferred to step (3)；
(2) LDPC code decoding is carried out to data to decode, and saves decoding result；Decoding terminates；
(3) the low page data after decoding in same unit is obtained, and LDPC is carried out to data to decode according to low page data Code decoding；Decoding terminates；
In an optional embodiment, step (3) is specifically included:
The threshold voltage ranges of storage unit are determined according to low page data and data to decode；
Log-likelihood ratio is calculated according to threshold voltage ranges；
It is decoding input with log-likelihood ratio, LDPC code decoding is carried out to data to decode；
According to the specific value of high page data (i.e. data to decode) and low page data, threshold value voltage range is simultaneously calculated The method of log-likelihood ratio are as follows:
If low page data is " 1 " and does not overturn before and after decoding, and data to decode is " 1 ", then threshold voltage model Enclose for (- ∞, VREF1], and log-likelihood ratio are as follows:
If low page data is " 1 " and does not overturn before and after decoding, and data to decode is " 0 ", then threshold voltage model Enclose for (VREF1, VREF2], and log-likelihood ratio are as follows:
If low page data is " 0 " and does not overturn before and after decoding, and data to decode is " 1 ", then threshold voltage model Enclose for (VREF3, ∞], and log-likelihood ratio are as follows:
If low page data is " 0 " and does not overturn before and after decoding, and data to decode is " 0 ", then threshold voltage model Enclose for (VREF2, VREF3], and log-likelihood ratio are as follows:
If low page data is flipped before and after decoding, log-likelihood ratio are as follows:
LLR (MSB)=LLRMAX；
Wherein, corresponding when ER, P1, P2 and P3 are respectively storage unit stores data " 11 ", " 10 ", " 00 " and " 01 " to deposit Storage unit state, VREF1, VREF2 and VREF3 are that default reads reference voltage, and VREF1 < VREF2 < VREF3, p(S)(x) The probability that state of memory cells is S before data to decode generation mistake when expression threshold voltage is x, S ∈ { ER, P1, P2, P3 }, LLRMAX indicates to be greater than 50 constant.
As shown in figure 4, for the high page data in storage unit, it, can be with threshold value voltage range if reading data is 1 For (- ∞, VREF1] ∪ (VREF3 ,+∞], if reading data is 0, can be with threshold value voltage range (VREF1, VREF3], The threshold voltage ranges determined according only to high page data are larger；It, can further really according to the value of page data low in same unit Determine threshold voltage ranges be (- ∞, VREF1], (VREF1, VREF2], (VREF2, VREF3] and (VREF3 ,+∞) among certain Thus a range reduces threshold voltage ranges, available more accurate decoding input；
For a code word, if decoding front and back is flipped on a certain position, show this place The threshold voltage state of storage unit is deviated, and causes to read error in data；Since threshold voltage state deviates more offsets To adjacent states, and the Gray code for being encoded to only difference one of threshold voltage adjacent states, so if threshold voltage state is inclined Moving to adjacent states causes a certain position of storage unit to be flipped, then is constant with the another one data of unit；Due to low page Error in data occurs in the overlapping region P1 and P2, so showing low if storage unit low page data decoding front and back is flipped Page data read error, threshold voltage are in P1 or P2 state；And the high page data of P1 and P2 state is all 0, so same list It is that 0, LLR can be set to a very big value LLRMAX, in the embodiment above, LLRMAX that the high page data of member, which has very maximum probability, Value range be greater than 50.
In the present invention, when decoding to high page data, high number of pages is assisted using the low page decoding information of same unit According to decoding, can according to the relevance between high page data and low page data reduce threshold voltage ranges, obtain more accurate Decoding input, to improve decoding success rate, reduce decoding iteration number, reaching reduces decoding latency, improves flash memory reading performance Purpose.
Based on " Exploiting Memory Device Wear-Out Dynamics to Improve NAND Flash Flash memory error model and parameter in Memory System Performance ", are respectively adopted traditional LDPC code interpretation method (i.e. the not decoding of auxiliary information) and the LDPC code interpretation method provided by the invention suitable for MLC nand flash memory (have auxiliary The decoding of supplementary information) decoding test is carried out, the code length that LDPC code is arranged is 9216, message length 8192, code rate 88.9%, Maximum decoding iteration number is 50.Testing sample erase-write cycles (PE) is 2000-5000 times, and programming interference number is 0-3 times, is protected Staying the time is 1 month to 10 years, and the flash memory bit error rate is 10-3To 10-2Rank.Specific test specimens are for example shown in table 1, using two kinds Interpretation method carries out the decoding success rate of decoding test and the height of the interpretation method using auxiliary information to test sample shown in table 1 The page bit error rate is as shown in Figure 5.
Table 1 tests sample
Number PE CCI interferes number Retention time High page data error rate
1 2000 1 6 years 8.55E-03
2 5000 1 January 8.74E-03
3 2000 1 7 years 9.26E-03
4 2000 1 8 years 9.74E-03
5 3000 2 2 years 9.75E-03
6 3000 3 3 years 9.97E-03
7 2000 0 3 years 1.02E-02
8 3000 1 1 year 1.04E-02
9 2000 1 9 years 1.05E-02
10 2000 1 10 years 1.09E-02
11 4000 3 1 year 1.16E-02
12 2000 0 4 years 1.20E-02
13 3000 2 3 years 1.20E-02
14 3000 3 5 years 1.21E-02
15 3000 3 6 years 1.28E-02
16 2000 0 5 years 1.34E-02
17 3000 3 7 years 1.36E-02
18 4000 2 1 year 1.40E-02
19 5000 0 January 1.41E-02
Test result is provided by the present invention suitable it is found that compared to traditional LDPC code interpretation method according to figure 5 The decoding success rate that 49% is at most improved for the LDPC code interpretation method of MLC nand flash memory reduces 40% decoding and changes Decoding latency can be effectively reduced in generation number.
As it will be easily appreciated by one skilled in the art that the foregoing is merely illustrative of the preferred embodiments of the present invention, not to The limitation present invention, any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should all include Within protection scope of the present invention.

Claims (3)

1.一种适用于MLC NAND闪存的LDPC码译码方法，其特征在于，包括如下步骤：1. an LDPC code decoding method applicable to MLC NAND flash memory, is characterized in that, comprises the steps: (1)确定待译码数据所属页的类型，若为低页，则转入步骤(2)；否则，转入步骤(3)；(1) determine the type of the page to which the data to be decoded belongs, if it is a low page, then go to step (2); otherwise, go to step (3); (2)对所述待译码数据进行LDPC码译码，并保存译码结果；译码结束；(2) carry out LDPC code decoding to the described data to be decoded, and save the decoding result; Decoding ends; (3)获得同一单元中译码后的低页数据，并根据所述低页数据对所述待译码数据进行LDPC码译码；译码结束。(3) Obtain the decoded lower page data in the same unit, and perform LDPC code decoding on the to-be-decoded data according to the lower page data; the decoding ends. 2.如权利要求1所述的适用于MLC NAND闪存的LDPC码译码方法，其特征在于，其特征在于，所述步骤(3)包括：2. The LDPC code decoding method applicable to MLC NAND flash memory as claimed in claim 1, wherein the step (3) comprises: 根据所述低页数据和所述待译码数据确定存储单元的阈值电压范围；determining the threshold voltage range of the memory cell according to the low page data and the to-be-decoded data; 根据所述阈值电压范围计算对数似然比；calculating a log-likelihood ratio based on the threshold voltage range; 以所述对数似然比为译码输入，对所述待译码数据进行LDPC码译码。Using the log-likelihood ratio as a decoding input, perform LDPC code decoding on the data to be decoded. 3.如权利要求2所述的适用于MLC NAND闪存的LDPC码译码方法，其特征在于，3. the LDPC code decoding method applicable to MLC NAND flash memory as claimed in claim 2 is characterized in that, 若所述低页数据为“1”且在译码前后没有翻转，并且所述待译码数据为“1”，则所述阈值电压范围为(-∞,VREF1]，且所述对数似然比为：If the low page data is "1" and is not inverted before and after decoding, and the data to be decoded is "1", the threshold voltage range is (-∞, VREF1], and the logarithm is similar to The ratio is: 若所述低页数据为“1”且在译码前后没有翻转，并且所述待译码数据为“0”，则所述阈值电压范围为(VREF1,VREF2]，且所述对数似然比为：If the low page data is "1" and is not flipped before and after decoding, and the data to be decoded is "0", the threshold voltage range is (VREF1, VREF2], and the log-likelihood The ratio is: 若所述低页数据为“0”且在译码前后没有翻转，并且所述待译码数据为“1”，则所述阈值电压范围为(VREF3,∞]，且所述对数似然比为：If the lower page data is "0" and is not flipped before and after decoding, and the data to be decoded is "1", the threshold voltage range is (VREF3,∞], and the log-likelihood The ratio is: 若所述低页数据为“0”且在译码前后没有翻转，并且所述待译码数据为“0”，则所述阈值电压范围为(VREF2,VREF3]，且所述对数似然比为：If the lower page data is "0" and is not flipped before and after decoding, and the data to be decoded is "0", the threshold voltage range is (VREF2, VREF3], and the log-likelihood The ratio is: 若所述低页数据在译码前后发生翻转，则所述对数似然比为：LLR(MSB)＝LLRMAX；If the low page data is flipped before and after decoding, the log-likelihood ratio is: LLR(MSB)=LLRMAX; 其中，ER、P1、P2和P3分别为存储单元存储数据“11”、“10”、“00”和“01”时对应的存储单元状态，VREF1、VREF2和VREF3均为默认读参考电压，且VREF1＜VREF2＜VREF3，p(S)(x)表示阈值电压为x时所述待译码数据发生错误前存储单元状态为S的概率，S∈{ER,P1,P2,P3}，LLRMAX表示大于50的常数。Among them, ER, P1, P2 and P3 are the corresponding memory cell states when the memory cells store data "11", "10", "00" and "01" respectively, VREF1, VREF2 and VREF3 are the default read reference voltages, and VREF1<VREF2<VREF3, p (S) (x) represents the probability that the state of the memory cell is S before the error occurs in the data to be decoded when the threshold voltage is x, S∈{ER,P1,P2,P3}, LLRMAX represents A constant greater than 50.
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CN110752850A (en) * 2019-08-27 2020-02-04 广东工业大学 Method for quickly iterating LDPC code of MLC flash memory chip
CN111611101A (en) * 2020-04-22 2020-09-01 珠海妙存科技有限公司 Method and device for adjusting throughput rate of flash memory read data
WO2023134132A1 (en) * 2022-01-13 2023-07-20 苏州浪潮智能科技有限公司 Method and device for improving data read success rate, and medium

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