CN111564497B - SiC MOSFET device with non-uniform body diode - Google Patents

Abstract

The invention discloses a SiC MOSFET device with a non-uniform body diode. The upper surface of an n-type 4H-SiC substrate is sequentially provided with a buffer layer, a drift region and a current spreading layer, and a p-well region is embedded in the middle of the current spreading layer. An n ⁺ source region is embedded in each p well region, and a p ⁺ contact region is embedded in each n ⁺ source region; the upper end surfaces of adjacent p well regions are jointly covered with a gate oxide layer, which simultaneously covers On the upper surface of the current spreading layer between part of the n ⁺ source region and the n ⁺ source region, the upper surface of the gate oxide layer is provided with a polysilicon gate, and the outer surface of the gate oxide layer and the polysilicon gate are jointly wrapped with an isolation dielectric layer; in the p ⁺ contact area The source electrode is covered on the n ⁺ source region and the isolation dielectric layer; the drain is provided on the lower surface of the n-type 4H-SiC substrate; the gate covers the upper surface of the isolation dielectric layer and is connected to the polysilicon gate. The structure of the invention significantly improves the reliability of the SiC MOSFET device.

Description

A SiC MOSFET device with non-uniform body diode

technical field

The invention belongs to the technical field of power electronic devices, and relates to a SiC MOSFET device with a non-uniform body diode.

Background technique

Because SiC material has the characteristics of large band gap, high thermal conductivity, high critical avalanche breakdown electric field strength, high saturated carrier drift velocity, and good thermal stability, SiC MOSFET has low conduction loss, fast switching speed, high Operating frequency and many other excellent characteristics. Compared with Si IGBT, SiC MOSFET has higher efficiency and power density, which is very suitable for application in the field of power conversion. However, due to the high interface state density and poor reliability of the SiC gate oxide layer, SiC MOSFETs are generally difficult to withstand high junction temperatures, which not only limits the operating temperature range of SiC MOSFETs, but also affects the reliability of SiC MOSFETs. adverse effects.

In 2019, Yusuke Kobayashi et al. studied the high temperature characteristics of SiC SJ-MOSFET in their article "High-temperature Performance of 1.2kV-class SiC Super Junction MOSFET", and clarified the mechanism of soft recovery of SiC MOSFET body diode. Research on reducing power consumption and reducing self-heating of SiC MOSFETs provides theoretical support. In 2020, Kijeong Han et al. in their article "1.2-kV 4H-SiC SenseFET With Monolithically Integrated Sensing Resistor" realized the accurate online monitoring of SiC MOSFET junction temperature through the technical solution of integrating SenseFET into 1.2kV SiC MOSFET. The healthy operation of the chip provides an important monitoring technology guarantee. Although the above technical solutions have achieved good results in reducing the self-heating of SiC MOSFETs and monitoring the junction temperature of SiC MOSFETs in real time, under the working state of SiC MOSFET chips, due to the difference in heat dissipation efficiency in different regions of the chip, there will be temperature gradients between different regions of the chip. The central region often exhibits a higher junction temperature, so that the SiC MOSFET chip still has the risk of high temperature failure when the junction temperature in some regions does not reach the limit, which has an adverse effect on the reliability of the SiC MOSFET chip.

Contents of the invention

The purpose of the present invention is to provide a SiC MOSFET device with a non-uniform body diode, which solves the problem that the SiC MOSFET chip in the prior art still has the risk of high temperature failure when the junction temperature in some areas does not reach the limit, and there is a reliability problem. Insufficient problem.

The technical solution adopted in the present invention is that a SiC MOSFET device with a non-uniform body diode includes an n-type 4H-SiC substrate, a buffer layer is arranged on the upper surface of the n-type 4H-SiC substrate, and the upper surface of the buffer layer is arranged There is a drift region, and the upper surface of the drift region is provided with a current spreading layer, and a p well region is embedded in the current spreading layer, and an n ⁺ source region is embedded in each p well region, and a p well region is embedded in each n ⁺ source region. ⁺ contact region, the lower end surface of the p ⁺ contact region is in contact with the p well region; the upper end surface of the adjacent p well region is jointly covered with a gate oxide layer, and the gate oxide layer covers part of the n ⁺ source region and between the n ⁺ source region The upper surface of the inter-current spreading layer, the upper surface of the gate oxide layer is provided with a polysilicon gate, and the outer surface of the gate oxide layer and the polysilicon gate is jointly wrapped with an isolation dielectric layer; on the p ⁺ contact region, n ⁺ source region and the isolation dielectric layer, a common The source electrode is covered; the drain electrode is arranged on the lower surface of the n-type 4H-SiC substrate; and the gate electrode is also included. The gate electrode covers the upper surface of the isolation dielectric layer and is connected with the polysilicon gate.

The SiC MOSFET device with non-uniform body diode of the present invention is also characterized in that:

The n-type 4H-SiC substrate has a thickness of 100 μm-500 μm and a diameter of 3 inches-8 inches.

The buffer layer is made of n-type 4H-SiC material with a thickness of 0.1 μm-1.0 μm and an impurity concentration of 1×10 ¹⁸ cm ⁻³ to 1×10 ¹⁹ cm ⁻³ .

The drift region is made of n-type 4H-SiC material with a thickness of 5.0 μm-65 μm and an impurity concentration of 1x10 ¹⁴ cm ^-3 -2x10 ¹⁶ cm ^-3 . The increasing concentration gradient is not less than 1x10 ¹⁴ cm ^-4 .

The current spreading layer is made of n-type 4H-SiC material with a thickness of 0.5 μm-5.0 μm, and the impurity concentration is not lower than that of the drift region, and the impurity concentration is 1×10 ¹⁴ cm ⁻³ to 2×10 ¹⁶ cm ⁻³ .

The shape of the p-well region adopts one or more combinations of strip, circle, ring, regular quadrangle, regular hexagon and regular octagon as required, and the thickness of the p-well region is 0.5 μm-3.0 μm , the distance between adjacent p-well regions is 0.5 μm-5.0 μm.

The thickness of the n ⁺ source region is 0.1 μm-0.5 μm, and the impurity concentration of the n ⁺ source region is 1×10 ¹⁸ cm ⁻³ to 1×10 ¹⁹ cm ⁻³ .

The thickness of the p ⁺ contact region is 0.2 μm-0.8 μm, the impurity concentration of the p ⁺ contact region is 2×10 ¹⁸ cm ⁻³ -2×10 ¹⁹ cm ⁻³ , the width of the p ⁺ contact region is W _p+ , from the edge of the chip to In the center of the chip, W _p+ shows an increasing non-uniform distribution law, and the total increase range is not less than 0.5 μm, and the W _p+ of the edge cells of the chip is smaller than the W _p+ of the central cells of the chip.

The gate oxide layer is made of one or more combinations of SiO ₂ , Al ₂ O ₃ , and HfO ₂ , and the thickness of the gate oxide layer is 10nm-100nm.

The beneficial effect of the present invention is that the heat distribution of the existing SiC MOSFET chip is optimized, the power consumption of the existing SiC MOSFET chip is reduced, the problem of uneven internal temperature distribution of the existing SiC MOSFET chip is improved, and the existing SiC MOSFET chip is significantly improved. Reliability of MOSFET chips.

Description of drawings

Fig. 1 is the structural representation of the SiC MOSFET device with non-uniform body diode of the present invention;

2 is a schematic structural diagram of a SiC MOSFET device having a square cell with a non-uniform body diode according to Embodiment 1 of the present invention;

Fig. 3 is the SiC MOSFET device that the cell of embodiment 2 of the present invention has non-uniform body diode is bar shape;

FIG. 4 is an enlarged schematic diagram of a partial structure in FIG. 1 .

In the figure, 1. n-type 4H-SiC substrate, 2. buffer layer, 3. drift region, 4. current spreading layer, 5. p well region, 6. n ⁺ source region, 7. p ⁺ contact region, 8 . Gate oxide layer, 9. Polysilicon gate, 10. Isolation dielectric layer, 11. Source, 12. Drain, 13. Gate.

Detailed ways

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

1 and 4, the SiC MOSFET structure of the present invention includes an n-type 4H-SiC substrate 1, a buffer layer 2 is provided on the upper surface of the n-type 4H-SiC substrate 1, and a drift layer 2 is provided on the upper surface of the buffer layer 2. region 3, the upper surface of the drift region 3 is provided with a current spreading layer 4, and a p well region 5 is embedded in the current spreading layer 4, and an n ⁺ source region 6 is embedded in each p well region 5, and each n ⁺ source region 6 is inlaid with a p ⁺ contact region 7, the lower end surface of the p ⁺ contact region 7 is in contact with the p well region 5, and the upper end surface of the adjacent p well region 5 is jointly covered with a gate oxide layer 8, which simultaneously covers On the upper surface of the current spreading layer 4 between part of the n ⁺ source region 6 and the n ⁺ source region 6, a polysilicon gate 9 is provided on the upper surface of the gate oxide layer 8, and the outer surfaces of the gate oxide layer 8 and the polysilicon gate 9 are jointly wrapped with an isolation medium Layer 10, covering the p ⁺ contact region 7, n ⁺ source region 6 and isolation dielectric layer 10 together with a source 11; the lower surface of the n-type 4H-SiC substrate 1 is provided with a drain 12; it also includes a gate 13 , the gate 13 covers the upper surface of the isolation dielectric layer 10 and is connected to the polysilicon gate 9 .

The n-type 4H-SiC substrate 1 has a thickness of 100 μm-500 μm and a diameter of 3 inches-8 inches;

The buffer layer 2 is made of n-type 4H-SiC material with a thickness of 0.1 μm-1.0 μm and an impurity concentration of 1×10 ¹⁸ cm ⁻³ to 1×10 ¹⁹ cm ⁻³ .

The drift region 3 is made of n-type 4H-SiC material with a thickness of 5.0 μm-65 μm and an impurity concentration of 1x10 ¹⁴ cm ^-3 -2x10 ¹⁶ cm ^-3 . The gradient is not smaller than 1x10 ¹⁴ cm ^-4 .

The current spreading layer 4 is made of n-type 4H-SiC material with a thickness of 0.5 μm-5.0 μm, and the impurity concentration is not lower than that of the drift region 3, and the impurity concentration is 1×10 ¹⁴ cm ⁻³ to 2×10 ¹⁶ cm ⁻³ .

The p well region 5 is located on the upper surface of the current spreading layer 4 and is embedded in the current spreading layer 4. The shape of the p well region 5 adopts one of strip, circle, ring, regular quadrilateral, regular hexagon and regular octagon as required. A combination of one or more, the thickness of the p-well region 5 is 0.5 μm-3.0 μm, and the distance between adjacent p-well regions 5 is 0.5 μm-5.0 μm.

The thickness of the n ⁺ source region 6 is 0.1 μm-0.5 μm, and the impurity concentration of the n ⁺ source region 6 is 1×10 ¹⁸ cm ⁻³ -1×10 ¹⁹ cm ⁻³ ;

The thickness of the p ⁺ contact region 7 is 0.2 μm-0.8 μm, the impurity concentration of the p ⁺ contact region 7 is 2x10 ¹⁸ cm ^-3 -2x10 ¹⁹ cm ^-3 , the width of the p ⁺ contact region 7 is W _p+ , from the edge of the chip to In the center of the chip, W _p+ presents an increasing non-uniform distribution, with a total increase of not less than 0.5 μm, and the W _p+ of the cells at the edge of the chip is smaller than the W _p+ of the cells at the center of the chip;

The gate oxide layer 8 is a combination of one or more of SiO ₂ , Al ₂ O ₃ , and HfO ₂ , and the thickness of the gate oxide layer 8 is 10nm-100nm;

The gate 13 covers the isolation dielectric layer 10 and is connected to the polysilicon gate 9 through a contact hole in the isolation dielectric layer 10 .

Materials for the buffer layer 2 , drift region 3 , p well region 5 , n ⁺ source region 6 and p ⁺ contact region 7 may also be Ga ₂ O ₃ , diamond, GaN and other semiconductor materials.

The source 11 and the drain 12 are made of one or a combination of Ti, Ni, W, Al, Ag, Au materials, and the gate 13 is made of one or a combination of metals Al or Au.

The SiC MOSFET device of the present invention contains a non-uniform body diode, that is, the lateral width of the body diode is non-uniform, the impurity concentration of the withstand voltage layer of the body diode is non-uniform, and the impurity concentration in the drift region of the SiC MOSFET cell is uniform. Since the lateral width of the body diode of the chip is distributed from the edge of the chip to the center of the chip, when the SiC MOSFET is in the forward conduction state, the body diode is in the cut-off state, and the channel ratio in the central area of the chip is lower than that in the edge area of the chip. Therefore, the resistance per unit area of the central area of the chip is higher than the resistance per unit area of the edge area of the chip, and since the voltage drop U _on is consistent across the chip, it can be known from P _on = U _on ² /R that the self-heating of the central area of the chip Smaller than the self-heating of the edge area of the chip, the phenomenon of prominent junction temperature in the center of the chip is suppressed, the heat distribution of the existing SiC MOSFET chip is optimized, the problem of uneven internal temperature distribution in the working state of the existing SiC MOSFET chip is improved, and the existing SiC MOSFET chip is improved. Reliability of MOSFET chips. On the other hand, due to the non-uniform impurity concentration of the withstand voltage layer of the body diode, the impurity concentration in the withstand voltage region of the body diode also shows an increasing regular distribution from top to bottom, and the body diode of the present invention has a stronger Withstand voltage capability; when the chip is in the switching action state, the induced electric field from bottom to top generated by the increasing law of impurity concentration from top to bottom can accelerate the carrier extraction speed of the body diode in the reverse recovery state and shorten the body diode. The recovery time of the diode reduces the switching loss of the chip and reduces self-heating. At the same time, because the impurity concentration in the drift region of the SiC MOSFET device increases from top to bottom, when the chip is in the off state, the drift region is completely exhausted, and the concentration of ionized donors increases from top to bottom, so the electric field strength is from top to bottom. The rate of decrease from top to bottom is slow first and then fast. Compared with the existing SiC MOSFET with uniform distribution of impurities in the drift region, the SiC MOSFET device of the present invention has a stronger withstand voltage capability; when the chip is in the forward conduction state, the drift The region is not completely depleted. In the non-depleted region, due to the increasing law of the donor impurity concentration from top to bottom, an induced electric field will be formed from bottom to top, and electrons will accelerate drift under the action of the induced electric field, making the chip The on-state resistance is reduced, which reduces the power consumption of the chip and reduces self-heating.

Example 1

Referring to Figures 1 and 2, the cells with non-uniform body diodes use square SiC MOSFET devices, including n-type 4H-SiC substrate 1, with a thickness of 300 μm and an upper surface area of 6 inches;

The buffer layer 2 on the n-type 4H-SiC substrate 1 has a thickness of 0.5 μm, an n-type conductivity type, and an impurity concentration of 1×10 ¹⁸ cm ⁻³ ;

The thickness of the drift region 3 is ^9.0 μm, ^and the impurity concentration ^is continuously increasing in a gradient from the upper surface to the lower surface ^. The incremental gradient from the upper surface to the lower surface is 5x10 ¹⁴ cm ^-3 per micron;

The current spreading layer 4 is n-type 4H-SiC with a thickness of 1.0 μm and an impurity concentration of 1×10 ¹⁶ cm ⁻³ ;

The p-well region 5 is located on the upper surface of the current spreading layer 4 and is embedded in the current spreading layer 4. The top view shape of the p-well region is a regular quadrilateral, the thickness of the p-well region is 0.8 μm, and the distance between adjacent p-well regions is 2.0 μm.

The thickness of the n ⁺ source region 6 is 0.3 μm, the impurity concentration of the n ⁺ source region 6 is 1×10 ¹⁸ cm ^-3 , the thickness of the p ⁺ contact region 7 is 0.7 μm, the impurity concentration of the p ⁺ contact region 7 is 1×10 ¹⁸ cm ^-3 , the p ⁺ The width of the contact region 7 is W _p+ , the width W p+ of the p ⁺ contact region 7 located at the edge of the chip is 1.0 μm, and the width W _p+ of the p ⁺ contact region ₇ located at the center of the chip is 11.0 μm, from the edge of the chip to the center of the chip W p+ The distribution of _p+ is increasing, and the increasing gradient is 10 μm per mm;

The gate oxide layer 8 is made of SiO ₂ , and the thickness of the gate oxide layer is 50nm;

The polysilicon gate 9 covering the upper surface of the gate oxide layer 8, the gate oxide layer 8 and the polysilicon gate 9 covering the upper surface of the edge of the n ⁺ source region 6 and the upper surface of the p well region 5 between the n ⁺ source regions 6 and the current On the upper surface of the extension layer 4, the thickness of the polysilicon gate is 0.8 μm;

An isolation dielectric layer 10 wrapping the gate oxide layer 8 and the polysilicon gate 9, the material of the isolation dielectric layer 10 is SiO ₂ , and the thickness is 1.5 μm;

The source electrode 11 covering the p ⁺ contact region 7, part of the n ⁺ source region 6 and the upper surface of the isolation dielectric layer 10, the source electrode 11 is a combination of three metals: Ti, Ni, and Al, and the total thickness of the source electrode 11 is 6 μm;

The material of the drain electrode 12 is a combination of three metals: Ti, Ni, and Ag, and the total thickness of the drain electrode 12 is 2 μm;

The material of the gate 13 is metal Al with a thickness of 6 μm;

The buffer layer 2, the drift region 3, the p well region 5, the n ⁺ source region 6, and the p ⁺ contact region 7 are all made of 4H-SiC.

Example 2

Referring to Fig. 1 and Fig. 3, the cell with non-uniform body diode of the present invention adopts a strip-shaped SiC MOSFET device, the thickness of the n-type 4H-SiC substrate 1 is 150 μm, and the upper surface area is 4 inches;

The thickness of the buffer layer 2 is 1.0 μm, the conductivity type is n-type, and the impurity concentration is 1×10 ¹⁸ cm ⁻³ ;

Drift region 3 is n-type 4H-SiC with a thickness of 30.0 μm, and the impurity concentration is distributed in a gradient continuous increase from the upper surface to the lower surface. The impurity concentration on the lower surface is 1x10 ¹⁵ cm ^-3 , and the upper surface is 7x10 ¹⁴ cm ^-3 , the increasing gradient of impurity concentration from the upper surface to the lower surface is 1x10 ¹³ cm ^-3 per micron;

The current spreading layer 4 is n-type 4H-SiC with a thickness of 1.0 μm and an impurity concentration of 5×10 ¹⁵ cm ⁻³ ;

The p well region 5 is located on the upper surface of the current spreading layer 4 and is embedded in the current spreading layer 4. The top view shape of the p well region 5 is a strip shape, the thickness of the p well region 5 is 1.0 μm, and the distance between adjacent p well regions 5 is 3.0 μm. μm.

The thickness of the n ⁺ source region 6 is 0.3 μm, the impurity concentration of the n ⁺ source region 6 is 1×10 ¹⁸ cm ^-3 , the thickness of the p ⁺ contact region 7 is 0.7 μm, the impurity concentration of the p ⁺ contact region 7 is 1×10 ¹⁸ cm ^-3 , the p ⁺ The width of the contact region 7 is W _p+ , the width W p+ of the p ⁺ contact region 7 located at the edge of the chip is 1.0 μm, and the width W _p+ of the p ⁺ contact region ₇ located at the center of the chip is 6.0 μm, from the edge of the chip to the center of the chip W p+ The distribution of _p+ is increasing, and the increasing gradient is 5 μm per millimeter;

The material of the gate oxide layer 8 is SiO ₂ , and the thickness of the gate oxide layer 8 is 50nm;

The polysilicon gate 9 covering the upper surface of the gate oxide layer 8, the gate oxide layer 8 and the polysilicon gate 9 covering the upper surface of the edge of the n ⁺ source region 6 and the upper surface of the p well region 5 between the n ⁺ source regions 6 and the current On the upper surface of the extension layer 4, the thickness of the polysilicon gate 9 is 1.0 μm;

An isolation dielectric layer 10 wrapping the gate oxide layer 8 and the polysilicon gate 9, the material of the isolation dielectric layer 10 is SiO ₂ , and the thickness of the isolation dielectric layer 10 is 2.0 μm;

The source electrode 11 covering the p ⁺ contact region 7, part of the n ⁺ source region 6 and the upper surface of the isolation dielectric layer 10, the material of the source electrode 11 is a combination of three metals: Ti, Ni, and Al, and the total thickness of the source electrode 11 is 6 μm ;

The material of the drain electrode 12 is a combination of three metals: Ti, Ni, and Ag, and the total thickness of the drain electrode 12 is 2 μm;

The material of the gate 13 is metal Al with a thickness of 6 μm;

The aforementioned buffer layer 2, drift region 3, p well region 5, n ⁺ source region 6, and p ⁺ contact region 7 are all made of 4H-SiC.

Claims (9)

1. A SiC MOSFET device having a non-uniform body diode, characterized by: the device comprises an n-type 4H-SiC substrate (1), wherein a buffer layer (2) is arranged on the upper surface of the n-type 4H-SiC substrate (1), a drift region (3) is arranged on the upper surface of the buffer layer (2), a current expansion layer (4) is arranged on the upper surface of the drift region (3), p well regions (5) are inlaid in the current expansion layer (4) at intervals, and an n well region (5) is inlaid in each p well region (5) ⁺ A source region (6) of each n ⁺ A p is embedded in the source region (6) ⁺ Contact area (7), p ⁺ The lower end face of the contact region (7) is in contact with the p-well region (5), p ⁺ The width of the contact area (7) is W _p+ From the edge of the chip to the center of the chip, W _p+ The W of the cell at the edge of the chip is in an increasing non-uniform distribution rule, the total increasing amplitude is not less than 0.5 mu m _p+ Smaller than W of the central cell of the chip _p+ (ii) a The upper end faces of the adjacent p well regions (5) are jointly covered with a gate oxide layer (8), and the gate oxide layer (8) covers part of the n well regions at the same time ⁺ A source region (6) and n ⁺ The upper surface of the current extension layer (4) between the source regions (6) and the upper surface of the gate oxide layer (8) are provided with a polysilicon gate (9) which is oxidizedThe outer surfaces of the layer (8) and the polysilicon gate (9) are jointly wrapped with an isolation dielectric layer (10); at p ⁺ Contact zone (7), n ⁺ A source electrode (11) is covered on the active region (6) and the isolation dielectric layer (10) together; a drain electrode (12) is arranged on the lower surface of the n-type 4H-SiC substrate (1); the grid (13) is covered on the upper surface of the isolation dielectric layer (10) and is connected with the polysilicon gate (9).

2. The SiC MOSFET device of claim 1, wherein: the thickness of the n-type 4H-SiC substrate (1) is 100-500 mu m, and the diameter is 3-8 inches.

3. The SiC MOSFET device of claim 1, wherein: the buffer layer (2) is made of n-type 4H-SiC material, the thickness is 0.1-1.0 μm, and the impurity concentration is 1x10 ¹⁸ cm ^-3 -1x10 ¹⁹ cm ^-3 。

4. The SiC MOSFET device of claim 1, wherein: the drift region (3) is made of n-type 4H-SiC material, the thickness is 5.0-65 mu m, and the impurity concentration is 1x10 ¹⁴ cm ^-3 -2x10 ¹⁶ cm ^-3 The impurity concentration is distributed in a gradient increasing rule from the upper surface to the lower surface, and the gradient of the impurity concentration is not less than 1x10 ¹⁴ cm ^-4 。

5. The SiC MOSFET device of claim 1, wherein: the current spreading layer (4) is made of n-type 4H-SiC material, the thickness of the current spreading layer is 0.5-5.0 mu m, the impurity concentration is not lower than that of the drift region (3), and the impurity concentration is 1x10 ¹⁴ cm ^-3 -2x10 ¹⁶ cm ^-3 。

6. The SiC MOSFET device of claim 1, wherein: the shape of the p-well region (5) adopts one or a combination of more of a strip shape, a circular shape, a ring shape, a regular quadrangle, a regular hexagon and a regular octagon according to the requirement, the thickness of the p-well region (5) is 0.5-3.0 μm, and the spacing distance between the adjacent p-well regions (5) is 0.5-5.0 μm.

7. The SiC MOSFET device of claim 1, wherein: n is ⁺ The thickness of the source region (6) is 0.1-0.5 μm, n ⁺ The impurity concentration of the source region (6) is 1x10 ¹⁸ cm ^-3 -1x10 ¹⁹ cm ^-3 。

8. The SiC MOSFET device of claim 1, wherein: said p is ⁺ The thickness of the contact region (7) is 0.2-0.8 μm, p ⁺ The impurity concentration of the contact region (7) is 2x10 ¹⁸ cm ^-3 -2x10 ¹⁹ cm ^-3 。

9. The SiC MOSFET device of claim 1, wherein: the gate oxide layer (8) adopts SiO ₂ 、Al ₂ O ₃ 、HfO ₂ Of the gate oxide layer (8) is 10nm to 100nm thick.

Images