CN111508964A - 3D memory device and method of manufacturing the same - Google Patents

Abstract

The application discloses a 3D memory device and a method of manufacturing the same. The manufacturing method comprises the following steps: forming a stop layer and a sacrificial layer on a substrate having a plurality of grooves, each groove being filled with the sacrificial layer, the substrate being separated from the sacrificial layer by the stop layer; forming a laminated structure on the sacrificial layer; forming a channel column penetrating through the laminated structure, wherein the channel column extends towards the direction of the substrate, the side wall of the channel column is in contact with the sacrificial layer, and the channel column comprises a channel layer; forming a plurality of grid line gaps, wherein each grid line gap extends into the sacrificial layer towards the substrate direction; sequentially removing the sacrificial layer and the stop layer through the plurality of gate line gaps so as to form a first gap between the laminated structure and the substrate, wherein part of the side wall of the channel column is exposed by the first gap; removing a portion of the sidewall of the channel pillar through the first gap to expose a portion of the channel layer; and forming an epitaxial layer in the first gap, wherein the channel layer is electrically connected with the substrate through the epitaxial layer, and each grid line gap corresponds to the corresponding groove.

Description

3D memory device and method of manufacturing the same

technical field

The present invention relates to memory technology, and more particularly, to 3D memory devices and methods of manufacturing the same.

Background technique

The development direction of semiconductor technology is the reduction of feature size and the improvement of integration. For memory devices, the improvement of the storage density of the memory device is closely related to the progress of the semiconductor manufacturing process. As the feature sizes of semiconductor manufacturing processes are getting smaller and smaller, the storage density of memory devices is getting higher and higher.

In order to further increase the storage density, three-dimensionally structured storage devices (ie, 3D storage devices) have been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, and the integration degree can be doubled on a wafer per unit area, and the cost can be reduced.

In 3D memory devices, gate stack structures and channel pillars are generally used to provide selection transistors and memory transistors, and conductive channels are used to form interconnections between peripheral circuits and memory strings. The channel pillars are formed in the channel holes, and an epitaxial structure is formed at the bottom of each channel hole for electrically connecting the channel layer of the channel pillars and the semiconductor substrate. However, in order to make the channel layer contact the epitaxial layer, it is necessary to remove a part of the silicon-oxygen-nitrogen-oxygen (S-O-N-O) structure formed on the epitaxial structure through an etching process, thereby exposing the epitaxial structure. The etching process may cause damage to the S-O-N-O structure. As the storage capacity of the 3D memory device becomes larger and larger, the number of layers of the gate stack structure will gradually increase, which further increases the difficulty of etching.

Therefore, it is desirable to further improve the manufacturing process of the 3D memory device, thereby increasing the yield of the 3D memory device.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide an improved 3D memory device and its manufacturing method, which can form the electrical connection between the channel layer and the substrate without forming an epitaxial structure in the channel hole and without etching the S-O-N-O structure at the bottom of the channel hole. the epitaxial layer.

According to an aspect of the present invention, there is provided a method of fabricating a 3D memory device, comprising: forming a stop layer and a sacrificial layer on a substrate, the substrate having a plurality of grooves and each of the grooves being covered by the Filling the sacrificial layer, the substrate and the sacrificial layer are separated by the stop layer; forming a stacked structure on the sacrificial layer, including alternately stacked interlayer sacrificial layers and interlayer dielectric layers; In the channel pillar of the stacked structure, the channel pillar extends toward the substrate, the sidewall of the channel pillar is in contact with the sacrificial layer, and the channel pillar includes a channel layer; forming a plurality of gate line gaps, each of which extends into the sacrificial layer in the direction of the substrate; the sacrificial layer and the stop layer are sequentially removed through the plurality of gate line gaps, so that the A first gap is formed between the stacked structure and the substrate, and a part of the sidewall of the channel pillar is exposed by the first gap; and a part of the sidewall of the channel pillar is removed through the first gap, so as to Part of the channel layer is exposed; and an epitaxial layer is formed in the first gap, the channel layer is electrically connected to the substrate via the epitaxial layer, wherein each of the gate line gaps is respectively Corresponding to the position of the corresponding groove.

Preferably, the substrate surface includes a storage area, a step area and a peripheral area, each of the grooves extends through the storage area and the step area to the peripheral area, and the manufacturing method further comprises: removing Part of the stacked structure forms a plurality of steps above the step area, and exposes the sacrificial layer above the peripheral area; removes the sacrificial layer and the stop layer above the peripheral area, the sacrificial layer and the stop layer in the groove are retained; and a first insulating layer is formed over the step region and the peripheral region, the first insulating layer covering the plurality of steps and the A substrate, wherein the gate line gaps respectively pass through the stacked structure and the first insulating layer toward the substrate.

Preferably, the lateral dimension of the groove is not smaller than the lateral dimension of the gate line gap.

Preferably, in the step of forming the epitaxial layer, the epitaxial layer grows from the surface of the substrate toward the stacked structure, stops growing when it is spaced from the stacked structure by a preset distance, and retains part of the epitaxial layer. the first gap, and the manufacturing method further includes: forming a second insulating layer on the surface of the epitaxial layer.

Preferably, a part of the first gap is reserved between the second insulating layer and the stacked structure, and a layer of the stacked structure close to the substrate is an interlayer insulating layer, and the manufacturing method further includes: A gate conductor layer is formed in the first gap through the gate line gap.

Preferably, the method further includes: forming a channel epitaxial portion on the surface of the channel pillar exposed in the first gap, the channel epitaxial portion being in contact with the channel layer and the epitaxial layer respectively, wherein the first Two insulating layers extend to the surface of the channel epitaxial portion.

Preferably, a gate conductor layer is formed in the first gap surrounded by at least the second insulating layer and the interlayer insulating layer.

Preferably, the second insulating layer is in contact with the stacked structure, and the layer of the stacked structure close to the substrate is an interlayer sacrificial layer. The interlayer sacrificial layer is replaced with the gate conductor layer.

Preferably, the method further includes: forming a conductive channel in the gate line gap, the conductive channel being in contact with the epitaxial layer; and forming a third insulating layer in the gate line gap, the third insulating layer connecting the The conductive via is spaced apart from the stack structure.

Preferably, the method further includes: forming a doped region in the substrate and in contact with the epitaxial layer, wherein the bottom end of the channel pillar is located in the doped region, and the doped region is in contact with the doped region. The epitaxial layers collectively serve as the well region.

According to another aspect of the present invention, there is provided a 3D memory device, comprising: a substrate having a plurality of grooves; an epitaxial layer on the substrate, and each of the grooves is filled by the epitaxial layer a stacked structure, located on the epitaxial layer, including alternately stacked gate conductor layers and interlayer dielectric layers; a channel pillar, passing through the stacked structure, the channel pillar extending toward the substrate , the channel pillar includes a channel layer, and part of the channel layer is exposed through sidewalls of the channel pillar, so that the channel layer is electrically connected to the substrate through the epitaxial layer; and A plurality of conductive channels, each of which extends toward the substrate to the epitaxial layer, wherein each of the conductive channels corresponds to the position of the corresponding groove.

Preferably, the substrate surface includes a storage area, a stepped area and a peripheral area, each of the grooves extends through the storage area and the stepped area to the peripheral area, and the stack above the stepped area The structure is a plurality of steps, and the 3D memory device further includes: a first insulating layer covering the steps and the peripheral region of the substrate, wherein the conductive channels respectively pass through the stack toward the substrate direction layer structure and the first insulating layer.

Preferably, a channel epitaxial portion is further included, located between the substrate and the stacked structure, and in contact with the channel layer and the epitaxial layer, respectively.

Preferably, a doped region is further included in the substrate, and the doped region is in contact with the epitaxial layer.

Preferably, a third insulating layer is further included, and the third insulating layer is located between the conductive channel and the laminated structure.

According to the 3D memory device and the manufacturing method thereof according to the embodiments of the present invention, a sacrificial layer is formed between the substrate and the stacked structure, a space for forming the first gap is reserved, the sacrificial layer is removed through the gate line gap, and then the first gap is removed. Part of the sidewalls of the channel pillars are removed to expose the channel layer, and then an epitaxial layer is formed on the substrate, and the epitaxial layer enables the substrate and the channel layer to be electrically connected. Since a groove is formed in the substrate, and part of the sacrificial layer is filled in the groove, the etching process window of the gate line gap is increased, which ensures that the area of the gate line gap exposed to the sacrificial layer is guaranteed, and the gate line gap is not The stop layer between the substrate and the sacrificial layer will be destroyed.

Further, since the grooves correspond to the storage area, the step area and the peripheral area respectively, and the inner surfaces of the grooves are covered by the stop layer, when ensuring that the gate line gap corresponding to the storage area can expose enough sacrificial layers, prevent the The gate line gap corresponding to the peripheral region passes through the stop layer to damage the structure in the substrate.

Therefore, the 3D memory device and the manufacturing method thereof according to the embodiments of the present invention improve product yield and reliability.

Description of drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings.

1a and 1b respectively show a circuit diagram and a schematic structural diagram of a memory cell string of a 3D memory device.

Figure 2a shows a perspective view of a 3D memory device.

Figure 2b shows a top view of the 3D memory device.

2c to 2e respectively illustrate schematic cross-sectional views of a 3D memory device when a gate line gap is formed.

3a to 3l-2 show structural diagrams of various stages of a method for fabricating a 3D memory device according to an embodiment of the present invention.

Detailed ways

The present invention will be described in more detail below with reference to the accompanying drawings. In the various figures, like elements are designated by like reference numerals. For the sake of clarity, various parts in the figures have not been drawn to scale. Additionally, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be depicted in one figure.

It will be understood that, in describing the structure of a device, when a layer or region is referred to as being "on" or "over" another layer or region, it can be directly on the other layer or region, or Other layers or regions are also included between it and another layer, another region. And, if the device is turned over, the layer, one region, will be "under" or "under" another layer, another region.

In order to describe the situation directly above another layer, another area, the expression "directly on" or "on and adjacent to" will be used herein.

In this application, the term "semiconductor structure" refers collectively to the entire semiconductor structure formed during the various steps of fabricating a memory device, including all layers or regions that have already been formed. Numerous specific details of the present invention are described below, such as device structures, materials, dimensions, processing techniques and techniques, in order to provide a clearer understanding of the present invention. However, as can be understood by one skilled in the art, the present invention may be practiced without these specific details.

The invention may be embodied in various forms, some examples of which will be described below.

1a and 1b respectively show a circuit diagram and a schematic structural diagram of a memory cell string of a 3D memory device. The case where the memory cell string includes 4 memory cells is shown in this embodiment. It can be understood that the present invention is not limited to this, and the number of memory cells in the memory cell string can be any number, for example, 32 or 64.

As shown in FIG. 1a, the first end of the memory cell string 100 is connected to a bit line (Bit-Line, BL), and the second end is connected to a source line (Source Line, SL). The memory cell string 100 includes a plurality of transistors connected in series between a first terminal and a second terminal, including: a first selection transistor (drain side selection transistor) Q1, memory transistors M1 to M4, and a second selection transistor (source side selection transistor) side selection transistor) Q2. The gate of the first selection transistor Q1 is connected to a drain selection gate (Selection Gate for Drain, SGD), also known as a top gate selection line. The gate of the second selection transistor Q2 is connected to a source selection gate (Selection Gate for Source, SGS), also known as a bottom gate selection line. The gates of the memory transistors M1 to M4 are connected to corresponding word lines of the word lines WL1 to WL4, respectively.

As shown in FIG. 1b, the select transistors Q1 and Q2 of the memory cell string 100 include a top gate conductor layer 122 and a bottom gate to body layer 123, respectively, and the memory transistors M1 to M4 include a gate conductor layer 121, respectively. The gate conductor layers 121 , 122 and 123 are in the same stacking sequence as the transistors in the memory cell string 100 , and adjacent gate conductor layers are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel pillar 110 . The channel pillar 110 is adjacent to or penetrates through the gate stack structure. In the middle portion of the channel pillar 110 , the tunnel dielectric layer 112 , the charge storage layer 113 and the gate dielectric layer 114 are sandwiched between the gate conductor layer 121 and the channel layer 111 , thereby forming the memory transistors M1 to M4 . At both ends of the channel pillar 110, the gate dielectric layer 114 is sandwiched between the gate conductor layers 122 and 123 and the channel layer 111, thereby forming the selection transistors Q1 and Q2.

In this embodiment, the channel layer 111 is composed of polysilicon, for example, the tunnel dielectric layer 112 and the gate dielectric layer 114 are composed of oxide, such as silicon oxide, respectively, and the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals. For example, silicon nitride containing particles of metal or semiconductor, the gate conductor layers 121 , 122 and 123 are composed of metal such as tungsten. The channel layer 111 is used to provide channel regions of the control selection transistor and the control transistor, and the doping type of the channel layer 111 is the same as that of the selection transistor and the control transistor. For example, for N-type selection transistors and control transistors, the channel layer 111 may be N-type doped polysilicon.

In this embodiment, the core of the channel pillar 110 is the channel layer 111 , and the tunneling dielectric layer 112 , the charge storage layer 113 and the gate dielectric layer 114 form a stacked structure surrounding the sidewall of the core. In an alternative embodiment, the core of the channel pillar 110 is an additional insulating layer, and the channel layer 111 , the tunneling dielectric layer 112 , the charge storage layer 113 and the gate dielectric layer 114 form a stacked structure surrounding the semiconductor layers.

In this embodiment, the selection transistors Q1 and Q2 and the memory transistors M1 to M4 use a common channel layer 111 and a gate dielectric layer 114 . In the channel pillar 110, the channel layer 111 provides source and drain regions and channel layers of a plurality of transistors. In alternative embodiments, separate steps may be used to form the semiconductor layers and gate dielectric layers of the select transistors Q1 and Q2 and the semiconductor layers and gate dielectric layers of the memory transistors M1 to M4, respectively. In the channel pillar 110, the semiconductor layers of the selection transistors Q1 and Q2 and the semiconductor layers of the memory transistors M1 to M4 are electrically connected to each other.

In some other embodiments, the selection transistor Q1 can also be fabricated into a structure like the memory transistors M1 to M4 , specifically, a tunnel is sandwiched between the gate conductor layer 121 and the channel layer 111 on the upper part of the channel pillar 110 . The dielectric layer 112, the charge storage layer 113 and the gate dielectric layer 114 are formed to form the selection transistor Q1. Since the structure of the selection transistor Q1 is the same as that of the memory transistors M1 to M4, the formation process of the channel pillar can be simplified.

In a write operation, the memory cell string 100 utilizes FN tunneling to write data into selected ones of the memory transistors M1 to M4. Taking the memory transistor M2 as an example, while the source line SL is grounded, the source select gate line SGS is biased to a voltage of about zero volts, so that the select transistor Q2 corresponding to the source select gate line SGS is turned off and the drain select gate line is turned off. The line SGD is biased to the high voltage VDD, so that the selection transistor Q1 corresponding to the drain selection gate line SGD is turned on. Further, the bit line BL2 is grounded, the word line WL2 is biased to the programming voltage VPG, for example, about 20V, and the remaining word lines are biased to the low voltage VPS1. Since only the word line voltage of the selected storage transistor M2 is higher than the tunneling voltage, electrons in the channel region of the storage transistor M2 reach the charge storage layer 113 through the tunneling dielectric layer 112, thereby converting data into charges and storing them in in the charge storage layer 113 of the storage transistor M2.

In the read operation, the memory cell string 100 determines the charge amount in the charge storage layer according to the conduction state of the selected memory transistors among the memory transistors M1 to M4, thereby obtaining data represented by the charge amount. Taking the memory transistor M2 as an example, the word line WL2 is biased to the read voltage VRD, and the remaining word lines are biased to the high voltage VPS2. The conduction state of the storage transistor M2 is related to its threshold voltage, that is, the charge amount in the charge storage layer, so that the data value can be determined according to the conduction state of the storage transistor M2. The memory transistors M1 , M3 and M4 are always in an on state, and therefore, the on state of the memory cell string 100 depends on the on state of the memory transistor M2 . The control circuit determines the conduction state of the memory transistor M2 according to the electrical signals detected on the bit line BL and the source line SL, so as to obtain the data stored in the memory transistor M2.

Figure 2a shows a perspective view of a 3D memory device. Wherein, X, Y, and Z respectively represent the length direction, width direction and height direction of the 3D memory device. For the sake of clarity, each insulating layer in the 3D memory device is not shown in FIG. 2a.

The 3D memory device shown in this embodiment includes 4*4 16 memory cell strings 100 in total, and each memory cell string 100 includes 4 memory cells, thereby forming a 4*4*4 memory array of 64 memory cells in total . It can be understood that the present invention is not limited thereto, and the 3D memory device may include any number of memory cell strings, for example, 1024, and the number of memory cells in each memory cell string may be any number, for example, 32 or 64.

In the 3D memory device, the memory cell strings respectively include respective channel pillars 110 and common gate conductor layers 121 , 122 and 123 . The gate conductor layers 121 , 122 and 123 are in the same stacking sequence as the transistors in the memory cell string 100 , and adjacent gate conductor layers are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure 120 . The interlayer insulating layer is not shown in the figure.

The internal structure of the channel pillar 110 is shown in FIG. 2b , which will not be described in detail here. In the middle portion of the channel pillar 110 , the gate conductor layer 121 forms the memory transistors M1 to M4 together with the channel layer 111 , the tunneling dielectric layer 112 , the charge storage layer 113 and the gate dielectric layer 114 inside the channel pillar 110 . At both ends of the channel pillar 110, the gate conductor layers 122 and 123, together with the channel layer 111 and the gate dielectric layer 114 inside the channel pillar 110, form the selection transistors Q1 and Q2.

The channel pillars 110 penetrate through the gate stack structure 120 and are arranged in an array. The first ends of the plurality of channel pillars 110 in the same column are commonly connected to the same bit line (ie, one of the bit lines BL1 to BL4 ), and the second ends are commonly connected to the same bit line. Connected to the substrate 101 , the second terminal forms a common source connection via the substrate 100 .

The gate conductor 122 of the drain side select transistor Q1 is divided into different gate lines by a gate line slit 109 . The gate lines of the plurality of channel pillars 110 in the same row are commonly connected to the same drain selection gate line (ie, one of the drain selection gate lines SGD1 to SGD4 ).

The gate conductors 121 of the memory transistors M1 and M4 are connected in one body at different levels, respectively. If the gate conductors 121 of the memory transistors M1 and M4 are divided into different gate lines by the gate line gap 109, the gate lines of the same level reach the interconnection layer 132 via the respective conductive channels 131 to be interconnected with each other, and then pass through the conductive channels 133 is connected to the same word line (ie, one of the word lines WL1 to WL4).

The gate conductors of the source side selection transistor Q2 are connected integrally. If the bottom gate conductor layer 123 of the source side selection crystal Q2 is divided into different gate lines by the gate line slits 109, the gate lines reach the interconnection layer 132 via the respective conductive channels 131 to be interconnected with each other, and then via the conductive channels 133 is connected to the same source select line SGS.

Figure 2b shows a top view of the 3D memory device, wherein X and Y represent the length direction and width direction of the 3D memory device, respectively. The 3D memory device includes a memory area, a stepped area, and a peripheral area, which correspond to the substrate surface hereinafter. The storage area 10 , the step area 20 and the peripheral circuit area 30 , FIGS. 2 c to 2 e respectively show schematic cross-sectional views of the 3D memory device when a gate line gap is formed. Fig. 2c is taken along the line BB in Fig. 2b, and Fig. 2d and Fig. 2e are taken along the line AA in Fig. 2b.

As shown in FIGS. 2 c and 2 d , before the gate line gap 207 is formed, the semiconductor structure that has been formed includes a substrate 201 , a stop layer 203 , a sacrificial layer 204 , a first insulating layer 205 , a channel pillar 210 and a stacked layer structure 250 . The stop layer 203 and the sacrificial layer 204 are sequentially stacked on the surface of the substrate 201 along the height direction of the 3D memory device, wherein the stop layer 203 and the sacrificial layer 204 are only located in the storage region 10 and the step region 20 . The stacked structure 250 is located on the sacrificial layer 204 and forms a plurality of steps in the step region. The first insulating layer 205 covers the substrate 201 corresponding to the peripheral area 30 and the steps corresponding to the step area 20 .

Further, the stacked structure 250 and the first insulating layer 205 are etched respectively to form gate line gaps 207 extending along the X direction of the device. The gate line gaps 207 correspond to the storage region 10 , the step region 20 and the peripheral region 30 respectively. Further, the sacrificial layer 204 is removed through the gate line gap 207 to expose part of the sidewall of the channel pillar 210 . Further, part of the sidewalls of the channel pillars 210 are sequentially removed to expose the channel layer of the channel pillars, and the stop layer 203 is also removed to expose the substrate 201 . Further, an epitaxial layer is formed on the surface of the substrate 201 , and the epitaxial layer is in contact with the channel layer of the channel pillar 210 and the substrate 201 respectively, so as to achieve the purpose of electrically connecting the channel layer and the substrate 201 .

The electrical connection between the channel layer and the substrate 201 by the above method can avoid forming an epitaxial structure in the channel hole, and avoid using an etching process to remove the S-O-N-O structure on the epitaxial structure at the bottom of the channel hole.

However, the above process has strict requirements on the depth of the gate line gap 207 . As shown in FIG. 2 c , when the depth of the formed gate line gap 207 is too shallow (for example, h1 ), the area of the sacrificial layer 204 exposed by the gate line gap 207 is limited, which is often removed when the sacrificial layer 204 is removed through the gate line gap 207 Not clean or even removeable. When the depth of the formed gate line gap 207 is too deep (for example, h2), the stop layer 203 between the substrate 201 and the sacrificial layer 204 will be damaged, and in the step of removing the sacrificial layer 204, the substrate 201 will be damaged, Thus, structures in the substrate 201 (eg, doped regions, well regions, etc. formed in the substrate 201 ) are destroyed.

At the same time, when the gate line gap 207 is formed, the stacked structure 250 and the first insulating layer 205 need to be etched at the same time. Since the structure and material of the first insulating layer 205 are single, the first insulating layer 205 is etched The etch rate is greater than that of the stacked structure 250 . As shown in FIG. 2d, when the depth of the gate line gap 207 corresponding to the storage region 10 is guaranteed to be on the surface of the stop layer 203, since the etching rate of the first insulating layer 205 is high, and the peripheral region 30 does not have a corresponding stop layer, the corresponding The gate line gap 207 in the peripheral region 30 will directly reach the substrate 201, and in the subsequent step of removing the sacrificial layer 204, the structures in the substrate 201 (for example, the doped regions, well regions formed in the substrate 201) will be damaged. Wait). As shown in FIG. 2e, when the depth of the gate line gap 207 corresponding to the peripheral region 30 is guaranteed to be on the surface of the substrate 201, the depth of the gate line gap 207 corresponding to the storage region 10 is relatively shallow, so that the sacrificial layer 204 cannot be effectively removed. .

3a to 3l-2 show structural diagrams of various stages of a method for fabricating a 3D memory device according to an embodiment of the present invention.

As shown in Figure 3a, the method begins with a semiconductor substrate 101 having formed a plurality of doped regions 101a. A plurality of grooves 102 are formed on the substrate 101 through a zero mask. A stop layer 103 and a sacrificial layer 104 are formed on the substrate 101 , each groove 102 is filled with the sacrificial layer 104 , and the substrate 101 and the sacrificial layer 104 are separated by the stop layer 103 . A stacked structure 150 is formed on the sacrificial layer 104 , including interlayer sacrificial layers 152 and interlayer dielectric layers 151 that are alternately stacked. Wherein, Fig. 3a is taken along line BB or line CC in Fig. 2b.

In this embodiment, the substrate 101 is, for example, a single crystal silicon substrate, and the surface of the substrate 101 includes adjacent storage regions 10 , step regions 20 and peripheral regions 30 . Each groove 102 extends through the storage area 10 and the stepped area 20 to the peripheral area 30 . The stop layer 102 and the sacrificial layer 104 have a higher etching selectivity ratio, for example, the material of the stop layer 102 includes but not limited to silicon oxide, the material of the sacrificial layer 104 includes but not limited to polysilicon, and the structure of the sacrificial layer 104 can also be based on the present invention. Other settings are required by those skilled in the art. The interlayer sacrificial layer 152 and the interlayer dielectric layer 151 have a higher etching selectivity ratio, so that the interlayer sacrificial layer 152 can be replaced with a gate conductor layer in the subsequent process. For example, the material of the interlayer dielectric layer 151 includes but not Limited to silicon oxide, the material of the interlayer sacrificial layer 152 includes, but is not limited to, silicon nitride.

Further, a part of the stacked structure 150 is removed to form a plurality of steps above the step area 20, and the sacrificial layer 104 above the peripheral area 30 is exposed; the sacrificial layer 104 and the stop layer 103 above the peripheral area 30 are removed, and filled in The sacrificial layer 104 and the stop layer 103 in the groove 102 are retained; the first insulating layer 105 is formed over the step area 20 and the peripheral area 30, and the first insulating layer 105 covers the plurality of steps and the peripheral area 30 on the surface of the substrate 101, As shown in Figure 3b. Wherein, Fig. 3b is taken along the CC line in Fig. 2b. In this embodiment, the material of the first insulating layer 105 includes but is not limited to silicon oxide.

Further, channel pillars 110 are formed in the storage region 10 through the stacked structure 150 , the channel pillars 110 extend toward the substrate 101 , and the sidewalls of the channel pillars 110 are in contact with the sacrificial layer 104 , as shown in FIG. 3 c . Wherein, Fig. 3c is taken along the line BB in Fig. 2b.

In this embodiment, the bottom of the channel pillar 110 extends into the doped region 101a. In some other embodiments, the bottoms of the channel pillars 110 may also extend into the sacrificial layer 104 or the stop layer 103 . The channel pillar 110 includes a gate dielectric layer 114 , a charge storage layer 113 , a tunnel dielectric layer 112 and a channel layer 111 sequentially covering the inner surface of the channel hole 106 . In some other embodiments, the channel pillar 110 further includes an insulating core 115 surrounded by the channel layer 111 .

Further, a plurality of gate line gaps 107 are formed, and the gate line gaps 107 extend into the sacrificial layer 104 in the direction of the substrate 101. Each gate line gap 107 corresponds to the position of the corresponding groove 102, as shown in FIG. 3d-1 and Figure 3d-2. Wherein, Fig. 3d-1 is taken along line BB in Fig. 2b, and Fig. 3d-2 is taken along line CC in Fig. 2b.

In this step, anisotropic etching is performed on the stacked structure 150, the first insulating layer 105 and the sacrificial layer 104. The anisotropic etching can be dry etching, such as ion milling etching, plasma etching, reactive ion etching, and laser burning. eclipse. For example, by controlling the etching time, the etching is stopped in the sacrificial layer 104 or other predetermined positions.

In this embodiment, since the substrate 101 has the grooves 102 corresponding to the gate line gaps 107, the window of the gate line gap etching process is increased, that is, the area of the gate line gap 107 exposed to the sacrificial layer 104 is ensured, and the The gate line gap 107 does not damage the stop layer 103 between the substrate 101 and the sacrificial layer 104 . At the same time, since the grooves 102 correspond to the storage area 10 , the step area 20 and the peripheral area 30 respectively, and the inner surfaces of the grooves 102 corresponding to each area are covered by the stop layer 103 , it is guaranteed that the While gate line gaps 107 of region 10 may expose sufficient sacrificial layer 104 , gate line gaps 107 corresponding to peripheral region 30 are prevented from reaching into substrate 101 to damage structures in substrate 101 . The lateral dimension of the groove 102 is not smaller than the lateral dimension of the gate line gap 107 . In some preferred embodiments, the lateral dimension of the groove 102 is larger than the lateral dimension of the gate line gap 107, so as to further achieve the purpose of increasing the etching process window.

Further, the sacrificial layer 104 is removed through the plurality of gate line gaps 107 to form a first gap 1071, and part of the sidewall of the channel pillar 110 is exposed by the first gap 1071, as shown in FIG. 3e-1 and FIG. 3e-2. Wherein, Fig. 3e-1 is taken along line BB in Fig. 2b, and Fig. 3e-2 is taken along line CC in Fig. 2b.

In this step, for example, the sacrificial layer 104 is removed by a wet etching process. Since the area of the sacrificial layer 104 exposed by the gate line gap 107 is relatively large, the sacrificial layer 104 can be completely removed. The stop layer 103 protects the substrate 101 and prevents the substrate 101 from being damaged by the etchant.

Further, part of the sidewalls of the channel pillars are removed through the first gap 1071 to expose part of the channel layer 111, and the stop layer 103 is also removed through the first gap 1071, as shown in FIG. 3f-1 and FIG. 3f-2 . Wherein, Fig. 3f-1 is taken along line BB in Fig. 2b, and Fig. 3f-2 is taken along line CC in Fig. 2b.

In this step, the gate dielectric layer 114 , the charge storage layer 113 , and the tunnel dielectric layer 112 exposed in the first gap 1071 are sequentially removed by, for example, a wet etching process to expose the channel layer 111 , and the sacrificial layer 104 may be connected with the gate dielectric layer. Layer 114 and/or tunneling dielectric layer 112 are removed simultaneously.

Further, the epitaxial layer 140 and the channel outer edge portion 116 are formed in the first gap 1071, and the channel layer 111 is electrically connected to the substrate 101 through the epitaxial layer 140, as shown in FIG. 3g-1 and FIG. 3g-2. Wherein, Fig. 3g-1 is taken along line BB in Fig. 2b, and Fig. 3g-2 is taken along line CC in Fig. 2b.

In this embodiment, the channel outer edge portion 116 grows from the surface of the channel layer 111 along the radial direction of the channel column, and is in contact with the epitaxial layer 140. The epitaxial layer 140 grows from the surface of the substrate 101 in the direction of the stacked structure 150, The growth is stopped when spaced from the stacked structure 150 by a predetermined distance, and part of the first gap 1071 is retained. The material of the channel outer edge portion 116 includes but not limited to polysilicon, the material of the epitaxial layer 140 includes but not limited to silicon, and the groove 102 is filled with the epitaxial layer 140 . The epitaxial layer 140 and the doped region 101a together serve as a well region, and the structure of the epitaxial layer 140 can also be set in other ways according to the needs of those skilled in the art.

In some other embodiments, the growth of the epitaxial layer 140 stops when it contacts the insulating structure 150 , and the layer of the stacked structure 150 close to the substrate 101 is an interlayer insulating layer.

Further, a second insulating layer 108 is formed on the surface of the epitaxial layer 140, and the second insulating layer 108 extends to the surface of the outer edge portion 116 of the channel, as shown in FIG. 3h.

In this step, for example, a surface oxidation process is used to oxidize the surfaces of the epitaxial layer 140 and the channel epitaxial portion 116 exposed in the first gap 1071 to form the second insulating layer 108 , wherein the material of the second insulating layer 108 includes but is not limited to Silicon oxide. However, the embodiments of the present invention are not limited thereto, and those skilled in the art may select other processes to form the second insulating layer 108 as required.

In this embodiment, a part of the first gap 1071 remains between the second insulating layer 108 and the stacked structure 150 , and the layer of the stacked structure 150 close to the substrate 101 is an interlayer insulating layer.

In some other embodiments, the second insulating layer 108 is in contact with the stacked structure 150 , and the layer of the stacked structure 150 close to the substrate 101 is an interlayer sacrificial layer.

Further, the interlayer sacrificial layer is removed relative to the interlayer insulating layer 151 in the stacked structure 150 through the gate wire gap 107 to form a second gap 1072, as shown in FIG. 3i. Further, a conductive material 109 is filled in the gate line gap 107, the first gap 1071 and the second gap 1072, as shown in FIG. 3j, wherein the conductive material 109 includes but is not limited to metal tungsten, and in the gate line gap, the conductive material 109 is The material 109 is not filled, leaving the gap.

Further, an etch-back process is used to remove part of the conductive material through the remaining gap, and the gate line gap 107 is re-formed, as shown in FIG. 3k .

In this step, the interlayer sacrificial layer is replaced with the gate conductor layers 121 , 122 , and 123 to form the stacked structure 120 . In this embodiment, the space of the first gap 1071 is fully utilized to form the bottom gate conductor layer 123 , and the bottom gate conductor layer 123 is surrounded by at least the second insulating layer 1081 and the interlayer insulating layer 151 .

Further, a third insulating layer 1082 is formed on the sidewall of the gate line gap 107, a conductive channel 160 is formed in the gate line gap 107, the conductive channel 160 is in contact with the epitaxial layer 140, and the third insulating layer 1082 connects the conductive channel 160 with the stacked layer. The structures 150 are spaced as shown in FIGS. 31-1 and 31-2. Wherein, Fig. 3l-1 is taken along line BB in Fig. 2b, and Fig. 3l-2 is taken along line CC in Fig. 2b.

In this embodiment, the conductive via 160 is in contact with the epitaxial layer 140 through the second insulating layer 1081 . The conductive channel 160 includes an adhesive layer 161 and a conductive layer 162, the material of the adhesive layer 161 includes but not limited to titanium nitride, and the material of the conductive layer 162 includes but not limited to metal tungsten.

According to the 3D memory device and the manufacturing method thereof according to the embodiments of the present invention, a sacrificial layer is formed between the substrate and the stacked structure, a space for forming the first gap is reserved, the sacrificial layer is removed through the gate line gap, and then the first gap is removed. Part of the sidewalls of the channel pillars are removed to expose the channel layer, and then an epitaxial layer is formed on the substrate, and the epitaxial layer enables the substrate and the channel layer to be electrically connected. Since a groove is formed in the substrate, and part of the sacrificial layer is filled in the groove, the etching process window of the gate line gap is increased, which ensures that the area of the gate line gap exposed to the sacrificial layer is guaranteed, and the gate line gap is not The stop layer between the substrate and the sacrificial layer will be destroyed.

Further, since the grooves correspond to the storage area, the step area and the peripheral area respectively, and the inner surfaces of the grooves are covered by the stop layer, when ensuring that the gate line gap corresponding to the storage area can expose enough sacrificial layers, prevent the The gate line gap corresponding to the peripheral region passes through the stop layer to damage the structure in the substrate.

Therefore, the 3D memory device and the manufacturing method thereof according to the embodiments of the present invention improve product yield and reliability.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as those described above. Additionally, although the various embodiments have been described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

Embodiments of the present invention have been described above. However, these examples are for illustrative purposes only, and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present invention.

Claims (15)

1. A method of manufacturing a 3D memory device, comprising: forming a stop layer and a sacrificial layer on a substrate, the substrate having a plurality of grooves and each of the grooves being filled by the sacrificial layer, the substrate and the sacrificial layer being separated by the stop layer ; forming a stacked structure on the sacrificial layer, including alternately stacked interlayer sacrificial layers and interlayer dielectric layers; forming a channel pillar passing through the stacked structure, the channel pillar extending toward the substrate, the sidewall of the channel pillar being in contact with the sacrificial layer, and the channel pillar including the channel layer ; forming a plurality of gate line gaps, each of the gate line gaps extending into the sacrificial layer toward the substrate; The sacrificial layer and the stop layer are sequentially removed through the plurality of gate line gaps, so as to form a first gap between the stacked structure and the substrate, and part of the sidewalls of the channel pillars are the first gap is exposed; removing a portion of the sidewall of the channel pillar through the first gap to expose a portion of the channel layer; and An epitaxial layer is formed in the first gap, and the channel layer is electrically connected to the substrate through the epitaxial layer, Wherein, each of the gate line gaps corresponds to the position of the corresponding groove. 2 . The manufacturing method of claim 1 , wherein the substrate surface includes a storage area, a stepped area, and a peripheral area, and each of the grooves extends through the storage area and the stepped area to the the peripheral area, the manufacturing method further includes: removing part of the stacked structure to form a plurality of steps above the step area, and exposing the sacrificial layer above the peripheral area; removing the sacrificial layer and the stop layer over the peripheral region, the sacrificial layer and the stop layer in the recess being retained; and A first insulating layer is formed over the step region and the peripheral region, the first insulating layer covers the plurality of steps and the substrate, Wherein, the gate line gaps respectively pass through the stacked structure and the first insulating layer toward the substrate. 3. The manufacturing method of claim 2, wherein a lateral dimension of the groove is not smaller than a lateral dimension of the gate line gap. 4 . The manufacturing method according to claim 1 , wherein, in the step of forming the epitaxial layer, the epitaxial layer grows from the surface of the substrate in the direction of the stacked structure. 4 . Stop growing at a preset distance, keep part of the first gap, The manufacturing method further includes: forming a second insulating layer on the surface of the epitaxial layer. 5. The manufacturing method according to claim 4, wherein a part of the first gap is reserved between the second insulating layer and the stacked structure, and a layer of the stacked structure close to the substrate is a layer insulating layer, The manufacturing method further includes forming a gate conductor layer in the first gap through the gate line gap. 6 . The manufacturing method according to claim 5 , further comprising: forming a channel epitaxial part on the surface of the channel pillar exposed in the first gap, the channel epitaxial part being respectively connected with the channel layer and the channel epitaxial part. 7 . epitaxial layer contacts, Wherein, the second insulating layer extends to the surface of the channel epitaxial portion. 7. The manufacturing method according to claim 6, wherein a gate conductor layer is formed in the first gap surrounded by at least the second insulating layer and the interlayer insulating layer. 8. The manufacturing method according to claim 4, wherein the second insulating layer is in contact with the laminated structure, and a layer of the laminated structure close to the substrate is an interlayer sacrificial layer, The manufacturing method further includes: replacing the interlayer sacrificial layer with the gate conductor layer through the gate line gap. 9. The manufacturing method according to claim 2, further comprising: forming a conductive via in the gate gap, the conductive via being in contact with the epitaxial layer; and A third insulating layer is formed in the gate line gap, the third insulating layer separating the conductive via from the stack structure. 10. The method of claim 2, further comprising: forming a doped region in the substrate in contact with the epitaxial layer, Wherein, the bottom end of the channel pillar is located in the doped region, and the doped region and the epitaxial layer together serve as the well region. 11. A 3D memory device, comprising: a substrate having a plurality of grooves; an epitaxial layer on the substrate, and each of the grooves is filled with the epitaxial layer; a stacked structure, located on the epitaxial layer, comprising alternately stacked gate conductor layers and interlayer dielectric layers; a channel pillar passing through the stacked structure, the channel pillar extending toward the substrate, the channel pillar including a channel layer, and a part of the channel layer passing through the sidewall of the channel pillar is exposed so that the channel layer is electrically connected to the substrate via the epitaxial layer; and a plurality of conductive channels, each of the conductive channels extending toward the substrate to the epitaxial layer, Wherein, each of the conductive channels corresponds to the position of the corresponding groove. 12. The 3D memory device of claim 11, wherein the substrate surface includes a storage region, a stepped region, and a peripheral region, each of the grooves extending through the storage region and the stepped region to the In the peripheral region, the stacked structure above the stepped region has multiple steps, and the 3D memory device further includes: a first insulating layer covering the step and the peripheral region of the substrate, Wherein, the conductive channels respectively pass through the stacked structure and the first insulating layer toward the substrate. 13. The 3D memory device of claim 12, further comprising a channel epitaxial portion located between the substrate and the stacked structure, in contact with the channel layer and the epitaxial layer, respectively. 14. The 3D memory device of claim 13, further comprising a doped region in the substrate, the doped region being in contact with the epitaxial layer. 15. The 3D memory device of claim 12, further comprising a third insulating layer located between the conductive via and the stack structure.

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