CN109037227B - 3D memory device and method of manufacturing the same - Google Patents

Abstract

The application discloses a 3D memory device and a method of manufacturing the same. The 3D memory device includes: a stacked structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked; a plurality of channel pillars extending through the stacked structure; a plurality of bit lines on one of the first surface and the second surface of the stacked structure; and a common source line on the other of the first surface and the second surface of the stacked structure, wherein one ends of the plurality of channel pillars are respectively connected to corresponding bit lines of the plurality of bit lines, and the other ends are commonly connected to the common source line. The 3D memory device adopts the common source line and the bit line which are respectively positioned on the first surface and the second surface of the 3D memory device stacking structure, compared with single-sided wiring, the 3D memory device has the advantages that the wiring density can be reduced, the wiring width is increased, the parasitic resistance and the parasitic capacitance are reduced, the memory density and the access speed are improved, and therefore the yield and the reliability of the 3D memory device are improved.

Description

3D memory device and method of manufacturing the same

Technical Field

The present invention relates to the field of memory technology, and more particularly, to a 3D memory device and a method of manufacturing the same.

Background

The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As feature sizes of semiconductor fabrication processes become smaller, memory density of memory devices becomes higher. In order to further increase the storage density, three-dimensional structured memory devices (i.e., 3D memory devices) have been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can improve integration in multiple per unit area of a wafer, and can reduce cost.

Existing 3D memory devices are mainly used as nonvolatile flash memories. Two main non-volatile flash technologies employ NAND and NOR architectures, respectively. The read speed in the NAND memory device is slightly slower, but the write speed is fast, the erase operation is simple, and smaller memory cells can be realized, thereby achieving higher memory density, as compared to the NOR memory device. Therefore, 3D memory devices employing NAND structures have found wide application.

In a 3D memory device of a NAND structure, a stacked structure is employed to provide gate conductors of a selection transistor and a memory transistor, and a large number of metal wirings are employed to provide electrical connection of the transistors to external circuits. An increase in metal wiring density will affect the yield and reliability of the 3D memory device. Further improvements in the structure of 3D memory devices and methods of manufacturing the same are desired to increase the yield and reliability of 3D memory devices.

Disclosure of Invention

In view of the above, it is an object of the present invention to provide a 3D memory device and a method of manufacturing the same, in which a common source line and a bit line are respectively located at a first surface and a second surface of a stacked structure, thereby reducing a wiring density to improve yield and reliability of the 3D memory device.

According to an aspect of the present invention, there is provided a 3D memory device, comprising: a stacked structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked; a plurality of channel pillars extending through the stacked structure; a plurality of bit lines on one of the first surface and the second surface of the stacked structure; and a common source line on the other of the first surface and the second surface of the stacked structure, wherein one ends of the plurality of channel pillars are respectively connected to corresponding bit lines of the plurality of bit lines, and the other ends are commonly connected to the common source line.

Preferably, the plurality of channel pillars includes a first group of channel pillars and a second group of channel pillars adjacent to each other, the plurality of bit lines connected to the first group of channel pillars are located on the first surface of the stacked structure, the common source line connected to the first group of channel pillars is located on the second surface of the stacked structure, the plurality of bit lines connected to the second group of channel pillars is located on the second surface of the stacked structure, and the common source line connected to the second group of channel pillars is located on the first surface of the stacked structure.

Preferably, the method further comprises: CMOS circuitry adjacent to the first and/or second surfaces of the stacked structure.

Preferably, the method further comprises: a conductive path penetrating the laminated structure; a plurality of bit lines on one of the first and second surfaces of the stacked structure are connected to CMOS circuits adjacent to the other of the first and second surfaces through the conductive vias.

Preferably, the plurality of bit lines and the common source line at the first surface are connected to CMOS circuitry adjacent to the first surface; the plurality of bit lines and the common source line at the second surface are connected to CMOS circuitry adjacent the second surface.

According to another aspect of the present invention, there is provided a method of manufacturing a 3D memory device, including: forming a plurality of bit lines on one of the first surface and the second surface of the stacked structure; and forming a common source line on the other of the first surface and the second surface of the stacked structure.

Preferably, the method further comprises: forming the stacked structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked; forming a plurality of channel pillars through the stacked structure; one ends of the channel pillars are respectively connected to corresponding bit lines in the bit lines, and the other ends of the channel pillars are commonly connected to the common source line.

Preferably, the plurality of channel pillars includes a first group of channel pillars and a second group of channel pillars adjacent to each other, the plurality of bit lines connected to the first group of channel pillars are located on the first surface of the stacked structure, the common source line connected to the first group of channel pillars is located on the second surface of the stacked structure, the plurality of bit lines connected to the second group of channel pillars is located on the second surface of the stacked structure, and the common source line connected to the second group of channel pillars is located on the first surface of the stacked structure.

According to the 3D memory device and the manufacturing method thereof provided by the invention, the common source line and the bit line respectively positioned on the first surface and the second surface of the 3D memory device stacking structure are adopted, compared with single-sided wiring, the wiring density can be reduced, the wiring width can be increased, the parasitic resistance and the parasitic capacitance can be reduced, the storage density and the access speed can be improved, and therefore, the yield and the reliability of the 3D memory device can be improved.

In the prior art, a large number of through silicon vias (TSV, through Silicon Via) and through array contacts (TAC, through Array Contacts) are used to implement double-sided wiring of a 3D memory device. Compared with the prior art, the 3D memory provided by the embodiment of the invention adopts the common source line and the bit line which are respectively positioned on the first surface and the second surface of the 3D memory device stacking structure, and the common source line and the bit line can be directly connected with an external circuit through metal wires, so that the requirements of through silicon vias and penetrating array contact parts are reduced, the manufacturing process is simplified, and the yield and the reliability of the 3D memory device are improved.

Further, in the 3D memory device, a plurality of first common source lines and a plurality of second common source lines which are respectively located at the upper side and the lower side of the 3D memory device stacking structure and a plurality of first bit lines and a plurality of second bit lines which are respectively located at the upper side and the lower side of the 3D memory device stacking structure and are respectively located at the staggered distribution are adopted, so that staggered double-sided wiring can be realized, compared with non-staggered double-sided wiring, the staggered double-sided wiring can utilize the common source lines between the bit lines to isolate the two, parasitic resistance and parasitic capacitance are further reduced, storage density and access speed are improved, and yield and reliability of the 3D memory device are improved.

Further, in the 3D memory device, CMOS circuits respectively located at the upper and lower sides of the 3D memory device are used, and the CMOS circuits at the upper and lower sides are respectively connected with the drains at the upper and lower sides, so that not only is the wiring density reduced, but also the operation speed of the 3D memory device is improved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1a and 1b show an equivalent circuit diagram and a schematic structure diagram of a memory cell string of a 3D memory device, respectively.

Fig. 2 illustrates a perspective view of a 3D memory device according to an embodiment of the present invention.

Fig. 3a and 3b respectively show cross-sectional views of a 3D memory device according to an embodiment of the present invention.

Fig. 4a to 4t show cross-sectional views of various stages of a 3D memory device manufacturing method according to an embodiment of the invention.

Fig. 5 illustrates a cross-sectional view of a 3D memory device according to a first embodiment of the present invention.

Fig. 6 illustrates a cross-sectional view of a 3D memory device according to a second embodiment of the present invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The semiconductor structure obtained after several steps may be depicted in one figure for simplicity.

It will be understood that when a layer, an area, or a structure of a device is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or further layers or areas can be included between the other layer, another area, etc. And if the device is flipped, the one layer, one region, will be "under" or "beneath" the other layer, another region.

If, for the purposes of describing a situation directly overlying another layer, another region, the expression "directly overlying … …" or "overlying and adjoining … …" will be used herein.

In the present application, the term "semiconductor structure" refers to a generic term for the entire semiconductor structure formed in the various steps of fabricating a memory device, including all layers or regions that have been formed. Numerous specific details of the application, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a thorough understanding of the application. However, as will be understood by those skilled in the art, the present application may be practiced without these specific details.

In a 3D memory device of a NAND structure, a stacked structure is used to provide gate conductors of a select transistor and a memory transistor, and a large number of metal wirings are used to provide electrical connection. The increase of the metal wiring density not only increases the process cost and the process complexity, but also causes the problems of short circuit, increase of parasitic capacitance, increase of parasitic resistance and the like. In addition, the wiring distributed on one side may cause an increase in complexity of the CMOS circuit, thereby reducing the operation speed of the 3D memory device, affecting the yield and reliability of the 3D memory device.

The inventors of the present application have noted the above-described problem affecting the yield and reliability of the 3D memory device, and thus have proposed a further improved 3D memory device and a method of manufacturing the same.

The invention may be embodied in various forms, some examples of which are described below.

Fig. 1a and 1b show a circuit diagram and a schematic diagram of a memory cell string of a 3D memory device, respectively. The memory cell string shown in this embodiment includes a case of 4 memory cells. It is to be understood that the present invention is not limited thereto, and the number of memory cells in the memory cell string may be any number, for example, 32 or 64.

As shown in fig. 1a, the memory cell string 100 has a first terminal connected to the bit line BL and a second terminal connected to the source line SL. The memory cell string 100 includes a plurality of transistors connected in series between a first terminal and a second terminal, including: a first selection transistor Q1, memory transistors M1 to M4, and a second selection transistor Q2. The gate of the first selection transistor Q1 is connected to the string selection line SSL, and the gate of the second selection transistor Q2 is connected to the ground selection line GSL. The gates of the memory transistors M1 to M4 are connected to the corresponding word lines of the word lines WL1 to WL4, respectively.

As shown in fig. 1b, the first and second select transistors Q1 and Q2 of the memory cell string 100 include gate conductors 122 and 123, respectively, and the memory transistors M1 to M4 include gate conductors 121, respectively. The gate conductors 121, 122, and 123 are aligned with the stacking order of transistors in the memory cell string 100, and adjacent gate conductors are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel pillar 110. The channel pillar 110 penetrates the gate stack structure. In the middle portion of the channel pillar 110, a tunneling dielectric layer 112, a charge storage layer 113, and a blocking dielectric layer 114 are sandwiched between a gate conductor 121 and a channel layer 111, thereby forming memory transistors M1 to M4. A blocking dielectric layer 114 is interposed between the gate conductors 122 and 123 and the channel layer 111 at both ends of the channel pillar 110, thereby forming a first selection transistor Q1 and a second selection transistor Q2.

In this embodiment, the channel layer 111 is composed of, for example, doped polysilicon, the tunneling dielectric layer 112 and the blocking dielectric layer 114 are each composed of an oxide, for example, silicon oxide, the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals, for example, silicon nitride containing microparticles of a metal or semiconductor, and the gate conductors 121, 122, and 123 are composed of a metal, for example, tungsten. The channel layer 111 is used to provide channel regions for controlling the select and memory transistors, and the doping type of the channel layer 111 is the same as the type of the select and memory transistors. For example, for an N-type select transistor and a memory transistor, the channel layer 111 may be N-type doped polysilicon.

In this embodiment, the core of the channel pillar 110 is the channel layer 111, and the tunneling dielectric layer 112, the charge storage layer 113, and the blocking dielectric layer 114 form a stacked structure around the core sidewall. In an alternative embodiment, the core of channel pillar 110 is an additional insulating layer, and channel layer 111, tunneling dielectric layer 112, charge storage layer 113, and blocking dielectric layer 114 form a stacked structure around the core.

In this embodiment, the first and second selection transistors Q1 and Q2 and the memory transistors M1 to M4 use a common channel layer 111 and blocking dielectric layer 114. In the channel pillar 110, a channel layer 111 provides source and drain regions and channel layers of a plurality of transistors. In alternative embodiments, the semiconductor layers and the blocking dielectric layers of the first and second selection transistors Q1 and Q2 and the semiconductor layers and the blocking dielectric layers of the memory transistors M1 to M4 may be formed separately from each other.

In the write operation, the memory cell string 100 writes data to a selected one of the memory transistors M1 to M4 using FN tunneling efficiency. Taking the memory transistor M2 as an example, the ground selection line GSL is biased to about zero volt while the source line SL is grounded, so that the selection transistor Q2 corresponding to the ground selection line GSL is turned off, and the string selection line SSL is biased to the high voltage VDD, so that the selection transistor Q1 corresponding to the string selection line SSL is turned on. Further, BIT line BIT2 is grounded, word line WL2 is biased at a programming voltage VPG, e.g., around 20V, and the remaining word lines are biased at a low voltage VPS1. Since only the word line voltage of the selected memory transistor M2 is higher than the tunneling voltage, electrons in the channel region of the memory transistor M2 reach the charge storage layer 113 via the tunneling dielectric layer 112, thereby converting data into charges to be stored in the charge storage layer 113 of the memory transistor M2.

In the read operation, the memory cell string 100 judges the amount of charge in the charge storage layer according to the on state of a selected one of the memory transistors M1 to M4, thereby obtaining data representing the amount of charge. Taking memory transistor M2 as an example, word line WL2 is biased at read voltage VRD and the remaining word lines are biased at high voltage VPS2. The on state of the memory transistor M2 is related to its threshold voltage, i.e. to the amount of charge in the charge storage layer, so that the data value can be determined from the on state of the memory transistor M2. The memory transistors M1, M3, and M4 are always in the on state, and thus, the on state of the memory cell string 100 depends on the on state of the memory transistor M2. The control circuit judges the on state of the memory transistor M2 from the electric signals detected on the bit line BL and the source line SL, thereby obtaining the data stored in the memory transistor M2.

Fig. 2 illustrates a perspective view of a 3D memory device. For clarity, the various insulating layers in the 3D memory device are not shown in fig. 2.

The 3D memory device 200 shown in this embodiment includes 4*4 total 16 memory cell strings 100, each memory cell string 100 including 4 memory cells, thereby forming a memory array of 4x 4 total 64 memory cells. It is to be understood that the present invention is not limited thereto, and the 3D memory device may include any number of memory cell strings, for example 1024, and the number of memory cells in each memory cell string may be any number, for example 32 or 64.

In a 3D memory device, the memory cell strings include respective channel pillars 110, and common gate conductors 121, 122, and 123, respectively. The gate conductors 121, 122 and 123 are aligned with the stacking order of transistors in the memory cell string 100, and adjacent gate conductors are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure 120. The interlayer insulating layer is not shown in the drawing.

In this embodiment, the channel pillars include a plurality of first and second groups of channel pillars 110a and 110b alternately arranged, and the internal structure of the channel pillars 110a and 110b is shown in fig. 1b, which will not be described in detail herein. Channel pillars 110a and 110b extend through gate stack structure 120 and are arranged in an array. A first common source line 103a (not shown) is located on the substrate 101 and a second common source line 103b is located above the semiconductor structure. First ends of the plurality of first group channel pillars 110a are commonly connected to the first common source line 103a, and second ends of the plurality of first group channel pillars 110a are commonly connected to the plurality of first bit lines BL1. The second ends of the plurality of second group channel pillars 110b are commonly connected to the second common source line 103b, and the first ends of the plurality of second group channel pillars 110b are commonly connected to the plurality of first bit lines BL1.

The gate conductor 122 of the first select transistor Q1 is divided into different gate lines by a gate line slit (GATE LINE SLIT) 161. The gate lines of the plurality of channel pillars 110 of the same row are commonly connected to the same string selection line (i.e., one of the string selection lines SSL1 to SSL 3).

The gate conductors 121 of the memory transistors M1 and M4 are connected to the corresponding word lines, respectively. If the gate conductors 121 of the memory transistors M1 and M4 are divided into different gate lines by the gate line slit 161, the gate lines of the same level reach the interconnection layer 132 via respective conductive paths to be interconnected with each other and then connected to the same word line via the conductive path 133.

The gate conductors of the second selection transistors Q2 are connected in one piece. If the gate conductor 123 of the second selection transistor Q2 is divided into different gate lines by the gate line slit 161, the gate lines reach the interconnection layer 132 via respective conductive paths to be interconnected with each other and then are connected to the same ground selection line GSL via the conductive paths.

Further, a dummy channel pillar (not shown) may also be included in this embodiment, and the internal structure of the dummy channel pillar and the channel pillar 110 may be identical and pass through at least a portion of the gate conductor in the gate stack structure. However, the dummy channel pillars are not connected to the bit lines, and thus only provide mechanical support, and are not used to form select transistors and memory transistors. Thus, the dummy channel pillars also do not form an effective memory cell.

Fig. 3a and 3b respectively show cross-sectional views of a 3D memory device according to an embodiment of the present invention. The cross-sectional view is taken perpendicular to the stacking direction.

As shown in fig. 3a, the second common source lines 103b are alternately distributed with the plurality of first bit lines BL1 on the second surface of the stacked structure, as viewed from top to bottom in the semiconductor structure, perpendicular to the stacked direction. The second common source line 103b is connected to the second ends of the plurality of second group channel pillars 110b, and the plurality of first word lines BL1 are connected to the second ends of the plurality of first group channel pillars 110 a.

As shown in fig. 3b, the first common source line 103a and the plurality of second bit lines BL2 are alternately distributed on the first surface of the stacked structure, as viewed from bottom to top in the semiconductor structure, perpendicular to the stacking direction. The first common source line 103a is connected to first ends of the plurality of first group channel pillars 110a, and the plurality of second bit lines BL2 is connected to first ends of the plurality of second group channel pillars 110 b.

Fig. 4a to 4q show cross-sectional views of various stages of a 3D memory device manufacturing method according to an embodiment of the invention. The cross-sectional view is taken along line AA in fig. 2.

The method starts with a semiconductor structure in which a plurality of well regions have been formed on a substrate 101, as shown in fig. 4 a. In this embodiment, the semiconductor substrate 101 is, for example, a single crystal silicon substrate.

In this embodiment, in order to facilitate a programming operation for memory cells in a 3D memory device, a plurality of well regions are formed in the substrate 101. The plurality of well regions include, for example, a deep N-well 102, a high voltage P-well 103 located in the deep N-well 102, a high voltage N-well 105 adjacent to the high voltage P-well 103, a p+ doped region 104 located in the high voltage P-well 103, and an n+ doped region 106 located in the high voltage N-well 105. In this embodiment, the high voltage P-well 103 serves as a common source line of the channel pillar, the high voltage N-well 105 is used to precharge the common source line, and the p+ doped region 104 and the n+ doped region 106 serve as contact regions, respectively, to reduce contact resistance. After etching the high voltage P-well 103, a common source line 103a, which is a plurality of first group channel pillars, is located under the insulating stack structure, as described below.

Further, a mask, such as a photoresist mask, is formed, for example, on the surface of the semiconductor structure, and then anisotropically etched to form trenches 160 in the substrate 101, as shown in fig. 4b and 4 c. In this embodiment, the anisotropic etching may employ dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. For example, by controlling the etching time, the etching is stopped near the bottom of the deep N-well 102.

Further, the photoresist mask is removed after etching by dissolution in a solvent or ashing, as shown in fig. 4 d.

Further, a first insulating region 153 is formed in the trench 160, as shown in fig. 4 e. In this embodiment, the first insulating region 153 is composed of, for example, silicon oxide.

Further, an insulating stack structure is formed on the substrate 101, as shown in fig. 4 f. The insulating stack structure includes a plurality of interlayer insulating layers 151 and a plurality of sacrificial layers 152 alternately stacked. In this embodiment, the interlayer insulating layer 151 is composed of, for example, silicon oxide, and the sacrificial layer 152 is composed of, for example, silicon nitride.

As described below, the sacrificial layer 152 will be replaced with a gate conductor 122, which gate conductor 122 is further connected to a word line. To form a conductive path from gate conductor 122 to the word line, a plurality of sacrificial layers 152 are, for example, patterned in a step-like manner, i.e., an edge portion of each sacrificial layer 152 is exposed with respect to the overlying sacrificial layer to provide an electrical connection region. After the patterning step of the plurality of sacrificial layers 152, an insulating layer may be used to cover the insulating stack structure. In fig. 4f, the interlayer insulating layer 151 between the plurality of sacrificial layers 152 and the interlayer insulating layer covering the insulating stacked structure are integrally shown. However, the present invention is not limited thereto, and the interlayer insulating layer between and over the plurality of sacrificial layers 152 may be formed using a plurality of independent deposition steps.

Further, a channel hole 161 is formed in an intermediate region (core region) in the insulating stack structure, as shown in fig. 4 g. In this embodiment, for example, a photoresist mask is formed on the surface of the semiconductor structure, and then anisotropic etching is performed to form the channel hole 161 in the insulating stack structure. The anisotropic etching may be dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. For example, by controlling the etching time, the etching is stopped in the vicinity of the lower side of the first common source line 103a, and the etching is stopped in the vicinity of the lower side of the first insulating region 153. The photoresist mask is removed after etching by dissolution in a solvent or ashing.

Further, a channel pillar 110 is formed in the channel hole 161, as shown in fig. 4 h. The lower portion of the channel pillar 110 includes a semiconductor layer 116, the semiconductor layer 116 being, for example, a silicon selective epitaxial growth layer. Further, the channel pillar 110 includes a channel layer 111 extending from an upper portion thereof to the semiconductor layer 116. As shown, at the middle portion of the channel pillar 110, the channel pillar 110 includes a tunneling dielectric layer 112, a charge storage layer 113, and a blocking dielectric layer 114 sequentially stacked on the channel layer 111, and at both ends of the channel pillar 110, the channel pillar 110 includes a blocking dielectric layer 114 stacked on the channel layer 111 or the semiconductor layer 116. The lower end of the channel pillar 110 is in contact with the high voltage P-well 103 in the semiconductor substrate 101. In the final 3D memory device, the upper ends of the channel pillars 110 are connected to bit lines, thereby forming an effective memory cell. The channel pillar 110 has a structure such as ONOP (oxide-nitride-oxide-polysilicon)

Further, a gate line slit 161 (see fig. 2) is formed in the insulating stack structure, a plurality of interlayer insulating layers 151 are used as an etch stop layer, a sacrificial layer 152 is removed by etching through the gate line slit 161 to form a cavity, and a metal layer is used to fill the cavity to form a gate conductor 122, wherein the plurality of gate conductors 122 and the plurality of interlayer insulating layers 151 are alternately stacked such that the plurality of channel pillars 110 penetrate the gate stack structure, as shown in fig. 4 i.

In forming the gate line slit 161, anisotropic etching may be employed, for example, dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. For example, by controlling the etching time, etching is stopped near the surface of the semiconductor substrate 101.

In this embodiment, the gate line slit 161 divides the gate conductor 122 into a plurality of gate lines. For this purpose, the gate line slit 161 penetrates the insulating stack structure.

In forming the cavity, the sacrificial layer 152 in the insulating stack structure is removed by isotropic etching using the gate line slit 161 as an etchant passage to form the cavity. The isotropic etching may employ selective wet etching or vapor etching. An etching solution is used as an etchant in wet etching, wherein the semiconductor structure is immersed in the etching solution. An etching gas is used as an etchant in a gas phase etching, wherein the semiconductor structure is exposed to the etching gas.

In the case where the interlayer insulating layer 151 and the sacrificial layer 152 in the insulating stack structure are composed of silicon oxide and silicon nitride, respectively, a phosphoric acid solution may be used as an etchant in wet etching, and one or more of C4F8, C4F6, CH2F2, and O2 may be used in vapor etching. In the etching step, the etchant fills the gate line slit 161. The end of the sacrificial layer 152 in the insulating stack structure is exposed in the opening of the gate line slit 161, and thus, the sacrificial layer 152 is contacted to the etchant. The etchant gradually etches the sacrificial layer 152 from the opening of the gate line slit 161 toward the inside of the insulating stack structure. Due to the selectivity of the etchant, the etching removes the sacrificial layer 152 with respect to the interlayer insulating layer 151 in the insulating stack structure.

In forming the gate conductor 122, atomic Layer Deposition (ALD) is used to fill the gate line slit 161 and the cavity with a metal layer using the gate line slit 161 as a deposition path.

In this embodiment, the metal layer is composed of tungsten, for example. The precursor source used in atomic layer deposition is, for example, tungsten hexafluoride WF6, and the reducing gas used is, for example, silane SiH4 or diborane B2H6. In the step of atomic layer deposition, a deposition process is performed by obtaining a tungsten material by chemisorption of a reaction product of tungsten hexafluoride WF6 and silane SiH 4.

In the semiconductor structure, a selection transistor and a memory transistor are formed. In the middle portion of the channel pillar 110, the gate conductor 122 forms a memory transistor together with the channel layer 111, the tunneling dielectric layer 112, the charge storage layer 113, and the blocking dielectric layer 114 inside the channel pillar 110. At both ends of the channel pillar 110, a gate conductor 122 forms a select transistor together with the channel layer 111 (or semiconductor layer 116) and the blocking dielectric layer 114 inside the channel pillar 110.

Further, a recess 162 is formed in the insulating layer over the first group of channel pillars 110a over the first common source line 103a, as shown in fig. 4 j. In this embodiment, a photoresist mask is formed, for example, on the surface of the semiconductor structure, and then anisotropically etched to form a recess 162 in the insulating stack structure. The anisotropic etching may be dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. For example, by controlling the etching time, the etching is stopped at a distance inside the surface of the first group of channel pillars 110a above the first common source line 103 a. The photoresist mask is removed after etching by dissolution in a solvent or ashing.

Further, a conductor layer 171a is formed in the groove 162, as shown in fig. 4 k. In this embodiment, conductor layer 171a provides an electrical connection between the channel pillar and the bit line, and conductor layer 171a is, for example, tungsten.

Further, a groove 163 is formed over the second group of channel pillars 110b located over the first insulating region 153, as shown in fig. 4l and 4 m. In this embodiment, for example, a photoresist mask is formed on the surface of the semiconductor structure, and then anisotropic etching is performed to form the recess 163 in the insulating stack structure. The anisotropic etching may be dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. For example, by controlling the etching time, the etching is stopped at a distance inside the surface of the second group of channel pillars 110 b. The photoresist mask is removed after etching by dissolution in a solvent or ashing.

Further, a second common source line 103b is formed in the recess 163, as shown in fig. 4 n. In this embodiment, the second common source line 103b is, for example, a high voltage p-well.

Further, a plurality of first bit lines BL1 are formed on the conductor layer 171a, and a pad 182 is formed on the second common source line 103b, second ends of the plurality of first group channel pillars 110a are commonly connected to the first bit lines BL1, an insulating material 183 is filled around the plurality of first bit lines BL1 and the second common source line 103b to fix the plurality of first bit lines BL1 and the second common source line 103b, and a surface of the insulating material 183 is smoothed, as shown in fig. 4 o. The first bit line BL1 and the bonding pad 182 are composed of, for example, ti/TiN or W, and the insulating material 183 is, for example, silicon oxide. A method of smoothing the surface of the insulating material 183 is, for example, chemical mechanical polishing.

Further, the semiconductor structure is flipped and the substrate is thinned, as shown in fig. 4 p. For example, the substrate is thinned by grinding and/or etching, including dry etching or wet etching, and etching is stopped on the oxide material by controlling the etching time.

Further, a conductor layer 171b is formed over the second group of channel pillars 110b, as shown in fig. 4 q. The conductor layer 171b provides an electrical connection between the channel pillars and the bit lines, and the conductor layer 171 is, for example, tungsten.

Further, a plurality of second bit lines BL2 are formed on the conductor layer 171b, and a pad 182 is formed on the first common source line 103a, first ends of the plurality of second group channel pillars 110b being commonly connected to the second bit lines BL2, as shown in fig. 4 r. The second bit line BL2 and the pad 182 are composed of, for example, ti/TiN or W.

Further, a plurality of conductive vias are formed over the gate stack structure of the semiconductor structure, as shown in fig. 4 s. The plurality of conductive channels in the 3D memory device respectively include conductive pillars 131 as cores and insulating layers 134 as isolation layers, the insulating layers 134 serving to separate the conductive pillars 131 and surrounding conductive material from each other. The plurality of conductive channels includes, for example, conductive channels SL1, HV1. Conductive vias SL1 and HV1 are in contact with p+ doped region 104 and n+ doped region 106, respectively, to provide electrical connection between the common source line and the high voltage N-well and external circuitry.

Further, to facilitate a programming operation of memory cells in the 3D memory device, in this embodiment, the 3D memory device further includes a CMOS circuit 200 for driving the select transistor and the memory transistor, as shown in fig. 4 t. The CMOS circuit 200 is formed, for example, directly in the substrate, or directly on or over the array, or formed separately and then bonded into the semiconductor structure.

In this embodiment, the step of separately forming the CMOS circuit and then connecting to the semiconductor structure includes: the interconnect layer 232 of the CMOS circuit 200 is aligned with the interconnect layer 132 of the semiconductor structure and then the interconnect layer 232 of the CMOS circuit 200 is brought into contact with the interconnect layer 132 of the semiconductor structure, and a bonding process is performed to form a bonding interface. The bonding process includes, for example, a plasma treatment process, a wet process, and/or a thermal treatment process, such that a surface of the interconnect layer 232 of the CMOS circuit 200 forms a physical or chemical bond with a surface of the interconnect layer 132 of the semiconductor structure. In some embodiments, the interconnect layer 132 of the semiconductor structure is, for example, a silicon oxide layer, and the interconnect layer 232 of the CMOS circuit 200 is, for example, a silicon nitride layer. In some embodiments, interconnect layer 132 of the semiconductor structure and interconnect layer 232 of CMOS circuit 200 each comprise copper, for example.

Fig. 5 illustrates a cross-sectional view of a 3D memory device according to a first embodiment of the present invention. The cross-sectional view is taken along line AA in fig. 2.

As shown in fig. 5, the CMOS circuit 200 is located, for example, above or below the semiconductor structure, and the drains located on both sides of the semiconductor structure are electrically connected through a plurality of conductive paths, and then bonded to the external CMOS circuit 200. In this embodiment, the drain electrode includes a plurality of first bit lines BL1 and a plurality of second bit lines BL2, and the plurality of conductive channels include conductive pillars 131 as cores and insulating layers 134 of isolation layers, respectively, the insulating layers 134 being used to isolate the conductive pillars 131 from surrounding conductive materials, and the CMOS circuit 200 is capable of simultaneously operating transistors of the first group of channel pillars 110a and the gate stack structure and transistors of the second group of channel pillars 110b and the gate stack structure.

Fig. 6 illustrates a cross-sectional view of a 3D memory device according to a second embodiment of the present invention. The cross-sectional view is taken along line AA in fig. 2.

As shown in fig. 6, the CMOS circuit 300 and the CMOS circuit 200 are located above and below the semiconductor structure, respectively, and the drains located on the upper and lower sides of the semiconductor structure are connected to the CMOS circuit 300 and the CMOS circuit 200, respectively. In this embodiment, the drain electrode includes a plurality of first bit lines BL1 and a plurality of second bit lines BL2, the plurality of conductive channels include conductive pillars 131 as cores and insulating layers 134 as isolation layers, respectively, the insulating layers 134 are used to separate the conductive pillars 131 from surrounding conductive materials, the CMOS circuit 300 controls transistors formed by the first group of channel pillars 110a and the gate stack structure, and the CMOS circuit 200 controls transistors formed by the second group of channel pillars 110b and the gate stack structure. The distribution of the two sides of the CMOS circuit reduces the wiring density, and the separate control of the two sets of transistors by the two sets of CMOS circuits further increases the operating speed of the 3D memory device.

In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.

The embodiments of the present invention are described above. These examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the invention, and such alternatives and modifications are intended to fall within the scope of the invention.

Claims (5)

1. A 3D memory device, comprising:

A stacked structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked;

A plurality of channel columns penetrating through the laminated structure, wherein the channel columns are of oxide-nitride-oxide-polysilicon;

A plurality of bit lines on one of the first surface and the second surface of the stacked structure; and

A common source line on the other of the first and second surfaces of the stacked structure,

Wherein one ends of the plurality of channel pillars are respectively connected to corresponding bit lines of the plurality of bit lines, and the other ends are commonly connected to the common source line, the plurality of channel pillars including a first group of channel pillars and a second group of channel pillars adjacent to each other,

The plurality of bit lines to which the first set of channel pillars are connected are located on the first surface of the stacked structure, the common source line to which the first set of channel pillars are connected is located on the second surface of the stacked structure,

The plurality of bit lines to which the second set of channel pillars are connected are located on the second surface of the stacked structure, and the common source line to which the second set of channel pillars are connected is located on the first surface of the stacked structure.

2. The 3D memory device of claim 1, further comprising: CMOS circuitry adjacent to the first and/or second surfaces of the stacked structure.

3. The 3D memory device of claim 2, further comprising:

A conductive path penetrating the laminated structure;

a plurality of bit lines on one of the first and second surfaces of the stacked structure are connected to CMOS circuits adjacent to the other of the first and second surfaces through the conductive vias.

4. The 3D memory device of claim 2, wherein,

The plurality of bit lines and the common source line at the first surface are connected to CMOS circuitry adjacent the first surface;

the plurality of bit lines and the common source line at the second surface are connected to CMOS circuitry adjacent the second surface.

5. A method of manufacturing a 3D memory device, comprising:

forming a stacked structure including a plurality of gate conductors and a plurality of interlayer insulating layers alternately stacked;

Forming a plurality of channel columns penetrating through the laminated structure, wherein the channel columns are formed by oxide-nitride-oxide-polysilicon;

forming a plurality of bit lines on one of a first surface and a second surface of the stacked structure; and

A common source line is formed on the other of the first and second surfaces of the stacked structure,

Wherein one ends of the plurality of channel pillars are respectively connected to corresponding bit lines of the plurality of bit lines, and the other ends are commonly connected to the common source line, the plurality of channel pillars including a first group of channel pillars and a second group of channel pillars adjacent to each other,

The plurality of bit lines to which the first set of channel pillars are connected are located on the first surface of the stacked structure, the common source line to which the first set of channel pillars are connected is located on the second surface of the stacked structure,

The plurality of bit lines to which the second set of channel pillars are connected are located on the second surface of the stacked structure, and the common source line to which the second set of channel pillars are connected is located on the first surface of the stacked structure.