CN111490047B - memory structure - Google Patents

Abstract

The invention discloses a memory structure, which includes a first transistor, a second transistor and a capacitor. The first transistor includes a first gate electrode and first and second doped regions located on both sides of the first gate electrode. The first doped region and the second doped region are arranged in the first direction. The second transistor includes a second gate electrode and third and fourth doped regions located on both sides of the second gate electrode. The second doped region and the third doped region are located between the first gate electrode and the second gate electrode. The second doped region and the third doped region are arranged in the second direction. The second direction intersects the first direction. The capacitor is coupled to the second doped region and the third doped region.

Description

memory structure

Technical field

The present invention relates to a semiconductor structure, and in particular to a memory structure.

Background technique

A memory structure has been developed that includes transistors and capacitors coupled to each other. In this memory structure, capacitors are used as storage components. Therefore, how to increase the capacitance of capacitors to improve the electrical performance of memory components is a goal that the industry continues to strive for.

Contents of the invention

The present invention provides a memory structure that can effectively increase the capacitance of the capacitor, thereby improving the electrical performance of the memory component.

The invention proposes a memory structure, including a first transistor, a second transistor and a capacitor. The first transistor includes a first gate electrode and first and second doped regions located on both sides of the first gate electrode. The first doped region and the second doped region are arranged in the first direction. The second transistor includes a second gate electrode and third and fourth doped regions located on both sides of the second gate electrode. The second doped region and the third doped region are located between the first gate electrode and the second gate electrode. The second doped region and the third doped region are arranged in the second direction. The second direction intersects the first direction. The capacitor is coupled to the second doped region and the third doped region.

According to an embodiment of the present invention, in the above memory structure, the first transistor and the second transistor may be one or the other of a P-type metal oxide semiconductor transistor and an N-type metal oxide semiconductor transistor, respectively.

According to an embodiment of the present invention, in the above memory structure, the capacitor may extend in the second direction.

According to an embodiment of the present invention, in the above memory structure, the third doped region and the fourth doped region may be arranged in the third direction. The third direction may intersect the second direction.

According to an embodiment of the present invention, in the above memory structure, the first direction may be parallel to the third direction.

According to an embodiment of the present invention, in the above memory structure, the extending direction of the gate of the first transistor may intersect with the first direction and may not be perpendicular to the second direction. The extending direction of the gate of the second transistor may intersect the third direction and may not be perpendicular to the second direction.

According to an embodiment of the present invention, in the above memory structure, the first transistor and the second transistor coupled to the capacitor may be arranged in a staggered manner.

According to an embodiment of the present invention, the above memory structure may further include a dielectric layer. The dielectric layer covers the first transistor and the second transistor and has at least one opening. Capacitors can be located in the openings.

According to an embodiment of the present invention, the above memory structure may further include an isolation structure. The isolation structure may be located between the second doped region and the third doped region.

According to an embodiment of the present invention, in the above memory structure, the number of openings may be one. The opening can expose the second doped region, the third doped region and the isolation structure.

According to an embodiment of the present invention, in the above memory structure, the number of openings may be multiple. Each opening may expose at least one of the second doped region, the third doped region and the isolation structure.

According to an embodiment of the present invention, the above memory structure may further include a contact window. The contact window is coupled to the capacitor. The contact window may be located over at least one of the isolation structure, the second doped region, and the third doped region.

Based on the above, in the memory structure proposed by the present invention, the first doped region and the second doped region are arranged in the first direction, the second doped region and the third doped region are arranged in the second direction, and the first doped region and the second doped region are arranged in the second direction. The two directions intersect the first direction, and the capacitor is coupled to the second doping region and the third doping region. Through the above arrangement, the size of the capacitor can be effectively increased without increasing the chip area, so the capacitance of the capacitor can be effectively increased, thereby improving the electrical performance of the memory component.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, embodiments are given below and described in detail with reference to the attached drawings.

Description of the drawings

Figure 1 is a top view of a memory structure according to an embodiment of the present invention;

Figure 2 is a cross-sectional view of the memory structure along the I-I’ section line in Figure 1;

Figure 3 is a top view of a memory structure according to another embodiment of the present invention;

FIG. 4 is a cross-sectional view of the memory structure along the II-II' cross-sectional line in FIG. 3 .

Symbol Description

100, 200: memory structure

102: Base

104, 106: Transistor

108, 208: Capacitor

108a, 108b, 208a, 208b: electrode

108c, 208c: insulation layer

110, 112: Well area

114: Isolation structure

116, 134: Gate

118, 120, 136, 138: Doping area

122, 140, 152: Dielectric layer

124, 142: Gap wall

126, 128, 144, 146: Lightly doped drain

130, 132, 148, 150: metal silicide layer

152a, 152b: opening

154, 158, 202: Contact window

156, 160, 164, 168, 172, 204, 206, 210, 212: barrier layer

162, 166, 170: Conductor layer

D1: first direction

D2: Second direction

D3: Third direction

ED1, ED2: extension direction

Detailed ways

FIG. 1 is a top view of a memory structure according to an embodiment of the present invention. Figure 2 is a cross-sectional view of the memory structure along the line I-I' in Figure 1. In FIG. 1 , some components in FIG. 2 are omitted to clearly illustrate the configuration relationship between transistors and capacitors. In addition, the proportional relationship between the components in Figure 1 and Figure 2 is only for schematic illustration, and the present invention is not limited thereto. In this embodiment, the content about "direction" is shown in Figure 1 .

Referring to FIGS. 1 and 2 , the memory structure 100 includes a substrate 102 , a transistor 104 , a transistor 106 and a capacitor 108 . The memory structure 100 is, for example, a two-transistor static random access memory (2T SRAM), but the invention is not limited thereto. The substrate 102 is, for example, a semiconductor substrate, such as a silicon substrate. Capacitor 108 may be coupled between transistor 104 and transistor 106 .

Hereinafter, the first conductivity type and the second conductivity type described may be one or the other of P-type conductivity type and N-type conductivity type respectively. In this embodiment, the first conductivity type is a P-type conductivity type, and the second conductivity type is an N-type conductivity type, for example, but the invention is not limited thereto. In another embodiment, the first conductivity type may be an N-type conductivity type, and the second conductivity type may be a P-type conductivity type.

The memory structure 100 may also include at least one of a well region 110, a well region 112, and an isolation structure 114. Well region 110 is located in substrate 102 . The well region 110 may have a first conductivity type (eg, P type). The well region 112 is located in the substrate 102 on one side of the well region 110 . The well region 112 may have a second conductivity type (eg, N-type).

The isolation structure 114 is disposed in the substrate 102 and is located between the well region 110 and the well region 112 . The isolation structure 114 is, for example, a shallow trench isolation structure (shallow trench isolation, STI). The material of the isolation structure 114 is, for example, silicon oxide.

The transistor 104 and the transistor 106 may be one or the other of a P-type metal oxide semiconductor transistor and an N-type metal oxide semiconductor transistor, respectively. In this embodiment, the transistor 104 may have a first conductivity type (P-type), and the transistor 106 may have a second conductivity type (N-type). That is, the transistor 104 is a P-type metal oxide semiconductor transistor, and the transistor 106 is an N-type metal oxide semiconductor transistor, but the invention is not limited thereto.

The transistor 104 includes a gate 116 and doped regions 118 and 120 located on both sides of the gate 116 . The doped regions 118 and 120 are arranged in the first direction D1. The material of the gate 116 is, for example, doped polysilicon. In some embodiments, transistor 104 may also include a metal suicide layer (not shown) disposed on gate 116 . The doped regions 118 and 120 may be located in the substrate 102 on both sides of the gate 116 . In addition, the doped regions 118 and 120 may be located in the well region 112 . The doped region 118 and the doped region 120 can respectively serve as a source electrode or a drain electrode. The doped regions 118 and 120 may have a first conductivity type (eg, P-type).

In addition, the transistor 104 may further include at least one of a dielectric layer 122, a spacer 124, a lightly doped drain (LDD) 126, a lightly doped drain 128, a metal silicide layer 130, and a metal silicide layer 132. One. The dielectric layer 122 is located between the gate electrode 116 and the substrate 102 so that the gate electrode 116 and the substrate 102 can be insulated from each other. The material of the dielectric layer 122 is, for example, silicon oxide.

The spacers 124 are disposed on the sidewalls of the gate 116 . The spacer 124 may be a single-layer structure or a multi-layer structure. The material of the spacer 124 is, for example, silicon oxide, silicon nitride or a combination thereof.

A lightly doped drain 126 is located in the substrate 102 between the gate 116 and the doped region 118 . A lightly doped drain 128 is located in the substrate 102 between the gate 116 and the doped region 120 . In addition, the lightly doped drain 126 and the lightly doped drain 128 may be located in the well region 112 . The lightly doped drain 126 and the lightly doped drain 128 may have a first conductivity type (eg, P-type). In some embodiments, "lightly doped drain (LDD)" may also be referred to as "source/drain extension (SDE)").

Metal suicide layer 130 is disposed on doped region 118 . Metal suicide layer 132 is disposed on doped region 120 . The material of the metal silicide layer 130 and the metal silicide layer 132 is, for example, nickel silicide or cobalt silicide.

The transistor 106 includes a gate 134 and doped regions 136 and 138 located on both sides of the gate 134 . The doped region 120 and the doped region 136 are located between the gate electrode 116 and the gate electrode 134 . Isolation structure 114 may be located between doped region 120 and doped region 136 . The doped regions 120 and 136 are arranged in the second direction D2. The second direction D2 intersects the first direction D1. In addition, the doped regions 136 and 138 may be arranged in the third direction D3. The third direction D3 may intersect the second direction D2. The first direction D1 may be parallel to the third direction D3, but the invention is not limited thereto. In addition, the extending direction ED1 of the gate electrode 116 of the transistor 104 may intersect the first direction D1 and may not be perpendicular to the second direction D2. The extension direction ED2 of the gate 134 of the transistor 106 may intersect the third direction D3 and may not be perpendicular to the second direction D2.

The material of the gate 134 is, for example, doped polysilicon. In some embodiments, the transistor 106 may further include a metal suicide layer (not shown) disposed on the gate 134 . The doped regions 136 and 138 may be located in the substrate 102 on both sides of the gate 134 . In addition, the doped regions 136 and 138 may be located in the well region 110 . The doped region 136 and the doped region 138 can respectively serve as a source electrode or a drain electrode. The doped regions 136 and 138 may have a second conductivity type (eg, N-type).

In addition, the transistor 106 may further include at least one of a dielectric layer 140 , a spacer 142 , a lightly doped drain 144 , a lightly doped drain 146 , a metal suicide layer 148 and a metal suicide layer 150 . The dielectric layer 140 is located between the gate electrode 134 and the substrate 102 so that the gate electrode 134 and the substrate 102 can be insulated from each other. The material of the dielectric layer 140 is, for example, silicon oxide.

The spacers 142 are disposed on the sidewalls of the gate 134 . The spacer 142 may be a single-layer structure or a multi-layer structure. The material of the spacer 142 is, for example, silicon oxide, silicon nitride or a combination thereof.

A lightly doped drain 144 is located in the substrate 102 between the gate 134 and the doped region 136 . A lightly doped drain 146 is located in the substrate 102 between the gate 134 and the doped region 138 . In addition, the lightly doped drain 144 and the lightly doped drain 146 may be located in the well region 110 . The lightly doped drain 144 and the lightly doped drain 146 may have a second conductivity type (eg, N-type).

Metal suicide layer 148 is disposed on doped region 136 . Metal suicide layer 150 is disposed on doped region 138 . The material of the metal silicide layer 148 and the metal silicide layer 150 is, for example, nickel silicide or cobalt silicide.

Memory structure 100 may also include dielectric layer 152 . The dielectric layer 152 covers the transistor 104 and the transistor 106 and has at least one opening 152a. Capacitor 108 may be located in opening 152a. In this embodiment, the number of openings 152a may be one, and the opening 152a may be a slot, but the invention is not limited thereto. The opening 152a may expose the doped region 120, the doped region 136 and the isolation structure 114, and may also expose the metal silicide layer 132 and the metal silicide layer 148. The dielectric layer 152 may be a multi-layer structure. The material of the dielectric layer 152 is, for example, silicon oxide, silicon nitride or a combination thereof.

Capacitor 108 is coupled to doped region 120 and doped region 136 . Therefore, the capacitor 108 may extend in the second direction D2, and the transistors 104 and 106 coupled to the capacitor 108 may be arranged in a staggered manner. The capacitor 108 may include an electrode 108a, an electrode 108b, and an insulating layer 108c. The electrode 108a can be directly connected to the doping region 120 and the doping region 136, and can also be directly connected to the metal silicide layer 132 and the metal silicide layer 148, but the invention is not limited thereto. Electrode 108a may serve as the lower electrode of capacitor 108. The electrode 108b is provided on the electrode 108a. Electrode 108b may serve as the upper electrode of capacitor 108. The materials of the electrodes 108a and 108b are, for example, Ti, TiN, Ta, TaN, Al, In, Nb, Hf, Sn, Zn, Zr, Cu, Y, W, Pt or combinations thereof. The insulating layer 108c is provided between the electrode 108a and the electrode 108b. The material of the insulating layer 108c is, for example, a high-k material, silicon oxide, silicon nitride, silicon oxide/silicon nitride/silicon oxide (oxide-nitride-oxide, ONO) or a combination thereof. The high dielectric constant material is, for example, tantalum oxide (Ta ₂ O ₅ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), zirconium oxide (ZrO ₂ ) or combinations thereof. In the capacitor 108, since the insulating layer 108c is disposed between the electrode 108a and the electrode 108b, a metal-insulator-metal (MIM) capacitor can be formed.

Memory structure 100 may also include contacts 154 in dielectric layer 152, barrier layer 156, contact 158, barrier layer 160, conductor layer 162, barrier layer 164, conductor layer 166, barrier layer 168, conductor At least one of layer 170 and barrier layer 172 . Contact 154 is coupled to doped region 118 . Barrier layer 156 may be disposed between contact window 154 and metal suicide layer 130 . Contact 158 is coupled to doped region 138 . Barrier layer 160 may be disposed between contact window 158 and metal suicide layer 150 . The material of the contact window 154 and the contact window 158 is, for example, tungsten. The material of the barrier layer 156 and the barrier layer 160 is, for example, titanium, titanium nitride or a combination thereof.

Conductor layer 162 is coupled to contact 154 . The barrier layer 164 is disposed between the conductor layer 162 and the contact window 154 . Conductor layer 166 is coupled to contact 158 . Barrier layer 168 is disposed between conductor layer 166 and contact window 158 . Conductor layer 170 is coupled to electrode 108b. Barrier layer 172 is disposed between conductor layer 170 and electrode 108b. The material of the conductor layer 162, the conductor layer 166 and the conductor layer 170 is, for example, aluminum (Al), copper (Cu) or a combination thereof. The material of the barrier layer 164, the barrier layer 168 and the barrier layer 172 is, for example, titanium, titanium nitride or a combination thereof.

Based on the above embodiments, it can be seen that in the memory structure 100, the doped regions 118 and 120 are arranged in the first direction D1, the doped regions 120 and the doped regions 136 are arranged in the second direction D2, and the doped regions 118 and 120 are arranged in the second direction D2. Intersecting the first direction D1 , the capacitor 108 is coupled to the doping region 120 and the doping region 136 . Through the above arrangement, the size of the capacitor 108 can be effectively increased without increasing the chip area. Therefore, the capacitance of the capacitor 108 can be effectively increased, thereby improving the electrical performance of the memory component.

FIG. 3 is a top view of a memory structure according to another embodiment of the present invention. FIG. 4 is a cross-sectional view of the memory structure along the II-II' cross-sectional line in FIG. 3 . In FIG. 3 , some components in FIG. 4 are omitted to clearly illustrate the configuration relationship between the transistor and the capacitor. In addition, the proportional relationship between the components in Figure 3 and Figure 4 is only for schematic illustration, and the present invention is not limited thereto. In this embodiment, the content about "direction" is shown in Figure 3 .

Please refer to FIGS. 1 to 4 at the same time. The differences between the memory structures 200 of FIG. 3 and FIG. 4 and the memory structures 100 of FIG. 1 and FIG. 2 are as follows. In the memory structure 200, the number of openings 152b in the dielectric layer 152 may be multiple, and the openings 152b may be via holes. Each opening 152b may expose at least one of the doped region 120, the doped region 136, and the isolation structure 114. For example, the opening 152b may only expose the doped region 120, the opening 152b may only expose the doped region 136, the opening 152b may simultaneously expose the doped region 120 and the isolation structure 114, or the opening 152b may simultaneously expose the doped region. 136 and isolation structure 114. In addition, although not shown in FIGS. 3 and 4 , in other embodiments, the opening 152 b may simultaneously expose the doped region 120 , the doped region 136 and the isolation structure 114 . The electrodes 208a, 208b and insulating layer 208c in the capacitor 208 can respectively extend into the plurality of openings 152b, thereby further increasing the capacitance of the capacitor 208. Regarding the arrangement, materials, and functions of each component in the capacitor 208, reference may be made to the content of the capacitor 108 described above and will not be described here.

In addition, the memory structure 200 may further include at least one of a contact window 202, a barrier layer 204, a barrier layer 206, a barrier layer 210, and a barrier layer 212. Contact 202 is coupled to capacitor 208 . Therefore, the conductor layer 170 can be coupled to the capacitor 208 through the barrier layer 172, the contact window 202, and the barrier layer 204. Additionally, the contact window 202 may be located over at least one of the isolation structure 114 , the doped region 120 , and the doped region 136 . In this embodiment, the contact window 202 is located above the isolation structure 114, but the invention is not limited to this. In other embodiments, the contact window 202 may be located only above the doped region 120 , the contact window 202 may be located only above the doped region 136 , the contact window 202 may be located above both the isolation structure 114 and the doped region 120 , the contact window 202 may be The contact window 202 may be located above the isolation structure 114 and the doped region 136 at the same time or the contact window 202 may be located above the isolation structure 114 , the doped region 120 and the doped region 136 at the same time. In FIG. 4 , the number of contact windows 202 is illustrated by taking one as an example, but the present invention is not limited to this. In some embodiments, the number of contact windows 202 may also be multiple. The material of the contact window 202 is, for example, tungsten.

Barrier layer 204 is provided between contact window 202 and electrode 208b. The barrier layer 206, the barrier layer 210 and the barrier layer 212 are respectively disposed on the conductor layer 162, the conductor layer 166 and the conductor layer 170. The material of the barrier layer 206, the barrier layer 210 and the barrier layer 212 is, for example, titanium, titanium nitride or a combination thereof.

In the memory structure 200, the conductor layer 162, the barrier layer 164, the conductor layer 166, the barrier layer 168, the conductor layer 170 and the barrier layer 172 may be located on the dielectric layer 152 according to the selection of the manufacturing process. In addition, the materials of the conductor layer 162, the conductor layer 166, and the conductor layer 170 can be adjusted according to the manufacturing process, such as aluminum.

In addition, in the memory structure 200 and the memory structure 100, similar components are represented by the same symbols and their descriptions are omitted.

Based on the above embodiments, it can be seen that in the memory structure 200, the doped regions 118 and 120 are arranged in the first direction D1, the doped regions 120 and the doped regions 136 are arranged in the second direction D2, and the doped regions 118 and 120 are arranged in the second direction D2. Intersecting the first direction D1 , the capacitor 208 is coupled to the doping region 120 and the doping region 136 . Through the above arrangement, the size of the capacitor 208 can be effectively increased without increasing the chip area. Therefore, the capacitance of the capacitor 208 can be effectively increased, thereby improving the electrical performance of the memory component. In addition, since the capacitor 208 can extend into the plurality of openings 152b, the capacitance of the capacitor 208 can be further increased.

In summary, the memory structure of the above embodiments can effectively increase the size of the capacitor without increasing the chip area through the arrangement of the capacitors. Therefore, the capacitance of the capacitor can be effectively increased, thereby improving the performance of the memory component. Electrical performance.

Although the present invention has been disclosed in conjunction with the above embodiments, they are not intended to limit the present invention. Anyone with ordinary skill in the technical field can make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be defined by the appended claims.

Claims (12)

1. A memory structure, characterized in that it includes: A first transistor includes a first gate electrode and first doping regions and second doping regions located on both sides of the first gate electrode, wherein the first doping region and the second doping region are on arranged in the first direction; The second transistor includes a second gate electrode and third and fourth doped regions located on both sides of the second gate electrode, wherein the second doped region and the third doped region are located at The first gate and the second gate are arranged in a second direction, and the second direction intersects the first direction; and A capacitor coupled to the second doped region and the third doped region. 2. The memory structure of claim 1, wherein the first transistor and the second transistor are one and the other of a P-type metal oxide semiconductor transistor and an N-type metal oxide semiconductor transistor, respectively. 3. The memory structure of claim 1, wherein the capacitor extends in the second direction. 4. The memory structure of claim 1, wherein the third doped region and the fourth doped region are arranged in a third direction, and the third direction intersects the second direction. 5. The memory structure of claim 4, wherein the first direction is parallel to the third direction. 6. The memory structure of claim 4, wherein The extending direction of the gate of the first transistor intersects with the first direction and is not perpendicular to the second direction, and The extending direction of the gate of the second transistor intersects with the third direction and is not perpendicular to the second direction. 7. The memory structure of claim 1, wherein the first transistor and the second transistor coupled to the capacitor are arranged in a staggered manner. 8. The memory structure of claim 1, further comprising: A dielectric layer covers the first transistor and the second transistor and has at least one opening, wherein the capacitor is located in the at least one opening. 9. The memory structure of claim 8, further comprising: An isolation structure is located between the second doped region and the third doped region. 10. The memory structure of claim 9, wherein the number of the at least one opening is one, and the opening exposes the second doped region, the third doped region and the isolation structure. 11. The memory structure of claim 9, wherein the number of the at least one opening is multiple, and each of the openings exposes the second doped region, the third doped region and the At least one of the isolation structures. 12. The memory structure of claim 9, further comprising: A contact window is coupled to the capacitor and located above at least one of the isolation structure, the second doped region, and the third doped region.