CN111490047A - Memory structure - Google Patents

Abstract

The invention discloses a memory structure, which includes a first transistor, a second transistor and a capacitor. The first transistor includes a first gate electrode and first and second doped regions located on both sides of the first gate electrode. The first doped region and the second doped region are arranged in the first direction. The second transistor includes a second gate electrode and third and fourth doped regions located on both sides of the second gate electrode. The second doped region and the third doped region are located between the first gate electrode and the second gate electrode. The second doped region and the third doped region are arranged in the second direction. The second direction intersects the first direction. The capacitor is coupled to the second doped region and the third doped region.

Description

memory structure

technical field

The present invention relates to a semiconductor structure, and in particular to a memory structure.

Background technique

A memory structure has been developed that includes a transistor and a capacitor coupled to each other. In this type of memory structure, capacitors are used as storage components. Therefore, how to increase the capacitance of the capacitor to improve the electrical performance of the memory device is currently the goal of continuous efforts in the industry.

SUMMARY OF THE INVENTION

The present invention provides a memory structure, which can effectively increase the capacitance of the capacitor, thereby improving the electrical performance of the memory device.

The present invention provides a memory structure including a first transistor, a second transistor and a capacitor. The first transistor includes a first gate, and a first doped region and a second doped region on both sides of the first gate. The first doped region and the second doped region are arranged in the first direction. The second transistor includes a second gate and third and fourth doped regions on both sides of the second gate. The second doped region and the third doped region are located between the first gate and the second gate. The second doping region and the third doping region are arranged in the second direction. The second direction intersects the first direction. The capacitor is coupled to the second doped region and the third doped region.

According to an embodiment of the present invention, in the above-mentioned memory structure, the first transistor and the second transistor can be one and the other of a P-type metal oxide semiconductor transistor and an N-type metal oxide semiconductor transistor, respectively.

According to an embodiment of the present invention, in the above-mentioned memory structure, the capacitor may extend in the second direction.

According to an embodiment of the present invention, in the above-mentioned memory structure, the third doping region and the fourth doping region may be arranged in a third direction. The third direction may intersect the second direction.

According to an embodiment of the present invention, in the above-mentioned memory structure, the first direction may be parallel to the third direction.

According to an embodiment of the present invention, in the above-mentioned memory structure, the extending direction of the gate of the first transistor may intersect with the first direction and may not be perpendicular to the second direction. The extending direction of the gate of the second transistor may intersect the third direction and may not be perpendicular to the second direction.

According to an embodiment of the present invention, in the above-mentioned memory structure, the first transistor and the second transistor coupled to the capacitor may be arranged in a staggered arrangement.

According to an embodiment of the present invention, the above-mentioned memory structure may further include a dielectric layer. The dielectric layer covers the first transistor and the second transistor and has at least one opening. A capacitor may be located in the opening.

According to an embodiment of the present invention, the above-mentioned memory structure may further include an isolation structure. The isolation structure may be located between the second doped region and the third doped region.

According to an embodiment of the present invention, in the above-mentioned memory structure, the number of openings may be one. The opening exposes the second doped region, the third doped region and the isolation structure.

According to an embodiment of the present invention, in the above-mentioned memory structure, the number of openings may be multiple. Each opening may expose at least one of the second doped region, the third doped region, and the isolation structure.

According to an embodiment of the present invention, the above-mentioned memory structure may further include a contact window. The contact window is coupled to the capacitor. The contact window may be located over at least one of the isolation structure, the second doped region and the third doped region.

Based on the above, in the memory structure proposed by the present invention, the first doping region and the second doping region are arranged in the first direction, the second doping region and the third doping region are arranged in the second direction, and the second doping region and the third doping region are arranged in the second direction. The two directions intersect with the first direction, and the capacitor is coupled to the second doped region and the third doped region. Through the above arrangement, the size of the capacitor can be effectively increased without increasing the chip area, so the capacitance of the capacitor can be effectively increased, thereby improving the electrical performance of the memory device.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

Description of drawings

1 is a top view of a memory structure according to an embodiment of the present invention;

Fig. 2 is a cross-sectional view of the memory structure along the I-I' section line in Fig. 1;

3 is a top view of a memory structure according to another embodiment of the present invention;

FIG. 4 is a cross-sectional view of the memory structure along the line II-II' in FIG. 3 .

Symbol Description

100, 200: memory components

102: Base

104, 106: Transistors

108, 208: Capacitors

108a, 108b, 208a, 208b: Electrodes

108c, 208c: insulating layer

110, 112: Well area

114: Isolation Structure

116, 134: Gate

118, 120, 136, 138: doped regions

122, 140, 152: Dielectric layer

124, 142: Spacers

126, 128, 144, 146: Lightly doped drain

130, 132, 148, 150: metal silicide layer

152a, 152b: openings

154, 158, 202: Contact windows

156, 160, 164, 168, 172, 204, 206, 210, 212: Barrier layer

162, 166, 170: Conductor layer

D1: first direction

D2: second direction

D3: third direction

ED1, ED2: extension direction

Detailed ways

FIG. 1 is a top view of a memory structure according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of the memory structure along the section line I-I' in FIG. 1 . In FIG. 1 , some components in FIG. 2 are omitted to clearly illustrate the arrangement relationship between the transistors and the capacitors. In addition, the proportional relationship of the components in FIG. 1 and FIG. 2 is only for schematic illustration, and the present invention is not limited thereto. In this embodiment, the content of "direction" is shown in FIG. 1 .

Referring to FIGS. 1 and 2 , the memory structure 100 includes a substrate 102 , a transistor 104 , a transistor 106 and a capacitor 108 . The memory structure 10 is, for example, a two-transistor static random access memory (2T SRAM), but the invention is not limited thereto. The substrate 100 is, for example, a semiconductor substrate, such as a silicon substrate. Capacitor 108 may be coupled between transistor 104 and transistor 106 .

Hereinafter, the first conductivity type and the second conductivity type described may be one and the other of the P-type conductivity type and the N-type conductivity type, respectively. In this embodiment, the first conductivity type is a P-type conductivity type as an example, and the second conductivity type is an N-type conductivity type as an example, but the invention is not limited to this. In another embodiment, the first conductivity type may be an N-type conductivity type, and the second conductivity type may be a P-type conductivity type.

The memory structure 100 may also include at least one of a well region 110 , a well region 112 , and an isolation structure 114 . The well region 110 is located in the substrate 102 . The well region 110 may have a first conductivity type (eg, P-type). The well region 112 is located in the substrate 102 on one side of the well region 110 . The well region 112 may have a second conductivity type (eg, N-type).

The isolation structure 114 is disposed in the substrate 102 between the well region 110 and the well region 112 . The isolation structure 114 is, for example, a shallow trench isolation (shallow trench isolation, STI). The material of the isolation structure 114 is, for example, silicon oxide.

Transistor 104 and transistor 106 may be one and the other of a P-type metal-oxide-semiconductor transistor and an N-type metal-oxide-semiconductor transistor, respectively. In this embodiment, the transistor 104 may have a first conductivity type (P-type), and the transistor 106 may have a second conductivity type (N-type). That is, the transistor 104 is an example of a P-type metal-oxide-semiconductor transistor, and the transistor 106 is an example of an N-type metal-oxide-semiconductor transistor, but the invention is not limited thereto.

The transistor 104 includes a gate 116 and doped regions 118 and 120 on both sides of the gate 116 . The doped regions 118 and 120 are arranged in the first direction D1. The material of the gate 116 is, for example, doped polysilicon. In some embodiments, transistor 104 may also include a metal silicide layer (not shown) disposed on gate 116 . The doped region 118 and the doped region 120 may be located in the substrate 102 on both sides of the gate 116 . In addition, the doped regions 118 and 120 may be located in the well region 112 . The doped region 118 and the doped region 120 can be used as a source electrode or a drain electrode, respectively. The doped regions 118 and 120 may have a first conductivity type (eg, P-type).

In addition, the transistor 104 may further include at least one of a dielectric layer 122 , a spacer 124 , a lightly doped drain (LDD) 126 , a lightly doped drain 128 , a metal silicide layer 130 and a metal silicide layer 132 . By. The dielectric layer 122 is located between the gate electrode 116 and the substrate 102, whereby the gate electrode 116 and the substrate 102 can be insulated from each other. The material of the dielectric layer 122 is, for example, silicon oxide.

Spacers 124 are disposed on the sidewalls of gate 116 . The spacer 124 may be a single-layer structure or a multi-layer structure. The material of the spacer 124 is, for example, silicon oxide, silicon nitride, or a combination thereof.

A lightly doped drain 126 is located in the substrate 102 between the gate 116 and the doped region 118 . A lightly doped drain 128 is located in the substrate 102 between the gate 116 and the doped region 120 . In addition, the lightly doped drain 126 and the lightly doped drain 128 may be located in the well region 112 . The lightly doped drain 126 and the lightly doped drain 128 may have a first conductivity type (eg, P-type). In some embodiments, a "lightly doped drain (LDD)" may also be referred to as a "source/drain extension (SDE)").

A metal silicide layer 130 is disposed on the doped region 118 . A metal silicide layer 132 is disposed on the doped region 120 . The material of the metal silicide layer 130 and the metal silicide layer 132 is, for example, nickel silicide or cobalt silicide.

The transistor 106 includes a gate 134 and doped regions 136 and 138 on both sides of the gate 134 . Doped region 120 and doped region 136 are located between gate 116 and gate 134 . The isolation structure 114 may be located between the doped region 120 and the doped region 136 . The doped regions 120 and 136 are arranged in the second direction D2. The second direction D2 intersects the first direction D1. In addition, the doped regions 136 and 138 may be arranged in the third direction D3. The third direction D3 may intersect the second direction D2. The first direction D1 may be parallel to the third direction D3, but the present invention is not limited thereto. In addition, the extending direction ED1 of the gate 116 of the transistor 104 may intersect the first direction D1 and may not be perpendicular to the second direction D2. The extending direction ED2 of the gate 134 of the transistor 106 may intersect the third direction D3 and may not be perpendicular to the second direction D2.

The material of the gate 134 is, for example, doped polysilicon. In some embodiments, transistor 106 may further include a metal silicide layer (not shown) disposed on gate 134 . The doped regions 136 and 138 may be located in the substrate 102 on both sides of the gate 134 . In addition, the doped regions 136 and 138 may be located in the well region 110 . The doped region 136 and the doped region 138 can function as a source electrode or a drain electrode, respectively. The doped regions 136 and 138 may have a second conductivity type (eg, N-type).

In addition, the transistor 106 may further include at least one of a dielectric layer 140 , a spacer 142 , a lightly doped drain 144 , a lightly doped drain 146 , a metal silicide layer 148 and a metal silicide layer 150 . The dielectric layer 140 is located between the gate electrode 134 and the substrate 102, whereby the gate electrode 134 and the substrate 102 can be insulated from each other. The material of the dielectric layer 140 is, for example, silicon oxide.

Spacers 142 are disposed on the sidewalls of the gate electrode 134 . The spacer 142 may be a single-layer structure or a multi-layer structure. The material of the spacer 142 is, for example, silicon oxide, silicon nitride, or a combination thereof.

Lightly doped drain 144 is located in substrate 102 between gate 134 and doped region 136 . Lightly doped drain 146 is located in substrate 102 between gate 134 and doped region 138 . In addition, the lightly doped drain 144 and the lightly doped drain 146 may be located in the well region 110 . The lightly doped drain 144 and the lightly doped drain 146 may have a second conductivity type (eg, N-type).

A metal silicide layer 148 is disposed on the doped region 136 . A metal silicide layer 150 is disposed on the doped region 138 . The material of the metal silicide layer 148 and the metal silicide layer 150 is, for example, nickel silicide or cobalt silicide.

The memory structure 100 may also include a dielectric layer 152 . The dielectric layer 152 covers the transistors 104 and 106 and has at least one opening 152a. Capacitor 108 may be located in opening 152a. In this embodiment, the number of the opening 152a may be one, and the opening 152a may be a slot-shaped opening, but the invention is not limited thereto. The opening 152a may expose the doped region 120 , the doped region 136 and the isolation structure 114 , and may also expose the metal silicide layer 132 and the metal silicide layer 148 . The dielectric layer 152 may be a multi-layer structure. The material of the dielectric layer 152 is, for example, silicon oxide, silicon nitride, or a combination thereof.

Capacitor 108 is coupled to doped region 120 and doped region 136 . Therefore, the capacitor 108 may extend in the second direction D2, and the transistor 104 and the transistor 106 coupled to the capacitor 108 may be arranged in a dislocation arrangement. The capacitor 108 may include an electrode 108a, an electrode 108b, and an insulating layer 108c. The electrode 108a can be directly connected to the doped region 120, the doped region 136, and also directly connected to the metal silicide layer 132 and the metal silicide layer 148, but the invention is not limited thereto. The electrode 108a can be used as the lower electrode of the capacitor 108 . Electrode 108b is provided on electrode 108a. Electrode 108b may serve as the upper electrode of capacitor 108 . The material of the electrode 108a and the electrode 108b is, for example, Ti, TiN, Ta, TaN, Al, In, Nb, Hf, Sn, Zn, Zr, Cu, Y, W, Pt or a combination thereof. The insulating layer 108c is provided between the electrode 108a and the electrode 108b. The material of the insulating layer 108c is, for example, a high-k material, silicon oxide, silicon nitride, silicon oxide/silicon nitride/silicon oxide (oxide-nitride-oxide, ONO) or a combination thereof. The high dielectric constant material is, for example, tantalum oxide (Ta ₂ O ₅ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), zirconium oxide (ZrO ₂ ), or a combination thereof. In the capacitor 108, since the insulating layer 108c is provided between the electrode 108a and the electrode 108b, a metal-insulator-metal (MIM) capacitor can be formed.

The memory structure 100 may further include a contact window 154 in the dielectric layer 152, a barrier layer 156, a contact window 158, a barrier layer 160, a conductor layer 162, a barrier layer 164, a conductor layer 166, a barrier layer 168, a conductor At least one of layer 170 and barrier layer 172 . The contact window 154 is coupled to the doped region 118 . The barrier layer 156 may be disposed between the contact window 154 and the metal silicide layer 130 . The contact window 158 is coupled to the doped region 138 . The barrier layer 160 may be disposed between the contact window 158 and the metal silicide layer 150 . The material of the contact window 154 and the contact window 158 is, for example, tungsten. The material of the barrier layer 156 and the barrier layer 160 is, for example, titanium, titanium nitride or a combination thereof.

The conductor layer 162 is coupled to the contact window 154 . The barrier layer 164 is disposed between the conductor layer 162 and the contact window 154 . The conductor layer 166 is coupled to the contact window 158 . The barrier layer 168 is disposed between the conductor layer 166 and the contact window 158 . The conductor layer 170 is coupled to the electrode 108b. The barrier layer 172 is provided between the conductor layer 170 and the electrode 108b. The materials of the conductor layer 162 , the conductor layer 166 and the conductor layer 170 are, for example, aluminum (Al), copper (Cu) or a combination thereof. The material of the barrier layer 164 , the barrier layer 168 and the barrier layer 172 is, for example, titanium, titanium nitride or a combination thereof.

Based on the above embodiments, in the memory structure 100, the doped regions 118 and 120 are arranged in the first direction D1, the doped regions 120 and 136 are arranged in the second direction D2, and the second direction D2 It intersects the first direction D1 and the capacitor 108 is coupled to the doped region 120 and the doped region 136 . Through the above arrangement, the size of the capacitor 108 can be effectively increased without increasing the chip area, so the capacitance of the capacitor 108 can be effectively increased, thereby improving the electrical performance of the memory device.

FIG. 3 is a top view of a memory structure according to another embodiment of the present invention. FIG. 4 is a cross-sectional view of the memory structure along the line II-II' in FIG. 3 . In FIG. 3 , some components in FIG. 4 are omitted to clearly illustrate the arrangement relationship between the transistors and the capacitors. In addition, the proportional relationship of the components in FIG. 3 and FIG. 4 is only for schematic illustration, and the present invention is not limited thereto. In this embodiment, the content of "direction" is shown in FIG. 3 .

Please refer to FIGS. 1 to 4 at the same time. The differences between the memory structures 200 of FIGS. 3 and 4 are as follows. In the memory structure 200, the number of the openings 152b in the dielectric layer 152 may be plural, and the openings 152b may be via holes. Each opening 152b may expose at least one of the doped region 120 , the doped region 136 and the isolation structure 114 . For example, the opening 152b may only expose the doped region 120, the opening 152b may only expose the doped region 136, the opening 152b may expose both the doped region 120 and the isolation structure 114, or the opening 152b may simultaneously expose the doped region 136 and isolation structure 114. In addition, although not shown in FIG. 3 and FIG. 4 , in other embodiments, the opening 152b may expose the doped region 120 , the doped region 136 and the isolation structure 114 at the same time. The electrode 208a, the electrode 208b and the insulating layer 208c in the capacitor 208 can respectively extend into the plurality of openings 152b, thereby further increasing the capacitance of the capacitor 208. Regarding the configuration, materials and functions of the components in the capacitor 208, reference may be made to the content of the capacitor 108, which will not be described here.

In addition, the memory structure 200 may further include at least one of the contact window 202 , the barrier layer 204 , the barrier layer 206 , the barrier layer 210 , and the barrier layer 212 . Contact window 202 is coupled to capacitor 208 . Therefore, the conductor layer 170 may be coupled to the capacitor 208 through the barrier layer 172 , the contact window 202 and the barrier layer 204 . Additionally, the contact window 202 may be located over at least one of the isolation structure 114 , the doped region 120 and the doped region 136 . In this embodiment, the contact window 202 is located above the isolation structure 114 as an example, but the invention is not limited to this. In other embodiments, the contact window 202 may be located only over the doped region 120 , the contact window 202 may be located only over the doped region 136 , the contact window 202 may be located over both the isolation structure 114 and the doped region 120 , and the contact window 202 may Over the isolation structure 114 and the doped region 136 at the same time, or the contact window 202 may be over the isolation structure 114 , the doped region 120 and the doped region 136 at the same time. In FIG. 4 , the number of the contact windows 202 is illustrated as one, but the present invention is not limited to this. In some embodiments, the number of the contact windows 202 may also be multiple. The material of the contact window 202 is, for example, tungsten.

The barrier layer 204 is disposed between the contact window 202 and the electrode 208b. The barrier layer 206 , the barrier layer 210 and the barrier layer 212 are respectively disposed on the conductor layer 162 , the conductor layer 166 and the conductor layer 170 . The materials of the barrier layer 206 , the barrier layer 210 and the barrier layer 212 are, for example, titanium, titanium nitride or a combination thereof.

In the memory structure 200 , the conductor layer 162 , the barrier layer 164 , the conductor layer 166 , the barrier layer 168 , the conductor layer 170 and the barrier layer 172 may be located on the dielectric layer 152 according to the selection of the manufacturing process. In addition, the materials of the conductor layer 162, the conductor layer 166, and the conductor layer 170 can be adjusted according to the manufacturing process, for example, aluminum.

In addition, in the memory structure 200 and the memory structure 100, similar components are denoted by the same symbols and the description thereof is omitted.

Based on the above embodiments, in the memory structure 200, the doped regions 118 and 120 are arranged in the first direction D1, the doped regions 120 and 136 are arranged in the second direction D2, and the second direction D2 It intersects the first direction D1 and the capacitor 208 is coupled to the doped region 120 and the doped region 136 . Through the above arrangement, the size of the capacitor 208 can be effectively increased without increasing the chip area, so the capacitance of the capacitor 208 can be effectively increased, thereby improving the electrical performance of the memory device. In addition, since the capacitor 208 can extend into the plurality of openings 152b, the capacitance of the capacitor 208 can be further increased.

To sum up, the memory structure of the above-mentioned embodiment can effectively increase the size of the capacitor without increasing the chip area through the above-mentioned arrangement of the capacitor, so the capacitance of the capacitor can be effectively increased, and the performance of the memory component can be improved. Electrical performance.

Although the present invention is disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The scope of protection of the present invention should be defined by the appended claims.

Claims (12)

1. A memory structure, comprising:

the transistor comprises a first transistor and a second transistor, wherein the first transistor comprises a first grid electrode, a first doped region and a second doped region, the first doped region and the second doped region are positioned on two sides of the first grid electrode, and the first doped region and the second doped region are arranged in a first direction;

a second transistor including a second gate and third and fourth doped regions located at both sides of the second gate, wherein the second and third doped regions are located between the first and second gates and arranged in a second direction, and the second direction intersects the first direction; and

a capacitor coupled to the second doped region and the third doped region.

2. The memory structure of claim 1, wherein the first transistor and the second transistor are one and the other of a pmos transistor and an nmos transistor, respectively.

3. The memory structure of claim 1, wherein said capacitor extends in said second direction.

4. The memory structure of claim 1, wherein the third doped region and the fourth doped region are aligned in a third direction, and the third direction intersects the second direction.

5. The memory structure of claim 4, wherein the first direction is parallel to the third direction.

6. The memory structure of claim 4, wherein

The extension direction of the gate of the first transistor intersects with the first direction and is not perpendicular to the second direction, and

an extending direction of a gate of the second transistor intersects the third direction and is not perpendicular to the second direction.

7. The memory structure of claim 1, wherein the first transistor and the second transistor coupled to the capacitor are in a staggered arrangement.

8. The memory structure of claim 1, further comprising:

a dielectric layer covering the first transistor and the second transistor and having at least one opening, wherein the capacitor is located in the at least one opening.

9. The memory structure of claim 8, further comprising:

and the isolation structure is positioned between the second doped region and the third doped region.

10. The memory structure of claim 9, wherein the at least one opening is one in number and exposes the second doped region, the third doped region and the isolation structure.

11. The memory structure of claim 9, wherein the at least one opening is plural in number, and each of the openings exposes at least one of the second doped region, the third doped region and the isolation structure.

12. The memory structure of claim 1, further comprising:

a contact window coupled to the capacitor and located over at least one of the isolation structure, the second doped region, and the third doped region.

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