CN111489773B

CN111489773B - Circuit for reading data, nonvolatile memory and method for reading data

Info

Publication number: CN111489773B
Application number: CN201910087625.9A
Authority: CN
Inventors: 黄鹏; 邓龙利
Original assignee: Zhaoyi Innovation Technology Group Co ltd; Hefei Geyi Integrated Circuit Co Ltd
Current assignee: Zhaoyi Innovation Technology Group Co ltd; Hefei Geyi Integrated Circuit Co Ltd
Priority date: 2019-01-29
Filing date: 2019-01-29
Publication date: 2023-04-07
Anticipated expiration: 2039-01-29
Also published as: CN111489773A

Abstract

The invention provides a circuit for reading data, a nonvolatile memory and a method for reading the circuit. The circuit is applied to a nonvolatile memory, the nonvolatile memory comprises a storage unit, and the circuit comprises: the data output module is connected with the data output module, the sense amplifiers are respectively connected with the logic circuit and the latches, the latches are respectively connected with the sense amplifiers and the latch management module, the latch management module is respectively connected with the latches and the data output module, and the data output module is connected with the latch management module.

Description

Circuit for reading data, nonvolatile memory and method for reading data

Technical Field

The present invention relates to the field of nonvolatile memories, and more particularly, to a circuit for reading data, a nonvolatile memory, and a method for reading data.

Background

With the development of various electronic devices, embedded systems, and the like, nonvolatile memory devices are widely used in electronic products. Taking a non-volatile Memory NAND Flash Memory (NAND Flash Memory) as an example, the NAND Memory is composed of a plurality of Memory cells (cells), can realize multiple times of programming, and has large capacity, simple reading and writing, few peripheral devices and low price.

The principle diagram of the Nand flash is shown in fig. 1, the Nand flash mainly has three types of operations, i.e., read, program, and erase, and for a read operation, an appropriate voltage is applied to a word line (wl for short in fig. 1), data on a selected memory cell is read out and output through a data transmission module, where wl0 to wlm represent m wl, bit lines (bl for short in fig. 1) 0 to bit lines (bl) n represent n bls, each bls corresponds to a sense amplifier (sa in fig. 1) and a latch (latch in fig. 1), when the nonvolatile memory performs the read operation, sa first reads all data in the memory cell through the bl, transmits the data to the latch, and then transmits the read data to a data output module (datapath), and finally, the data is read in a Q15 data output mode in each datapath (Q1).

In the process of the above operation, when sa receives a high-level enable signal, sa reads data of a memory cell through bl, transmits the data to latch, and transmits the data to datapath through latch, and then outputs the received read data when datapath receives the high-level enable signal, and sa does not work until the datapath outputs all data, and sa receives the high-level enable signal and continues to perform the next set of data reading work until the datapath finishes outputting the data, which wastes a lot of time and reduces the working efficiency of the nonvolatile memory.

Disclosure of Invention

The circuit for reading data and the method for reading data solve the problem that the occupied physical layout area is too large due to the huge amount of sa and latch, and simultaneously solve the problem that sa cannot work simultaneously during datapath data output.

In order to solve the above technical problem, an embodiment of the present invention provides a circuit for reading data, where the circuit is applied to a nonvolatile memory, where the nonvolatile memory includes a memory cell, and the circuit includes: the number of the sensitive amplifiers and the number of the latches are respectively integral and even times of the number of data output by the data output module;

the logic circuit is respectively connected with the bit lines of the storage unit and the sense amplifiers and is used for selecting a plurality of bit lines according to the number of the sense amplifiers, and the number of the bit lines is equal to that of the sense amplifiers;

the sense amplifier is respectively connected with the logic circuit and the latch and used for reading data on the bit lines according to a first working time sequence signal, wherein the first working time sequence signal is a working signal for reading data by the sense amplifier;

the latch is respectively connected with the sensitive amplifier and the latch management module and is used for latching the data read by the sensitive amplifier and transmitting the latched data to the latch management module;

the latch management module is respectively connected with the latch and the data output module and is used for transmitting the received data to the data output module according to a second working time sequence signal, and the second working time sequence signal is a working signal for the latch management module to carry out data transmission operation;

and the data output module is connected with the latch management module and used for outputting the received data.

Optionally, the non-volatile memory further comprises: a control module;

the control module is respectively connected with the sense amplifier and the latch management module and is used for sending the first working time sequence signal to the sense amplifier and sending the second working time sequence signal to the latch management module.

Optionally, when the first operation timing signal is at a high level, the sense amplifier reads data from the plurality of bit lines and transmits the read data to the latch management module through the latch;

when the second working timing signal is at a high level, the latch management module transmits the received data to the data output module, so that the data output module outputs the received data.

Optionally, the number of data output by the data output module is 16, and the number of the sense amplifiers and the number of the latches are respectively an even integer multiple of 16.

Optionally, during the period when the second operation timing signal is at a high level, if the first operation timing signal is at a high level, the sense amplifier continues to read a next set of data from the plurality of bit lines.

An embodiment of the present invention further provides a nonvolatile memory, where the nonvolatile memory includes: the control module is connected with the circuit for reading data.

The embodiment of the present invention further provides a method for reading data, where the method is applied to any of the above circuits for reading data, and the method includes:

the sensitive amplifier receives a first working time sequence signal sent by the control module;

if the first working time sequence signal is in a high level, the sensitive amplifier sends a data reading request to the logic circuit;

when the first working time sequence signal is at a high level, the logic circuit selects a plurality of bit lines according to the number of the sense amplifiers according to the read data request, the number of the bit lines is equal to the number of the sense amplifiers, and the bit line numbers of the bit lines are sent to the sense amplifiers;

the sense amplifier receives the bit line signal during the first operation timing signal is at a high level;

when the first working time sequence signal is in a high level, the sensitive amplifier reads data on a bit line corresponding to a bit line number according to the bit line number and transmits the read data to the latch;

during the period that the first working timing signal is at a high level, the latch latches the data read by the sensitive amplifier and transmits the latched data to the latch management module;

the latch management module receives a second working timing sequence signal sent by the control module;

if the second working timing sequence signal is at a high level, the latch management module transmits the received data to the data output module;

and the data output module outputs the received data when the second working timing sequence signal is in a high level.

Optionally, after the sense amplifier receives the first operation timing signal sent by the control module, the method further includes:

and if the first working time sequence signal is at a low level, the sensitive amplifier does not send the read data request to the logic circuit.

Optionally, after the latch management module receives the second operation timing signal sent by the control module, the method further includes:

and if the second working timing sequence signal is at a low level, the latch management module does not transmit the received data to the data output module.

Optionally, during a period when the second operation timing signal is at a high level, the data output module outputs the received data, including:

during the period that the second working timing signal is at a high level, if the first working timing signal is at a high level, the sense amplifier continues to send a new read data request to the logic circuit during the period that the first working timing signal is at a high level, the read of new data is completed, the newly read data is transmitted to the latch, and the latch transmits the newly received data to the latch management module.

Compared with the prior art, the invention provides a circuit for reading data and a method for reading data, wherein the number of the sensitive amplifiers and the latches on the circuit is reduced, the number of the latches is set according to the integral even multiple of the number of the data output by the data output module, the latch management module and the logic circuit are added, bl is selected by the logic circuit according to the number of the sensitive amplifiers during reading according to the working time sequence signal, then the data is read by the sensitive amplifiers and transmitted to the latch management module, the read data is managed by the latch management module, and when the data is required to be output, the data is transmitted to the data output module according to another working time sequence signal to be output, so that the data output is realized, and the mutual interference work is avoided. The circuit for reading data and the method for reading data improve the working efficiency of the nonvolatile memory and greatly reduce the physical layout occupied by sa and latch.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.

FIG. 1 is a schematic diagram of a conventional circuit for reading data from a nonvolatile memory;

FIG. 2 is a schematic diagram of a read data circuit according to an embodiment of the present invention;

FIG. 3 is a timing diagram of t1 and t2 operations in the embodiment of the present invention;

FIG. 4 is a schematic diagram of a non-volatile memory in an embodiment of the invention;

FIG. 5 is a flowchart of a method of reading a circuit according to an embodiment of the invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 2, a schematic diagram of a circuit for reading data is shown, where the circuit is applied to a nonvolatile memory, where the nonvolatile memory includes a memory cell 10, and the circuit for reading data may specifically include:

logic circuit 20 (logic in the figure), sense amplifiers 30 (SA 0 to SAx in the figure), latches 40 (Latch 0 to Latch in the figure), latch management block 50 (Latch _ path), and data output block 60 (datapath), where the number of sense amplifiers 30 and the number of latches 40 are respectively an integral and even multiple of the number of data output by data output block 60, for example, if the data output block 60 outputs data in a mode of outputting data by 16 data units in the embodiment of the present invention, the number of sense amplifiers 30 and the number of latches 40 may be respectively set to 16, 32, 64, or 128, and the like, and may be set according to user requirements.

The logic circuit 20 is connected to bl of the memory cell and the sense amplifiers 30, respectively, and is configured to select a plurality of bl, for example, 32 sense amplifiers 30, according to the number of the sense amplifiers 30, so that the logic circuit 20 selects 32 bl at a time to allow the sense amplifiers 30 to read data, the sense amplifiers 30 are connected to the logic circuit 20 and the latch 40, respectively, and are configured to read data on the plurality of bl selected by the logic circuit 20 according to a first operation timing signal (t 1 in the drawing), the latch 40 is connected to the sense amplifiers 30 and the latch management module 50, respectively, and is configured to latch data read by the sense amplifiers 30 and transmit the read data to the latch management module 50, and the latch management module 50 is connected to the latch 40 and the data output module 60, respectively, and is configured to transmit the received read data to the data output module 60 and receive the newly read data according to a second operation timing signal (t 2 in the drawing), and the data output module 60 is connected to the latch management module 50 and is configured to output the received data.

Optionally, referring to fig. 2, the nonvolatile memory further includes: and a control module 70, where the control module 70 is connected to the sense amplifier 30 and the latch management module 50, and is configured to send a first operation timing signal t1 to the sense amplifier 30 and a second operation timing signal t2 to the latch management module 50, when t1 is at a high level, the sense amplifier 30 reads data from bl of the storage unit and transmits the read data to the latch management module 50 through the latch 40, when t2 is at a high level, the latch management module 50 transmits the read data to the data output module 60 and outputs the read data through the data output module 60, and during a time period when t2 is at a high level, if t1 is also at a high level, the sense amplifier 30 continues to read a next set of data from bl of the storage unit.

For example, referring to the operation timing diagrams of t1 and t2 shown in fig. 3, when a read operation is performed, SA receives a signal of t1, SA transmits a request signal for reading data to logic in a time period of t1 high level, logic selects 32 bls to the sense amplifiers SA0 to SA31 according to the number of SA, SA0 to SA31 read out data in corresponding memory cells by bl and transfer the data to Latch0 to Latch31, latch0 to Latch31 then transfer the read data to Latch _ path, latch _ path receives a signal of t2, latch _ path transfers the read data to the datapath in a time period of t2 high level, and datapath has a Q <15: and (2) outputting the read data by 16 data patterns of 0> and simultaneously outputting the read data in a t2 high level time period, if SA 0-SA 31 receives the high level of t1 again, in the t1 high level time period, SA 0-SA 31 can read data of the next group of 32 bls, and the work of SA 0-SA 31 and the work of Latch _ path are respectively carried out and do not influence each other no matter t1 and t2 are simultaneously high level or the high levels of t1 and t2 are different, because SA and Latch respectively have 32 and are added together for 64, the working efficiency of the nonvolatile memory is improved, and the physical layout area occupied by SA and Latch is greatly reduced.

Optionally, referring to fig. 4, a schematic diagram of a nonvolatile memory in the embodiment of the present invention is shown, where the nonvolatile memory includes: the control module is connected with the circuit for reading data.

According to the above circuit for reading data, referring to fig. 5, an embodiment of the present invention further provides a method for reading a circuit, where the method specifically includes the following steps:

step 101: the sensitive amplifier receives a first working time sequence signal sent by the control module.

In the embodiment of the present invention, the SA0 to SA31 receive the first working timing signal t1 sent by the control module, where the signal is a timing signal with a periodically high and low level change. The embodiment of the present invention is not limited in detail, and may be set according to actual situations.

Step 102a: if the first working time sequence signal is in high level, the sensitive amplifier sends a read data request to the logic circuit.

In the embodiment of the present invention, if t1 received by SA0 to SA31 is a high level signal, a request for reading data is sent to logic, and the high level state lasts for a preset time. The embodiment of the present invention is not limited in detail, and may be set according to actual situations.

Step 102b: if the first operation timing signal is at a low level, the sense amplifier does not send a read data request to the logic circuit.

In the embodiment of the present invention, if t1 received by SA0 to SA31 is a low level signal, no request for reading data is sent to logic, and no other operation is performed, and similarly, the low level state also lasts for a preset time. The embodiment of the present invention is not limited in detail, and may be set according to actual situations.

Step 103: during the period when the first working time sequence signal is in a high level, the logic circuit selects a plurality of bit lines according to the number of the sensitive amplifiers according to the reading data request, the number of the bit lines is equal to the number of the sensitive amplifiers, and the bit line numbers of the bit lines are sent to the sensitive amplifiers.

In the embodiment of the present invention, in a sustained period of a high level t1, logic selects 32 bl according to a received read data request, it should be noted that the selected 32 bl is not necessarily bl with bit numbers 0 to 32, and may be bl with bit numbers 2 to 34, and only needs to satisfy that 32 bl, and is not in sequence, if 0 to 32 are selected in this time, then 0 to 32 will not be selected in the next selection, but the rest bl is selected until data reading is completed. logic sends the bit number of bl to SA 0-SA 31 after bl is selected. The embodiment of the present invention is not limited in detail, and may be set according to actual situations.

Step 104: the sense amplifier receives a bit line number during a period when the first operation timing signal is at a high level.

In the embodiment of the present invention, during the duration of the high level t1, the SA0 to SA31 receive the bit number of bl sent by logic, so that the SA0 to SA31 can know which bl data are read. The embodiment of the present invention is not limited in detail, and may be set according to actual situations.

Step 105: during the period that the first working timing signal is in high level, the sensitive amplifier reads the data on the bit line corresponding to the bit line number according to the bit line number and transmits the read data to the latch.

In the embodiment of the present invention, in the sustained period of the high level t1, SA0 to SA31 perform a read operation according to the bit number of bl, read out the data in the memory cell on the bit line corresponding to the bit number of bl, and transfer the read out data to the latches latch0 to latch31, it should be noted that, when performing a data read operation once, there may be a memory cell on bl that does not need to be read out according to the address of the data to be read out, and according to the specification of the nonvolatile memory, the sense amplifier still needs to perform a read operation on all bls, but there are some bls where no data needs to be read out. The embodiment of the present invention is not limited in detail, and may be set according to actual situations.

Step 106: during the period when the first operation timing signal is at high level, the latch latches the data read by the sense amplifier and transmits the latched data to the latch management module.

In the embodiment of the present invention, in the sustained period of the high level t1, the Latch0 to the Latch31 Latch the received data read from the SA0 to the SA31, so as to ensure that the data is not lost and play a role of temporary storage, and then the data read from the SA0 to the SA31 is transmitted to the Latch _ path. The embodiment of the present invention is not limited in detail, and may be set according to actual situations.

Step 107: and the latch management module receives a second working timing signal sent by the control module.

In the embodiment of the present invention, the Latch _ path50 receives the data read by the SA0 to SA31, but does not immediately operate the data but operates according to the enable signal of the control module, and the Latch _ path receives the second operation timing signal t2 sent by the control module. The embodiment of the present invention is not limited in detail, and may be set according to actual situations.

Step 108a: and if the second working timing sequence signal is at a high level, the latch management module transmits the received data to the data output module.

In the embodiment of the present invention, if t2 is at the high level, the Latch _ path transmits the received data to the datapath during the high level duration period. The embodiment of the present invention is not limited in detail, and may be set according to actual situations.

Step 108b: if the second working timing signal is in a low level, the latch management module does not transmit the received data to the data output module.

In the embodiment of the present invention, if t2 is low, latch _ path does not transmit the received data to datapath. The embodiment of the present invention is not limited in detail, and may be set according to actual situations.

Step 109: and the data output module outputs the received data when the second working timing signal is in a high level.

In the embodiment of the present invention, in the period that t2 continues to be at the high level, the datapath outputs the received data, it should be noted that the datapath still outputs data according to the mode of outputting 16 data at a time, and the number of the read data is 32, so that the datapath needs to output data twice continuously to complete the data output. The embodiment of the present invention is not limited in detail, and may be set according to actual situations.

Optionally, during the period when the second operation timing signal is at a high level, if the first operation timing signal is at a high level, during the period when the first operation timing signal is at a high level, the sense amplifier continues to send a new read data request to the logic circuit, finishes reading new data and transmits the newly read data to the latch, and the latch transmits the newly received data to the latch management module.

In the period that t2 continues to be at the high level, if t1 is also in the period that t1 continues to be at the high level, SA 0-SA 31 continue to send a new data reading request to logic, the request makes logic perform bl selection again, the above process is repeated, new data is read and transmitted to Latch _ path, latch _ path waits for t2 to be at the high level again, and then the new data is transmitted to datapath, so that the working process similar to a pipeline can be realized repeatedly, and the working efficiency of reading data is greatly improved.

For example, assuming that a data read operation is performed once and both t1 and t2 are at a high level, SA0 to SA31 send a request to read data to logic and Latch _ path transfers data to datapath, but since there is no data in Latch _ path, data is not transferred to datapath, logic selects bl with bit line numbers 0 to 32 and sends 0 to 32 to SA0 to SA31, SA0 to SA31 read data in memory cells on bl corresponding to 0 to 32 according to bit line numbers 0 to 32, and assuming that there is data, 32 data are read, SA0 to SA31 send the read data to corresponding Latch0 to Latch31, respectively, and Latch0 to Latch31 lock and hold the data to ensure that data is not lost or missing, and then transfer the data to Latch _ path, at which time t1 becomes low level, and at which time t1 becomes low level, SA0 to Latch31, and SA0 to Latch31 stop operating at SA0 to Latch 31.

The Latch _ path receives the data, and assuming that the level of t2 is low, the Latch _ path does not perform any operation, but temporarily latches the received data, assuming that the level of t2 is still high, the Latch _ path transmits the data read out from SA0 to SA31 to the datapath in a period of t2 lasting high, and after the datapath receives the data, the Latch _ path outputs the 32 data read out from SA0 to SA31 twice in a mode of outputting 16 data at a time, thereby completing the whole data output process.

Assuming that in the period of t2 high level, t1 changes from low level to high level again, SA 0-SA 31, logic and Latch 0-Latch 31 start repeating the above data reading steps, at this moment, SA 0-SA 31, logic and Latch 0-Latch 31 read out the data and finally transmit it to Latch _ path, and the data path is working, outputting 32 data read out last time, the reading and outputting processes are not affected mutually, the above processes are repeated, and a pipeline-like working process is generated, so as to improve the efficiency of reading data from the nonvolatile memory, optimally, t2 is in the period of sustained high level, the data path outputs the data read out last time, t2 is in the period of sustained low level, SA 0-SA 31, logic and Latch 0-Latch 31 complete the next data reading operation and transmit it to Latch _ path, which has the highest efficiency.

Through the embodiment, the number of the sensitive amplifiers and the number of the latches are set to be an integral and even number times of the number of the output data of the output module, so that the occupied physical layout area is greatly reduced, two newly added circuits, namely logic and Latch _ path, are utilized, respective work is carried out between high and low levels of the t1 and t2 time sequences, mutual influence is avoided, and the working efficiency of reading operation is improved.

Finally, it should also be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, herein, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.

While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A circuit for reading data, the circuit being applied to a non-volatile memory, the non-volatile memory including memory cells, the circuit comprising: the number of the sensitive amplifiers and the number of the latches are respectively integral and even times of the number of data output by the data output module, and the number of the sensitive amplifiers is equal to the number of the latches;

the logic circuit is respectively connected with the bit lines of the memory unit and the sense amplifiers and is used for selecting a plurality of bit lines according to the number of the sense amplifiers, and the number of the bit lines is equal to that of the sense amplifiers;

the sense amplifier is respectively connected with the logic circuit and the latch and used for reading data on the bit lines according to a first working timing signal, wherein the first working timing signal is a working signal for reading data operation of the sense amplifier;

the data output module is connected with the latch management module and used for outputting the received data;

the sense amplifier and the latch management module work independently according to the first working time sequence signal and the second working time sequence signal respectively.

2. The circuit of claim 1, wherein the non-volatile memory further comprises: a control module;

3. The circuit of claim 2, wherein when the first operation timing signal is high, the sense amplifier reads data from the plurality of bit lines and transmits the read data to the latch management module through the latch;

4. The circuit of claim 1, wherein the number of data output by the data output module is 16, and the number of the sense amplifiers and the number of the latches are respectively an even integer multiple of 16.

5. The circuit of claim 3, wherein during the period when the second operation timing signal is high, if the first operation timing signal is high, the sense amplifier continues to read a next group of data from the plurality of bit lines.

6. A non-volatile memory, the non-volatile memory comprising: a control module and the circuit for reading data according to any one of claims 1 to 5, said control module being connected to said circuit for reading data.

7. A method for reading data, the method being applied to a circuit for reading data according to any one of claims 1 to 5, the method comprising:

the sense amplifier receives the bit line signal during a period when the first operation timing signal is at a high level;

and the data output module outputs the received data when the second working timing sequence signal is at a high level.

8. The method of claim 7, wherein after the sense amplifier receives the first operation timing signal sent by the control module, the method further comprises:

9. The method of claim 7, wherein after the latch management module receives the second operation timing signal sent by the control module, the method further comprises:

10. The method of claim 7, wherein the data output module outputs the received data during the period when the second operation timing signal is at a high level, comprising: