CN111489773A - Circuit for reading data, nonvolatile memory and method for reading data - Google Patents
Circuit for reading data, nonvolatile memory and method for reading data Download PDFInfo
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Abstract
The invention provides a circuit for reading data, a nonvolatile memory and a method for reading the circuit. The circuit is applied to a nonvolatile memory, the nonvolatile memory comprises a storage unit, and the circuit comprises: the data output module is connected with the data output module, the sense amplifiers are respectively connected with the logic circuit and the latches, the latches are respectively connected with the sense amplifiers and the latch management module, the latch management module is respectively connected with the latches and the data output module, and the data output module is connected with the latch management module.
Description
Technical Field
The present invention relates to the field of nonvolatile memories, and more particularly, to a circuit for reading data, a nonvolatile memory, and a method for reading data.
Background
With the development of various electronic devices, embedded systems, and the like, nonvolatile memory devices are widely used in electronic products. Taking a non-volatile Memory NAND Flash Memory (NAND Flash Memory) as an example, the NAND Memory is composed of a plurality of Memory cells (cells), can realize multiple times of programming, and has large capacity, simple reading and writing, few peripheral devices and low price.
The principle diagram of the Nand flash is shown in fig. 1, and the basic operations of the Nand flash mainly include reading (read), programming (program), erasing (erase), for a read operation, a proper voltage is applied to a word line (wl in fig. 1), data on a selected memory cell is read out and output through a data transmission module, where wl0 through wlm represent m wl, bit line (bl in FIG. 1) 0 through bit line (bl in FIG. 1) n represent n bl, each bl corresponding to a sense amplifier (sa in FIG. 1) and a latch (latch in FIG. 1), when the nonvolatile memory carries out read operation, sa reads all data in the memory cell through bl, transmits the data to latch, transmits the read data to a data output module (datapath), and finally outputs the read data in a mode of 16 data at a time (Q < 15: 0> in FIG. 1).
In the process of the above operation, when sa receives a high level enable signal, sa reads out data of the memory cell through bl, transmits the data to latch, and transmits the data to datapath through latch, and then outputs the received read data when datapath receives a high level enable signal, and sa is always inactive in a time period of data output by datapath, and sa cannot operate even if sa receives a high level enable signal, and sa receives a high level enable signal until the datapath outputs all data, and then continues to perform the next set of data read operation, which wastes a lot of time and reduces the operating efficiency of the nonvolatile memory, on the other hand, because bl is many, there are tens of thousands of bls in a general nonvolatile memory, there are many latches corresponding to sa and sa, and thus it occupies a large physical layout area in the nonvolatile memory, this is a problem that needs to be solved urgently today where miniaturization of nonvolatile memories is required.
Disclosure of Invention
The circuit for reading data and the method for reading data solve the problem that the occupied physical layout area is overlarge due to the fact that the numbers of sa and latch are large, and simultaneously solve the problem that sa cannot work simultaneously during datapath data output.
In order to solve the above technical problem, an embodiment of the present invention provides a circuit for reading data, where the circuit is applied to a nonvolatile memory, where the nonvolatile memory includes a memory cell, and the circuit includes: the number of the sensitive amplifiers and the number of the latches are respectively integral and even times of the number of data output by the data output module;
the logic circuit is respectively connected with the bit lines of the memory unit and the sense amplifiers and is used for selecting a plurality of bit lines according to the number of the sense amplifiers, and the number of the bit lines is equal to that of the sense amplifiers;
the sense amplifier is respectively connected with the logic circuit and the latch and used for reading data on the bit lines according to a first working timing signal, wherein the first working timing signal is a working signal for reading data operation of the sense amplifier;
the latch is respectively connected with the sensitive amplifier and the latch management module and is used for latching the data read by the sensitive amplifier and transmitting the latched data to the latch management module;
the latch management module is respectively connected with the latch and the data output module and is used for transmitting the received data to the data output module according to a second working time sequence signal, and the second working time sequence signal is a working signal for the latch management module to carry out data transmission operation;
and the data output module is connected with the latch management module and used for outputting the received data.
Optionally, the non-volatile memory further comprises: a control module;
the control module is respectively connected with the sense amplifier and the latch management module and is used for sending the first working time sequence signal to the sense amplifier and sending the second working time sequence signal to the latch management module.
Optionally, when the first operation timing signal is at a high level, the sense amplifier reads data from the plurality of bit lines and transmits the read data to the latch management module through the latch;
when the second working timing signal is at a high level, the latch management module transmits the received data to the data output module, so that the data output module outputs the received data.
Optionally, the number of data output by the data output module is 16, and the number of the sense amplifiers and the number of the latches are respectively an even integer multiple of 16.
Optionally, during the period when the second operation timing signal is at a high level, if the first operation timing signal is at a high level, the sense amplifier continues to read a next set of data from the plurality of bit lines.
An embodiment of the present invention further provides a nonvolatile memory, where the nonvolatile memory includes: the control module is connected with the circuit for reading data.
An embodiment of the present invention further provides a method for reading data, where the method is applied to any one of the above circuits for reading data, and the method includes:
the sensitive amplifier receives a first working time sequence signal sent by the control module;
if the first working time sequence signal is at a high level, the sensitive amplifier sends a data reading request to the logic circuit;
when the first working time sequence signal is at a high level, the logic circuit selects a plurality of bit lines according to the number of the sense amplifiers according to the read data request, the number of the bit lines is equal to the number of the sense amplifiers, and the bit line numbers of the bit lines are sent to the sense amplifiers;
the sense amplifier receives the bit line signal during a period when the first operation timing signal is at a high level;
when the first working time sequence signal is in a high level, the sensitive amplifier reads data on a bit line corresponding to a bit line number according to the bit line number and transmits the read data to the latch;
during the period that the first working timing signal is at a high level, the latch latches the data read by the sensitive amplifier and transmits the latched data to the latch management module;
the latch management module receives a second working timing sequence signal sent by the control module;
if the second working timing sequence signal is at a high level, the latch management module transmits the received data to the data output module;
and the data output module outputs the received data when the second working timing sequence signal is at a high level.
Optionally, after the sense amplifier receives the first operation timing signal sent by the control module, the method further includes:
and if the first working time sequence signal is at a low level, the sensitive amplifier does not send the read data request to the logic circuit.
Optionally, after the latch management module receives the second operation timing signal sent by the control module, the method further includes:
and if the second working timing sequence signal is at a low level, the latch management module does not transmit the received data to the data output module.
Optionally, during a period when the second operation timing signal is at a high level, the data output module outputs the received data, including:
during the period that the second working timing signal is at a high level, if the first working timing signal is at a high level, the sense amplifier continues to send a new read data request to the logic circuit during the period that the first working timing signal is at a high level, the read of new data is completed, the newly read data is transmitted to the latch, and the latch transmits the newly received data to the latch management module.
Compared with the prior art, the invention provides a circuit for reading data and a method for reading data, wherein the number of the sensitive amplifiers and the latches on the circuit is reduced, the number of the latches is set according to the integral even multiple of the number of the data output by the data output module, the latch management module and the logic circuit are added, bl is selected by the logic circuit according to the number of the sensitive amplifiers during reading according to the working time sequence signal, then the data is read by the sensitive amplifiers and transmitted to the latch management module, the read data is managed by the latch management module, and when the data is required to be output, the data is transmitted to the data output module according to another working time sequence signal to be output, so that the data output is realized, and the mutual interference work is avoided. The circuit for reading data and the method for reading data improve the working efficiency of the nonvolatile memory and greatly reduce the physical layout occupied by sa and latch.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
FIG. 1 is a schematic diagram of a conventional circuit for reading data from a nonvolatile memory;
FIG. 2 is a schematic diagram of a read data circuit according to an embodiment of the present invention;
FIG. 3 is a timing diagram illustrating the operation of t1 and t2 in the embodiment of the present invention;
FIG. 4 is a schematic diagram of a non-volatile memory in an embodiment of the present invention;
FIG. 5 is a flowchart of a method for reading a circuit according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 2, a schematic diagram of a circuit for reading data is shown, the circuit is applied to a nonvolatile memory, the nonvolatile memory includes a memory cell 10, and the circuit for reading data may specifically include:
logic circuit 20 (logic in the figure), sense amplifiers 30 (SA 0-SAx in the figure), latches 40 (latch 0-latch in the figure), latch management block 50 (L atch _ path), and data output block 60(datapath), where the number of sense amplifiers 30 and the number of latches 40 are respectively an even multiple of the number of data output by data output block 60, for example, if the mode of data output by data output block 60 in the embodiment of the present invention is data output in units of 16 data, the number of sense amplifiers 30 and the number of latches 40 may be respectively set to 16, 32, 64, or 128, and the like, and may be set according to user requirements.
The logic circuit 20 is connected to bl of the memory cell and the sense amplifier 30 respectively, and is configured to select a plurality of bl according to the number of the sense amplifiers 30, for example, 32 sense amplifiers 30, so that the logic circuit 20 selects 32 bl at a time to allow the sense amplifier 30 to read data, the sense amplifier 30 is connected to the logic circuit 20 and the latch 40 respectively, and is configured to read data on the plurality of bl selected by the logic circuit 20 according to a first operation timing signal (t 1 in the figure), the latch 40 is connected to the sense amplifier 30 and the latch management module 50 respectively, and is configured to latch the data read by the sense amplifier 30 and transmit the read data to the latch management module 50, the latch management module 50 is connected to the latch 40 and the data output module 60 respectively, and is configured to transmit the received read data to the data output module 60 according to a second operation timing signal (t 2 in the figure), and accepts newly read data, and a data output module 60 is connected to the latch management module 50 for outputting the received data.
Optionally, referring to fig. 2, the nonvolatile memory further includes: control module 70, where the control module 70 is connected to the sense amplifier 30 and the latch management module 50 respectively, and is configured to send a first operation timing signal t1 to the sense amplifier 30 and a second operation timing signal t2 to the latch management module 50, when t1 is at a high level, the sense amplifier 30 reads data from bl of the memory cell and transmits the read data to the latch management module 50 through the latch 40, when t2 is at a high level, the latch management module 50 transmits the read data to the data output module 60 and outputs the read data from the data output module 60, and during a time period when t2 is at a high level, if t1 is also at a high level, the sense amplifier 30 continues to read a next group of data from bl of the memory cell.
For example, referring to the operation timing diagrams of t1 and t2 shown in fig. 3, when a read operation is performed, SA receives a signal of t1, SA sends a request signal for reading data to logic in a high level time period of t1, logic selects 32 bls to be given to sense amplifiers SA0 to SA31 according to the number of SA, SA0 to SA0 read out data in corresponding memory cells through bl and transfer the data to latch0, then latch0 to latch0 transfers the read data to 0 atch _ path, 0 atch _ path receives the signal of t 0, 0 atch transfers the read data to datapath in a 16 data mode of Q < 15: 0> in the high level time period of t 0, and if the operation timing diagrams of t 0 and t 8472 are different from each other, SA0 and SA0 do not occupy the same high level but do not occupy the same time period of SA0 and SA0, SA0 and SA0 are both high levels, and SA 72 are not taken up simultaneously, and SA 72 and SA are taken up at the same time periods.
Optionally, referring to fig. 4, a schematic diagram of a nonvolatile memory in the embodiment of the present invention is shown, where the nonvolatile memory includes: the control module is connected with the circuit for reading data.
According to the above circuit for reading data, referring to fig. 5, an embodiment of the present invention further provides a method for reading a circuit, where the method specifically includes the following steps:
step 101: the sensitive amplifier receives a first working time sequence signal sent by the control module.
In the embodiment of the present invention, the SA0 to SA31 receive the first operation timing signal t1 sent by the control module, where the first operation timing signal is a timing signal with a periodically high and low level change. The embodiment of the present invention is not limited in detail, and may be set according to actual situations.
In the embodiment of the present invention, if t1 received by SA 0-SA 31 is a high signal, a request for reading data is sent to logic, and the high state lasts for a predetermined time. The embodiment of the present invention is not limited in detail, and may be set according to actual situations.
In the embodiment of the present invention, if t1 received by SA 0-SA 31 is a low signal, no request for reading data is sent to logic, and no other operation is performed, and similarly, the low state lasts for a predetermined time. The embodiment of the present invention is not limited in detail, and may be set according to actual situations.
Step 103: during the period that the first working time sequence signal is in a high level, the logic circuit selects a plurality of bit lines according to the number of the sensitive amplifiers according to the read data request, the number of the bit lines is equal to the number of the sensitive amplifiers, and the bit line numbers of the bit lines are sent to the sensitive amplifiers.
In the embodiment of the present invention, in a high level duration period of t1, logic selects 32 bls according to a received read data request, it should be noted that the selected 32 bls are not necessarily bls with bit numbers of 0 to 32, and may be bls with bit numbers of 2 to 34, and only need to satisfy that the selected bls are 32, and are not in sequence, if 0 to 32 is selected in this time, then 0 to 32 will not be selected in the next selection, but the remaining bls are selected until the data reading is completed. logic sends bit numbers of bl to SA 0-SA 31 after bl is selected. The embodiment of the present invention is not limited in detail, and may be set according to actual situations.
Step 104: the sense amplifier receives a bit line number during a period when the first operation timing signal is at a high level.
In the embodiment of the present invention, during the high duration of t1, SA 0-SA 31 receive the bit number of bl sent by logic, so SA 0-SA 31 know which bl data are read. The embodiment of the present invention is not limited in detail, and may be set according to actual situations.
Step 105: during the period that the first working timing signal is in high level, the sensitive amplifier reads the data on the bit line corresponding to the bit line number according to the bit line number and transmits the read data to the latch.
In the embodiment of the present invention, in the sustained period of the high level t1, SA0 to SA31 perform a read operation according to the bit number of bl, read out the data in the memory cell on the bit line corresponding to the bit number of bl, and transfer the read out data to latches latch0 to latch31, it should be noted that, when performing a data read operation once, there may be a memory cell on bl that does not need to be read out according to the address of the required read data, and according to the specification of the nonvolatile memory, the sense amplifier still needs to perform a read operation on all bls, and only some bls do not have data to be read out. The embodiment of the present invention is not limited in detail, and may be set according to actual situations.
Step 106: during the period that the first working timing signal is in high level, the latch latches the data read by the sensitive amplifier and transmits the latched data to the latch management module.
In the embodiment of the present invention, in the sustained period of the high level t1, the latch0 to latch31 latch the received data read from SA0 to SA31, so as to ensure that the data are not lost and play a role of temporary storage, and then transmit the data read from SA0 to SA31 to L atch _ path.
Step 107: and the latch management module receives a second working timing signal sent by the control module.
In this embodiment of the present invention, L atch _ path50 receives data read from SA0 to SA31, but does not immediately operate on the data, but operates according to an enable signal of the control module, and L atch _ path receives the second operation timing signal t2 sent by the control module.
Step 108 a: and if the second working timing sequence signal is at a high level, the latch management module transmits the received data to the data output module.
In the embodiment of the present invention, if t2 is at the high level, L atch _ path transmits the received data to datapath in the high level duration period.
Step 108 b: if the second working timing signal is in a low level, the latch management module does not transmit the received data to the data output module.
In the embodiment of the present invention, if t2 is low, L atch _ path does not transmit the received data to datapath.
Step 109: and the data output module outputs the received data when the second working timing signal is in a high level.
In the embodiment of the present invention, in the period of t2 continuing to be at the high level, datapath outputs the received data, it should be noted that datapath still outputs data according to the mode of outputting 16 data at a time, and the number of read data is 32, so datapath needs to output data twice continuously to complete outputting the data at the time. The embodiment of the present invention is not limited in detail, and may be set according to actual situations.
Optionally, during the period when the second operation timing signal is at the high level, if the first operation timing signal is at the high level, during the period when the first operation timing signal is at the high level, the sense amplifier continues to send a new read data request to the logic circuit, finishes reading new data and transmits the newly read data to the latch, and the latch transmits the newly received data to the latch management module.
In a period of t2 continuing to be at a high level, if t1 is also in a period of t1 continuing to be at a high level, SA 0-SA 31 continue to send a new read data request to logic, the request enables logic to perform bl selection again, the above process is repeated, new data are read and transmitted to L atch _ path, L atch _ path, and when t2 waits for a high level again, the new data are transmitted to datapath, and the process is repeated to realize a pipeline-like working process, so that the working efficiency of reading data is greatly improved.
For example, assuming that a data read operation is performed once, at this time, t1 and t2 are both high, SA0 to SA31 send a request for reading data to logic, and L atch _ path transfers data to datapath, but no data is present in point L atch _ path, so no data is transferred to datapath, in a high-level period for which t1 continues, logic selects bls of bit line numbers 0 to 32, sends 0 to 32 to SA0 to SA31, SA0 to SA31 read data in memory cells on the bls corresponding to 0 to 32 according to the bit line numbers 0 to 32, assuming that there are all data, 32 data are read, SA0 to SA31 send the read data to the corresponding latches 0 to 31, SA0 to latch31, and save the data pair SA data to ensure that data are not lost or missing, then the data transfer is stopped at the low levels of t 59628 to SA 599, and t 849 to SA 599, at this time, and then the data transfer is stopped at the low level of pins 0 to SA 5932 and SA 5926 and SA 0.
L atch _ path receives the data, if the level of t2 is low level at this time, L atch _ path does not perform any operation, but temporarily latches the received data, and if the level of t2 is still high level at this time, L atch _ path transmits the data read out from SA0 to SA31 to datapath in the period of t2 continuing high level, and after the datapath receives the data, 32 data read out from SA0 to SA31 are output twice in a mode of outputting 16 data at a time, thereby completing the whole data output process.
If in the period of t2 high level, t1 changes from low level to high level again, SA 0-SA 31, logic and latch 0-latch 31 start to repeat the above steps of data reading, at this moment, SA 0-SA 31, logic and latch 0-latch 31 read out the data and finally transmit to L latch _ path, while the datapath is also working, outputting the 32 data read last time, and the processes of reading and outputting are not affected mutually, the above processes are repeated, and a pipeline-like working process is generated, so as to improve the efficiency of reading data from the nonvolatile memory, optimally, t2 is in the period of continuous high level, the datapath outputs the data read last time, t2 is in the period of continuous low level, SA 0-SA 31, logic and latch 0-latch 31 finish the next data reading operation and transmit to L latch _ path, and thus the efficiency is highest.
Through the embodiment, the number of the sensitive amplifiers and the number of the latches are set to be an integral and even number times of the number of the output data of the output module, so that the occupied physical layout area is greatly reduced, two newly added circuits, namely logic and L atch _ path, are utilized to respectively carry out respective work between high and low levels of the time sequence of t1 and t2, mutual influence is avoided, and the working efficiency of reading operation is improved.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, herein, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A circuit for reading data, the circuit being applied to a non-volatile memory, the non-volatile memory including memory cells, the circuit comprising: the number of the sensitive amplifiers and the number of the latches are respectively integral and even times of the number of data output by the data output module;
the logic circuit is respectively connected with the bit lines of the memory unit and the sense amplifiers and is used for selecting a plurality of bit lines according to the number of the sense amplifiers, and the number of the bit lines is equal to that of the sense amplifiers;
the sense amplifier is respectively connected with the logic circuit and the latch and used for reading data on the bit lines according to a first working timing signal, wherein the first working timing signal is a working signal for reading data operation of the sense amplifier;
the latch is respectively connected with the sensitive amplifier and the latch management module and is used for latching the data read by the sensitive amplifier and transmitting the latched data to the latch management module;
the latch management module is respectively connected with the latch and the data output module and is used for transmitting the received data to the data output module according to a second working time sequence signal, and the second working time sequence signal is a working signal for the latch management module to carry out data transmission operation;
and the data output module is connected with the latch management module and used for outputting the received data.
2. The circuit of claim 1, wherein the non-volatile memory further comprises: a control module;
the control module is respectively connected with the sense amplifier and the latch management module and is used for sending the first working time sequence signal to the sense amplifier and sending the second working time sequence signal to the latch management module.
3. The circuit of claim 2, wherein when the first operation timing signal is high, the sense amplifier reads data from the plurality of bit lines and transmits the read data to the latch management module through the latch;
when the second working timing signal is at a high level, the latch management module transmits the received data to the data output module, so that the data output module outputs the received data.
4. The circuit of claim 1, wherein the number of data output by the data output module is 16, and the number of the sense amplifiers and the number of the latches are respectively an even integer multiple of 16.
5. The circuit of claim 3, wherein during the period when the second operation timing signal is high, if the first operation timing signal is high, the sense amplifier continues to read a next group of data from the plurality of bit lines.
6. A non-volatile memory, the non-volatile memory comprising: a control module and the circuit for reading data according to any one of claims 1 to 5, said control module being connected to said circuit for reading data.
7. A method for reading data, the method being applied to a circuit for reading data according to any one of claims 1 to 5, the method comprising:
the sensitive amplifier receives a first working time sequence signal sent by the control module;
if the first working time sequence signal is at a high level, the sensitive amplifier sends a data reading request to the logic circuit;
when the first working time sequence signal is at a high level, the logic circuit selects a plurality of bit lines according to the number of the sense amplifiers according to the read data request, the number of the bit lines is equal to the number of the sense amplifiers, and the bit line numbers of the bit lines are sent to the sense amplifiers;
the sense amplifier receives the bit line signal during a period when the first operation timing signal is at a high level;
when the first working time sequence signal is in a high level, the sensitive amplifier reads data on a bit line corresponding to a bit line number according to the bit line number and transmits the read data to the latch;
during the period that the first working timing signal is at a high level, the latch latches the data read by the sensitive amplifier and transmits the latched data to the latch management module;
the latch management module receives a second working timing sequence signal sent by the control module;
if the second working timing sequence signal is at a high level, the latch management module transmits the received data to the data output module;
and the data output module outputs the received data when the second working timing sequence signal is at a high level.
8. The method of claim 7, wherein after the sense amplifier receives the first operation timing signal sent by the control module, the method further comprises:
and if the first working time sequence signal is at a low level, the sensitive amplifier does not send the read data request to the logic circuit.
9. The method of claim 7, wherein after the latch management module receives the second operation timing signal sent by the control module, the method further comprises:
and if the second working timing sequence signal is at a low level, the latch management module does not transmit the received data to the data output module.
10. The method of claim 7, wherein the data output module outputs the received data during the period when the second operation timing signal is at a high level, comprising:
during the period that the second working timing signal is at a high level, if the first working timing signal is at a high level, the sense amplifier continues to send a new read data request to the logic circuit during the period that the first working timing signal is at a high level, the read of new data is completed, the newly read data is transmitted to the latch, and the latch transmits the newly received data to the latch management module.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111968692A (en) * | 2020-10-22 | 2020-11-20 | 深圳市芯天下技术有限公司 | Circuit and chip for reducing area of column redundancy replacement circuit |
| CN114496029A (en) * | 2021-12-24 | 2022-05-13 | 厦门半导体工业技术研发有限公司 | Memory and using method |
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| CN114496029A (en) * | 2021-12-24 | 2022-05-13 | 厦门半导体工业技术研发有限公司 | Memory and using method |
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| CN111489773B (en) | 2023-04-07 |
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