CN111463272B - Tunneling field effect transistor structure - Google Patents
Tunneling field effect transistor structure Download PDFInfo
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- CN111463272B CN111463272B CN202010357071.2A CN202010357071A CN111463272B CN 111463272 B CN111463272 B CN 111463272B CN 202010357071 A CN202010357071 A CN 202010357071A CN 111463272 B CN111463272 B CN 111463272B
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- field effect
- effect transistor
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- 230000005669 field effect Effects 0.000 title claims abstract description 31
- 230000005641 tunneling Effects 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 56
- 239000010410 layer Substances 0.000 claims abstract description 48
- 239000011229 interlayer Substances 0.000 claims abstract description 19
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 12
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 9
- 229910052733 gallium Inorganic materials 0.000 claims description 9
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 9
- 229910052738 indium Inorganic materials 0.000 claims description 6
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 6
- 239000011787 zinc oxide Substances 0.000 claims description 6
- DZLPZFLXRVRDAE-UHFFFAOYSA-N [O--].[O--].[O--].[O--].[Al+3].[Zn++].[In+3] Chemical compound [O--].[O--].[O--].[O--].[Al+3].[Zn++].[In+3] DZLPZFLXRVRDAE-UHFFFAOYSA-N 0.000 claims description 3
- JAONJTDQXUSBGG-UHFFFAOYSA-N dialuminum;dizinc;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Al+3].[Al+3].[Zn+2].[Zn+2] JAONJTDQXUSBGG-UHFFFAOYSA-N 0.000 claims description 3
- TYHJXGDMRRJCRY-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) tin(4+) Chemical compound [O-2].[Zn+2].[Sn+4].[In+3] TYHJXGDMRRJCRY-UHFFFAOYSA-N 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 238000009825 accumulation Methods 0.000 description 4
- 125000005842 heteroatom Chemical group 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D12/211—Gated diodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
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- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本发明公开了一种隧穿场效应晶体管，包括漏极、重掺杂漏区、轻掺杂漂移区、重掺杂源区、非晶氧化物半导体层、栅介质、栅极、层间介质和源极，所述漏极顶部上连接重掺杂漏区，所述重掺杂漏区顶部连接轻掺杂漂移区，所述轻掺杂漂移区顶部设有重掺杂源区，所述轻掺杂漂移区顶部和重掺杂源区顶部与非晶氧化物半导体层连接，所述非晶氧化物半导体层顶部和轻掺杂漂移区顶部与栅介质连接，所述栅介质顶部与栅极连接，所述栅极被层间介质覆盖，所述层间介质与重掺杂源区顶部连接，所述层间介质被源极覆盖，所述源极与重掺杂源区顶部连接。通过使用本发明，可延长场效应晶体管的使用寿命。本发明作为一种隧穿场效应晶体管，可广泛应用于晶体管领域。
The invention discloses a tunneling field effect transistor, comprising a drain, a heavily doped drain region, a lightly doped drift region, a heavily doped source region, an amorphous oxide semiconductor layer, a gate dielectric, a gate, and an interlayer dielectric and source, the top of the drain is connected to a heavily doped drain region, the top of the heavily doped drain region is connected to a lightly doped drift region, and the top of the lightly doped drift region is provided with a heavily doped source region, the The top of the lightly doped drift region and the top of the heavily doped source region are connected to the amorphous oxide semiconductor layer, the top of the amorphous oxide semiconductor layer and the top of the lightly doped drift region are connected to the gate dielectric, and the top of the gate dielectric is connected to the gate The gate electrode is covered by an interlayer dielectric, the interlayer dielectric is connected to the top of the heavily doped source region, the interlayer dielectric is covered by a source electrode, and the source electrode is connected to the top of the heavily doped source region. By using the present invention, the service life of the field effect transistor can be extended. As a tunneling field effect transistor, the present invention can be widely used in the field of transistors.
Description
Technical Field
The invention relates to the field of transistors, in particular to a tunneling field effect transistor structure.
Background
The power semiconductor field effect transistor is widely applied to a power electronic system, a parasitic bipolar transistor exists in the conventional power semiconductor field effect transistor due to structural design defects, the parasitic bipolar transistor can be accidentally turned on under the conditions of avalanche breakdown, body diode reverse recovery, high-energy particle radiation, rapid rise of drain voltage in an off state and the like, and the secondary breakdown characteristic of the parasitic bipolar transistor can cause the power semiconductor field effect transistor to be permanently burned due to local overheating, so that the service life of the power semiconductor field effect transistor is short.
Disclosure of Invention
In order to solve the above technical problems, an object of the present invention is to provide a tunneling field effect transistor, which can make the transistor have no parasitic bipolar transistor and prolong the service life of the field effect transistor.
The first technical scheme adopted by the invention is as follows: a tunneling field effect transistor structure: the transistor comprises a drain electrode, a heavily doped drain region, a lightly doped drift region, a heavily doped source region, an amorphous oxide semiconductor layer, a gate dielectric, a gate electrode, an interlayer dielectric and a source electrode, wherein the heavily doped drain region is connected to the top of the drain electrode, the top of the heavily doped drain region is connected with the lightly doped drift region, the top of the lightly doped drift region is provided with the heavily doped source region, the top of the lightly doped drift region and the top of the heavily doped source region are connected with the amorphous oxide semiconductor layer, the top of the amorphous oxide semiconductor layer and the top of the lightly doped drift region are connected with the gate dielectric, the top of the gate dielectric is connected with the gate electrode, the gate electrode is covered by the interlayer dielectric, the interlayer dielectric is connected with the top of the heavily doped source region, the interlayer dielectric is covered by the source electrode, and the source electrode is connected with the top of the heavily doped source region.
Further, the amorphous oxide semiconductor layer includes, but is not limited to, amorphous indium gallium zinc oxide, amorphous indium tin zinc oxide, amorphous gallium zinc oxide, amorphous indium aluminum zinc oxide, and amorphous indium gallium aluminum zinc oxide.
Further, the electron affinity of the amorphous oxide semiconductor layer is higher than that of single crystal silicon, and the electron layer affinity of the amorphous oxide semiconductor layer is lower than the sum of the electron affinity of the single crystal silicon and the forbidden bandwidth of the single crystal silicon.
Further, the thickness of the amorphous oxide semiconductor layer is between 5nm and 30 nm.
Further, the amorphous oxide semiconductor layer and the heavily doped source region form a heterogeneous PN junction, and the amorphous oxide semiconductor layer and the lightly doped source region drift to form a heterogeneous NN junction.
Further, the heavily doped drain region is of a first conductivity type, the lightly doped drift region is of a first conductivity type, and the heavily doped source region is of a second conductivity type.
Further, the doping concentration of the heavily doped source region is between 1 × 1019cm-3And 1X 1021cm-3。
Further, the gate dielectric and the gate electrode are located in the trench.
Further, the source is isolated from the gate by an interlayer dielectric.
The method has the beneficial effects that: according to the field effect transistor, only one PN junction exists in the field effect transistor structure and a parasitic bipolar transistor does not exist through the light doping drift region, the heavy doping source region and the special structure of the transistor, and the current conducting capacity of the field effect transistor is improved through the addition of the amorphous oxide semiconductor layer.
Drawings
FIG. 1 is a cross-sectional view of an embodiment of the present invention;
FIG. 2 is a band diagram of the present invention when turned on;
FIG. 3 is a schematic top view of an embodiment of the present invention;
FIG. 4 is another schematic top view of an embodiment of the present invention;
fig. 5 is a cross-sectional view of another embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the figures and the specific embodiments. The step numbers in the following embodiments are provided only for convenience of illustration, the order between the steps is not limited at all, and the execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art.
The invention relates to a metal oxide semiconductor field effect transistor which is widely used in analog circuits and digital circuits, wherein the structure of the semiconductor field effect transistor is specially designed, so that the semiconductor field effect transistor only has one PN junction and does not contain a parasitic bipolar transistor, and the conduction process is realized by a tunneling junction in the semiconductor field effect transistor.
As shown in fig. 1, the present invention provides a tunneling field effect transistor 300, which includes a drain 323, a heavily doped drain region 315, a lightly doped drift region 314, a heavily doped source region 313, an amorphous oxide semiconductor layer 312, a gate dielectric 331, a gate 321, an interlayer dielectric 332, and a source 322, wherein the heavily doped drain region 315 is connected on the top of the drain 323, the heavily doped drain region 315 is connected on the top of the heavily doped drain region 314, the lightly doped drift region 314 is provided with a heavily doped source region 313 on the top, the lightly doped drift region 314 and the heavily doped source region 313 are connected on the top of the amorphous oxide semiconductor layer 312 and the lightly doped drift region 314 are connected with the gate dielectric 331, the gate dielectric 331 is connected with the gate 321 on the top, the gate 321 is covered by the interlayer dielectric 332, the interlayer dielectric 332 is connected with the top of the gate 313, and the interlayer dielectric source region 332 is covered by the, the source 322 is connected to the top of the heavily doped source region 313.
In particular, the heavily doped n-type region is labeled n+And the heavily doped p-type region is marked as p+These heavily doped regions typically have a thickness of between 1 × 1019cm-3And 1X 1021cm-3With a doping concentration in between, the lightly doped n-type region being marked n-And the lightly doped p-type region is marked as p-These lightly doped regions usually have a thickness of between 1 × 1013cm-3And 1X 1017cm-3Doping concentration between, source 322 and p+The source region 313 forms an ohmic contact, the source electrode 322 is used for connecting the device with the outside, and the device 300 is sequentially from bottom to top: a drain electrode 323, typically metal, for making connection to the outside; n is+The drain region 315, typically relatively thick (50 to 300 microns), is used to connect n-Drift region 314 and drain 323 and provide mechanical support for the chip; n is- A drift region 314 for blocking a reverse voltage; p is a radical of+ Source region 313, and n-The drift region 314 forms a body diode for blocking reverse voltage; an amorphous oxide semiconductor layer 312, which generates a heterojunction; a gate dielectric 331; a gate 321; an interlayer dielectric 332 for isolating the source electrode 322 from the gate electrode 321; and a source 322 for connecting with the outside.
Further as a preferred embodiment of the present invention, the amorphous oxide semiconductor layer 312 includes, but is not limited to, amorphous indium gallium zinc oxide, amorphous indium tin zinc oxide, amorphous gallium zinc oxide, amorphous indium aluminum zinc oxide, and amorphous indium gallium aluminum zinc oxide.
Further, in a preferred embodiment of the present invention, the electron affinity of the amorphous oxide semiconductor layer is higher than that of single crystal silicon, and the electron layer affinity of the amorphous oxide semiconductor layer is lower than the sum of the electron affinity of single crystal silicon and the band gap of single crystal silicon.
Specifically, notCrystalline oxide semiconductor layer 312 and p+A source region 313 forming a hetero PN junction, an amorphous oxide semiconductor layer 312 and n-There is also a hetero-NN junction between the drift regions 314, both of which have unidirectional conductivity in equilibrium, i.e., current flow is limited to p+The source region 313 flows into the amorphous oxide semiconductor layer 312, and flows from the amorphous oxide semiconductor layer 312 to n- A drift region 314. When the voltage at gate 321 is a positive high voltage, the gate voltage is coupled to the underlying semiconductor surface by an electric field in gate dielectric 331, where n-An electron accumulation region is formed on the surface of the drift region 314, and the concentration of electrons in the amorphous oxide semiconductor layer 312 is also increased, and electrons can be p+Valence band top tunneling of the source region 313 to the conduction band bottom of the amorphous oxide semiconductor layer 312, and tunneling from the conduction band bottom of the amorphous oxide semiconductor layer 312 to n-The above tunneling process can cause current to flow in the device 300 from the drain 323 to the source 322, which is the surface electron accumulation region of the drift region 314, and the device is turned on.
Further as a preferred embodiment of the present invention, the thickness of the amorphous oxide semiconductor layer is between 5nm and 30nm
Specifically, to improve tunneling efficiency in the device 300, the thickness of the amorphous oxide semiconductor layer 312 should be approximately equal to the thickness of its surface electron accumulation layer. An excessively low thickness of the amorphous oxide semiconductor layer 312 causes insufficient electron density of the surface participating in conduction, and thus the thickness thereof is generally higher than 5 nm. The thickness of the amorphous oxide semiconductor layer 312 is too high, which causes the hetero PN junction barrier described above to be widened and the tunneling current to be reduced, so that the thickness thereof is generally not more than 30 nm.
Further as a preferred embodiment of the present invention, the amorphous oxide semiconductor layer and the heavily doped source region form a hetero PN junction, and the amorphous oxide semiconductor layer and the lightly doped drift form a hetero NN junction.
Specifically, the on-state current of the device 300 results in tunneling at both heterojunctions, where the built-in barrier height of each heterojunction is below 1.12 eV. For example, the barrier height of the PN junction is 0.62eV, the barrier height of the NN junction is 0.5eV, and at this time, the tunneling currents of both the heterojunction barriers can be much larger than 1 μ a/μm, the on-current capability of the device 300 is greatly improved, and the on-resistance is obviously reduced.
As a further preferred embodiment of the present invention, the heavily doped drain region is of a first conductivity type, the lightly doped drift region is of a first conductivity type, and the heavily doped source region is of a second conductivity type.
Further as a preferred embodiment of the present invention, the doping concentration of the heavily doped source region is between 1 × 1019cm-3And 1X 1021cm-3。
Further in accordance with a preferred embodiment of the present invention, the gate dielectric and the gate electrode are located in the trench.
Further in accordance with a preferred embodiment of the present invention the source is isolated from the gate by an interlayer dielectric.
FIG. 3 is a schematic top view of an embodiment of the present invention, which corresponds exactly to the cross-sectional view of FIG. 1, that is, a device 300 having a typical striped cell structure, an amorphous oxide semiconductor layer 312 and a p-type semiconductor layer+The source regions 313 are disposed in parallel with the overlapping width thereof being constant, fig. 4 is another schematic top view according to an embodiment of the present invention, which does not exactly correspond to the cross-sectional view of fig. 1, and as shown in fig. 4, the amorphous oxide semiconductor layer 312 has a rectangular top view and is aligned with p+The source region 313 is vertical, in which case the principle of operation of the device remains unchanged, when on, p+Electrons in the source region 313 can tunnel to the conduction band bottom of the amorphous oxide semiconductor layer 312 first, and then tunnel to n from the conduction band bottom of the amorphous oxide semiconductor layer-The drift region 314 has a surface electron accumulation region, and the corresponding electron movement path is shown by the arrow in the figure.
Another embodiment of the present invention is as follows:
While the preferred embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. The tunneling field effect transistor is characterized by comprising a drain electrode, a heavily doped drain region, a lightly doped drift region, a heavily doped source region, an amorphous oxide semiconductor layer, a gate dielectric, a gate electrode, interlayer dielectric and a source electrode, wherein the top of the drain electrode is connected with the heavily doped drain region, the top of the heavily doped drain region is connected with the lightly doped drift region, the top of the lightly doped drift region is provided with the heavily doped source region, the top of the lightly doped drift region and the top of the heavily doped source region are connected with the amorphous oxide semiconductor layer, the top of the amorphous oxide semiconductor layer and the top of the lightly doped drift region are connected with the gate dielectric, the top of the gate dielectric is connected with the gate electrode, the gate electrode is covered by the interlayer dielectric, the interlayer dielectric is connected with the top of the heavily doped source region.
2. The tunneling field effect transistor of claim 1, wherein the amorphous oxide semiconductor layer comprises but is not limited to amorphous indium gallium zinc oxide, amorphous indium tin zinc oxide, amorphous gallium zinc oxide, amorphous indium aluminum zinc oxide, amorphous indium gallium aluminum zinc oxide.
3. The tunneling field effect transistor according to claim 2, wherein the electron affinity of the amorphous oxide semiconductor layer is higher than that of single-crystal silicon, and the electron affinity of the amorphous oxide semiconductor layer is lower than the sum of the electron affinity of single-crystal silicon and the forbidden band width of single-crystal silicon.
4. A tunneling field effect transistor according to claim 3, wherein the thickness of the amorphous oxide semiconductor layer is between 5nm and 30 nm.
5. The tunneling field effect transistor of claim 4, wherein the amorphous oxide semiconductor layer forms a hetero-PN junction with the heavily doped source region and the amorphous oxide semiconductor layer forms a hetero-NN junction with the lightly doped drift region.
6. The tunneling field effect transistor of claim 1, wherein the heavily doped drain region is of a first conductivity type, the lightly doped drift region is of the first conductivity type, and the heavily doped source region is of a second conductivity type.
7. The tunneling field effect transistor of claim 1, wherein the heavily doped source region has a doping concentration of 1 x 1019cm-3And 1X 1021cm-3In the meantime.
8. The tunneling field effect transistor of claim 1, wherein the lightly doped drift region has a doping concentration of 1 x 1013cm-3And 1X 1017cm-3In the meantime.
9. A tunneling field effect transistor according to claim 1, wherein the gate dielectric and the gate electrode are located in a trench.
10. A tunneling field effect transistor according to claim 1, wherein the source is isolated from the gate by an interlayer dielectric.
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| CN113540225B (en) * | 2021-07-19 | 2022-06-10 | 西安电子科技大学 | A high-performance recessed-gate tunneling field effect transistor based on a quasi-off-band heterojunction and a preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102593180A (en) * | 2012-03-14 | 2012-07-18 | 清华大学 | Tunneling transistor with heterogeneous gate dielectric and forming method for tunneling transistor |
| CN102751325A (en) * | 2011-04-21 | 2012-10-24 | 中国科学院微电子研究所 | Tunneling field effect transistor and manufacturing method thereof |
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| JPH01160056A (en) * | 1987-12-16 | 1989-06-22 | Nec Corp | Manufacture of thin-film field-effect transistor |
| CN101454659A (en) * | 2006-05-29 | 2009-06-10 | 皇家飞利浦电子股份有限公司 | Organic field-effect transistor for sensing applications |
| ATE490560T1 (en) * | 2007-05-31 | 2010-12-15 | Canon Kk | METHOD FOR PRODUCING A THIN FILM TRANSISTOR WITH AN OXIDE SEMICONDUCTOR |
| JP5354999B2 (en) * | 2007-09-26 | 2013-11-27 | キヤノン株式会社 | Method for manufacturing field effect transistor |
| CN101635308B (en) * | 2009-08-27 | 2012-03-07 | 绍兴文理学院 | High-k gate dielectric material and preparation method thereof |
| US9647135B2 (en) * | 2015-01-22 | 2017-05-09 | Snaptrack, Inc. | Tin based p-type oxide semiconductor and thin film transistor applications |
| CN106571391B (en) * | 2016-03-22 | 2020-06-30 | 廖慧仪 | Robust power semiconductor field effect transistor structure |
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| CN102751325A (en) * | 2011-04-21 | 2012-10-24 | 中国科学院微电子研究所 | Tunneling field effect transistor and manufacturing method thereof |
| CN102593180A (en) * | 2012-03-14 | 2012-07-18 | 清华大学 | Tunneling transistor with heterogeneous gate dielectric and forming method for tunneling transistor |
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