CN111463212B - Quick erasable floating gate memory and preparation method thereof - Google Patents

Abstract

The invention belongs to the technical field of semiconductor devices, in particular to a fast rewritable floating gate memory and a preparation method thereof. The fast rewritable floating gate memory of the present invention comprises: a substrate; a barrier layer covering the substrate, which is an insulating medium; a floating gate formed on the barrier layer; A mass junction and a second heterojunction, composed of two-dimensional materials; a tunneling layer covering the first heterojunction and the second heterojunction, which is a two-dimensional material; a trench formed on the tunneling layer a channel layer, which is a two-dimensional material; and a source electrode and a drain electrode formed on the surface of the channel layer. The present invention adopts the heterojunction composed of two two-dimensional semiconductor materials with opposite conduction directions as the charge erasing and writing channel, which can effectively improve the symmetry of the charge erasing and writing speed and speed up the reading and writing speed.

Description

A kind of fast rewritable floating gate memory and preparation method thereof

technical field

The invention belongs to the technical field of semiconductor devices, and in particular relates to a fast rewritable floating gate memory and a preparation method thereof.

Background technique

Today's mainstream storage technologies are divided into two categories: volatile storage technologies and non-volatile storage technologies. For volatile storage technologies, mainly static random access memory SRAM and dynamic random access memory DRAM. Volatile memory has nanosecond write speed, but its data retention capability is only milliseconds, which makes it only used in limited storage areas such as cache. For non-volatile storage technology, such as flash memory technology, its data retention capability can reach 10 years, but the relatively slow write operation greatly limits its application in the field of cache. For flash memory technology, this low erasing speed is mainly due to the contradiction between the thickness reduction of the tunnel oxide layer and the charge retention capability. Patent CN107665894A proposes a semi-floating gate memory based on two-dimensional semiconductor materials. In this kind of semi-floating gate memory, the electric charge realizes the nanosecond fast writing operation through the PN junction composed of the two-dimensional material, but the erasing operation is realized through the tunneling effect of the oxide layer. Among them, the erasing speed is much slower than the writing speed, which means that the erasing and writing speeds are seriously asymmetrical.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a fast rewritable floating gate memory which can effectively improve the symmetry of the charge erasing and writing speed and speed up the reading and writing speed and a preparation method thereof.

The fast rewritable floating gate memory provided by the present invention includes:

substrate;

a barrier layer, which is an insulating medium, covering the substrate;

a floating gate formed on the barrier layer;

The first heterojunction and the second heterojunction, which are composed of two-dimensional materials, are placed on the floating gate in parallel and adjacent, and the conduction directions of the two heterojunctions are opposite;

a tunneling layer, which is a two-dimensional material, covering the first heterojunction and the second heterojunction;

a channel layer, which is a two-dimensional material, formed on the tunneling layer; and

A source electrode and a drain electrode are formed on the surface of the channel layer.

In the flash rewritable floating gate memory of the present invention, preferably, the first end of the first heterojunction and the first end of the second heterojunction are placed in parallel and adjacent to the floating gate gate, and the the second end of the first heterojunction and the second end of the second heterojunction are placed on the first end of the first heterojunction and the first end of the second heterojunction, respectively, and Adjacent in parallel, the first end of the first heterojunction and the second end of the second heterojunction are made of the same two-dimensional material, and the second end of the first heterojunction and the second heterojunction The first end of the junction is the same two-dimensional material.

In the fast rewritable floating gate memory of the present invention, preferably, the two-dimensional material of the first end of the first heterojunction and the second end of the second heterojunction is p-type WSe ₂ or MoSe ₂ , Either n-type HfS ₂ or MoS ₂ , the second end of the first heterojunction and the first end of the second heterojunction are n-type HfS ₂ or MoS ₂ , or p-type WSe ₂ or MoSe ₂ .

In the fast rewritable floating gate memory of the present invention, preferably, the barrier layer is Al ₂ O ₃ , SiO ₂ , HfO ₂ , Ta ₂ O ₅ , TiO ₂ , HfZrO ₄ or a stack composed of part of the aforementioned materials .

In the fast rewritable floating gate memory of the present invention, preferably, the material of the tunneling layer is hexagonal boron nitride, CuInP ₂ S ₆ , or a stack composed of the two.

The preparation method of the above-mentioned fast erasable and rewritable floating gate memory provided by the present invention includes the following steps:

depositing an insulating medium on the substrate as a barrier layer;

forming a floating gate on the barrier layer;

forming a first heterojunction and a second heterojunction which are placed in parallel and adjacent to each other and have opposite conduction directions by stacking two-dimensional materials;

forming a tunneling layer on the first heterojunction and the second heterojunction;

forming a channel layer on the tunneling layer;

forming source and drain electrodes on the channel layer;

Wherein, the tunneling layer, the channel layer, the source electrode and the drain electrode are all two-dimensional materials.

In the method for manufacturing a flash rewritable floating gate memory of the present invention, preferably, the first end of the first heterojunction and the first end of the second heterojunction are transferred to the floating gate in parallel and adjacently. , transferring the second end of the first heterojunction and the second end of the second heterojunction to the first end of the first heterojunction and the first end of the second heterojunction, respectively end, and are adjacent to each other in parallel, the first end of the first heterojunction and the second end of the second heterojunction are the same two-dimensional material, the second end of the first heterojunction and the The first end of the second heterojunction is the same two-dimensional material.

In the preparation method of the flash rewritable floating gate memory of the present invention, preferably, the two-dimensional materials of the first end of the first heterojunction and the second end of the second heterojunction are p-type WSe ₂ , MoSe ₂ , or n-type HfS ₂ , MoS ₂ , the second end of the first heterojunction and the first end of the second heterojunction are n-type HfS ₂ , MoS ₂ , or p-type WSe ₂ , MoSe ₂ .

In the preparation method of the flash rewritable floating gate memory of the present invention, preferably, the barrier layer is Al ₂ O ₃ , SiO ₂ , HfO ₂ , Ta ₂ O ₅ , TiO ₂ , HfZrO ₄ or a material composed of some of the foregoing materials. Laminate

In the preparation method of the fast rewritable floating gate memory of the present invention, preferably, in the step of forming the floating gate on the barrier layer, Pd, Ni or Au is formed as the floating gate by physical vapor deposition pulsed laser deposition or electron beam evaporation. .

The present invention adopts the heterojunction composed of two two-dimensional semiconductor materials with opposite conduction directions as the charge erasing and writing channel, which can effectively improve the symmetry of the charge erasing and writing speed and speed up the reading and writing speed.

Description of drawings

FIG. 1 is a flow chart of a method for fabricating a flash rewritable floating gate memory.

FIG. 2 is a schematic diagram of the device structure after forming the barrier layer.

FIG. 3 is a schematic diagram of the device structure after forming the floating gate.

FIG. 4 is a schematic diagram of a first-end device structure forming a first end of a first heterojunction and a second heterojunction.

FIG. 5 is a schematic diagram of the device structure of the second end of the first heterojunction and the second end of the second heterojunction.

FIG. 6 is a schematic diagram of a device structure for forming a tunneling layer.

FIG. 7 is a schematic diagram of the device structure after the formation of the channel layer.

FIG. 8 is a schematic diagram of a device structure for forming a drain and a source.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It should be understood that the specific The embodiments are only used to explain the present invention, and are not intended to limit the present invention. The described embodiments are only some, but not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "vertical", "horizontal", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for convenience The invention is described and simplified without indicating or implying that the device or element referred to must have a particular orientation, be constructed and operate in a particular orientation, and therefore should not be construed as limiting the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed to indicate or imply relative importance.

Furthermore, numerous specific details of the present invention are described below, such as device structures, materials, dimensions, processing techniques and techniques, in order to provide a clearer understanding of the present invention. However, as will be understood by one skilled in the art, the present invention may be practiced without these specific details. Unless specifically indicated below, various parts of the device may be constructed of materials known to those skilled in the art, or materials developed in the future with similar functions may be employed.

The specific embodiments of the present invention will be further described below with reference to the accompanying drawings 1 to 8 . FIG. 1 is a flow chart of a method for fabricating a fast rewritable floating gate memory, and FIGS. 2 to 8 show structural schematic diagrams of each step of the method for fabricating a fast rewritable floating gate memory. The specific steps are:

In step S1, the substrate 200 is provided as the bottom gate of the floating gate memory. The substrate may be a low resistance silicon substrate, silicon on insulator, tantalum nitride/silicon dioxide/silicon substrate, or titanium nitride/silicon dioxide/silicon substrate. A low-resistance silicon substrate is used in this embodiment mode. Then, an insulating medium is deposited on the surface of the substrate 200 to form a barrier layer 201, and the obtained structure is shown in FIG. 2 . In this embodiment, Al ₂ O ₃ is formed as the barrier layer by atomic layer deposition, but the present invention is not limited to this, and the barrier layer can also be made of other suitable materials, such as SiO ₂ , HfO ₂ , Ta ₂ O ₅ , TiO ₂ , HfZrO ₄ or a stack composed of the aforementioned materials, etc., the formation method can also be chemical vapor deposition, physical vapor deposition, pulsed laser deposition, electron beam evaporation and the like.

In step S2 , metal is deposited on the surface of the barrier layer as the floating gate 202 , and the obtained structure is shown in FIG. 3 . For example, Pt is formed as the floating gate by physical vapor deposition, but the present invention is not limited to this, and the floating gate material can also be other suitable materials, such as Pd, Ni or Au, and the forming method can also be pulsed laser deposition or electron beam evaporation.

In step S3, two two-dimensional materials with opposite conductivity types are transferred to the surface of the floating gate 202 in parallel and adjacent to each other by a mechanical lift-off method, respectively serving as the first end 203 of the first heterojunction and the first end of the second heterojunction. end 204 and the resulting structure is shown in FIG. 4 . Then, two two-dimensional materials with opposite conductivity types are transferred to the surfaces of the first end 203 of the first heterojunction and the surface of the first end 204 of the second heterojunction by a mechanical lift-off method, and make them adjacent to each other in parallel, As the second end 205 of the first heterojunction and the second end 206 of the second heterojunction, the resulting structure is shown in FIG. 5 . The first heterojunction composed of the first end 203 of the first heterojunction and the second end 205 of the first heterojunction, and the first end 204 of the second heterojunction and the first end 204 of the second heterojunction. The conduction directions of the second heterojunction formed by the two ends 206 are opposite. In this embodiment, the materials of the first end 203 of the first heterojunction and the second end 206 of the second heterojunction are both p-type conductive two-dimensional material WSe ₂ , and the first end 204 of the second heterojunction and the material of the second end 205 of the first heterojunction are both n-type conductive MoS ₂ . However, the present invention is not limited to this. For example, the materials constituting the first heterojunction and the second heterojunction can also be HfS ₂ and MoS ₂ with n-type conductivity, and WSe ₂ and MoSe ₂ with p-type conductivity. The conduction direction of the mass junction can be reversed. Using a heterojunction composed of two 2D semiconductor materials in opposite directions as the charge erasing and writing channel can effectively improve the symmetry of the charge erasing and writing speed. The two-dimensional semiconductor material PN junction is used as the erasing and writing channel to speed up the reading and writing speed. The potential barrier between the metal floating gate and the heterojunction can be tuned by selecting an appropriate metal work function through energy band engineering.

In step S4 , the surfaces of the first heterojunction and the second heterojunction of the two-dimensional material are used as the tunneling layer 207 by a mechanical lift-off method, and the obtained structure is shown in FIG. 6 . In this embodiment, hexagonal boron nitride (hBN) is used as the tunneling layer material, but the present invention is not limited thereto, and CuInP ₂ S ₆ (CIPS) or CIPS/hBN stack can also be used as the tunneling layer material. Due to the addition of the heterojunction, the thickness of the tunnel oxide layer can be further reduced, thereby accelerating the read and write speed.

In step S5 , the two-dimensional material is transferred to the surface of the tunneling layer by a mechanical lift-off method to serve as the channel layer 208 , and the obtained structure is shown in FIG. 7 . The two-dimensional material may be HfS 2 or MoS ₂ with n-type conductivity or WSe ₂ or MoSe ₂ with p-type conductivity. In this embodiment, WSe ₂ with p _- type conductivity is used.

In step S6, the graphene is transferred to the surface of the channel layer 208 by means of mechanical exfoliation, and used as the drain electrode 209 and the source electrode 210, respectively, and the obtained structure is shown in FIG. 8 .

In the above, the specific implementations of a fast erasable and rewritable floating gate memory and a method for manufacturing the same of the present invention have been described in detail, but the present invention is not limited thereto. The specific implementation of each step may vary according to the situation. In addition, the order of some steps may be reversed, some steps may be omitted, and the like.

FIG. 8 is a schematic diagram of the structure of the flash rewritable floating gate memory of the present invention. As shown in FIG. 8, the fast rewritable floating gate memory includes: a substrate 200; a barrier layer 201, which is an insulating medium, covering the substrate 200; a floating gate 202, formed on the barrier layer 201; a first heterojunction and The second heterojunction, which is composed of two-dimensional materials, is placed on the floating gate 202 in parallel and adjacent to each other, and the conduction directions of the two heterojunctions are opposite; the tunneling layer 207, which is a two-dimensional material, covers the first heterojunction and the second heterojunction; the channel layer 208 , which is a two-dimensional material, is formed on the tunneling layer; and the drain electrode 209 and the source electrode 210 are formed on the surface of the channel layer 208 .

The first end 203 of the first heterojunction and the first end 204 of the second heterojunction are placed on the floating gate 202 in parallel and adjacent, and the second end 205 of the first heterojunction and the first end 205 of the second heterojunction The two ends 206 are respectively placed on the first end 203 of the first heterojunction and the first end 204 of the second heterojunction, and are adjacent to each other in parallel. Preferably, the first end 203 of the first heterojunction and the second end 206 of the second heterojunction are made of the same two-dimensional material, and the second end 205 of the first heterojunction and the first end of the second heterojunction 204 is the same two-dimensional material. Further preferably, the two-dimensional material of the first end 203 of the first heterojunction and the second end 206 of the second heterojunction is p-type WSe ₂ , MoSe ₂ or n-type HfS ₂ , MoS ₂ , the first heterojunction The second end 205 of the junction and the first end 204 of the second heterojunction are n-type HfS ₂ , MoS ₂ or p-type WSe ₂ , MoSe ₂ .

Preferably, the barrier layer is Al ₂ O ₃ , SiO ₂ , HfO ₂ , Ta ₂ O ₅ , TiO ₂ , HfZrO ₄ or a stack consisting of some of the aforementioned materials.

Preferably, the material of the tunneling layer is hexagonal boron nitride, CuInP ₂ S ₆ or a stack composed of both.

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical scope disclosed by the present invention can easily think of changes or substitutions. All should be included within the protection scope of the present invention.

Claims (10)

1. A fast rewritable floating gate memory, characterized in that, comprising: substrate; a barrier layer, which is an insulating medium, covering the substrate; a floating gate formed on the barrier layer; The first heterojunction and the second heterojunction, which are composed of two-dimensional materials, are placed on the floating gate in parallel and adjacent, and the conduction directions of the two heterojunctions are opposite; a tunneling layer, which is a two-dimensional material, covering the first heterojunction and the second heterojunction; a channel layer, which is a two-dimensional material, formed on the tunneling layer; and A source electrode and a drain electrode are formed on the surface of the channel layer. 2 . The flash rewritable floating gate memory according to claim 1 , wherein the first end of the first heterojunction and the first end of the second heterojunction are placed in parallel and adjacent to the On the floating gate, the second end of the first heterojunction and the second end of the second heterojunction are placed on the first end of the first heterojunction and the second end of the second heterojunction, respectively. on the first end, and are contiguous in parallel, The first end of the first heterojunction and the second end of the second heterojunction are made of the same two-dimensional material, and the second end of the first heterojunction and the second end of the second heterojunction are made of the same two-dimensional material. One end is the same two-dimensional material. 3 . The fast rewritable floating gate memory according to claim 2 , wherein the two-dimensional material of the first end of the first heterojunction and the second end of the second heterojunction is p-type. 4 . WSe ₂ or MoSe ₂ , or n-type HfS ₂ or MoS ₂ ; the second end of the first heterojunction and the first end of the second heterojunction are n-type HfS ₂ or MoS ₂ , or p-type WSe ₂ or MoSe ₂ . 4 . The fast rewritable floating gate memory according to claim 1 , wherein the barrier layer is one of Al ₂ O ₃ , SiO ₂ , HfO ₂ , Ta ₂ O ₅ , TiO ₂ , and HfZrO ₄ . , or a stack of several of them. 5 . The fast rewritable floating gate memory according to claim 1 , wherein the material of the tunneling layer is hexagonal boron nitride, CuInP ₂ S ₆ , or a stack composed of the two. 6 . 6. A method for preparing a fast rewritable floating gate memory, comprising the following steps: depositing an insulating medium on the substrate as a barrier layer; forming a floating gate on the barrier layer; forming a first heterojunction and a second heterojunction which are placed in parallel and adjacent to each other and have opposite conduction directions by stacking two-dimensional materials; forming a tunneling layer on the first heterojunction and the second heterojunction; forming a channel layer on the tunneling layer; forming source and drain electrodes on the channel layer, Wherein, the tunneling layer, the channel layer, the source electrode and the drain electrode are all two-dimensional materials. 7. The method for preparing a fast rewritable floating gate memory according to claim 6, wherein, Transfer the first end of the first heterojunction and the first end of the second heterojunction in parallel to the floating gate, and connect the second end of the first heterojunction to the first end of the second heterojunction. The second ends of the two heterojunctions are respectively transferred to the first end of the first heterojunction and the first end of the second heterojunction, and are adjacent to each other in parallel, The first end of the first heterojunction and the second end of the second heterojunction are made of the same two-dimensional material, and the second end of the first heterojunction and the second end of the second heterojunction are made of the same two-dimensional material. One end is the same two-dimensional material. 8. The method for preparing a fast rewritable floating gate memory according to claim 7, wherein, The two-dimensional material of the first end of the first heterojunction and the second end of the second heterojunction is p-type WSe ₂ or MoSe ₂ , or n-type HfS ₂ or MoS ₂ , and the first heterojunction The second end of the mass junction and the first end of the second heterojunction are n-type HfS ₂ or MoS ₂ , or p-type WSe ₂ or MoSe ₂ . 9 . The method for preparing a flash rewritable floating gate memory according to claim 6 , wherein the barrier layer is Al ₂ O ₃ , SiO ₂ , HfO ₂ , Ta ₂ O ₅ , TiO ₂ , HfZrO ₄ or A laminate consisting of some of the foregoing materials. 10. The method for preparing a fast rewritable floating gate memory according to claim 6, wherein in the step of forming the floating gate on the barrier layer, Pd, Ni or Au as floating gate.

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