CN111403476B - Trench gate MOS power device and gate manufacturing method thereof - Google Patents

Abstract

According to the trench gate MOS power device and the gate manufacturing method thereof, two gate oxide layers with different thicknesses are formed at different positions through the twice thermal oxidation process, the threshold voltage can meet the normal working requirements of the trench gate MOS power device through the arrangement of the thin oxide layers, the normal switching action of the MOS power device is ensured, the miller capacitance can be reduced through the thick oxide layer, the problem that the switching action is difficult to regulate and control is solved, the switching loss is reduced, the carrier bombardment resistance of the thick oxide layer is high, and the long-range reliability of the whole device is improved. The invention reduces the Miller capacitance while ensuring the normal switching action of the MOS power device, solves the problem that the switching action is difficult to regulate and control, reduces the switching loss, improves the long-range reliability and is not limited by the threshold voltage.

Description

Trench gate MOS power device and gate manufacturing method thereof

technical field

The invention belongs to the field of semiconductors, and in particular relates to a trench gate MOS power device and a gate manufacturing method thereof.

Background technique

The gate oxide layer of conventional trench gate MOS (Metal Oxide Semiconductor) power devices is formed by single thermal oxidation. Due to the limitation of the threshold voltage, the thickness of the thermal oxide layer is usually not too thick, that is, the capacitance C _OX of the gate oxide layer is relatively large. The Miller capacitance of the device can be expressed by:

The larger the capacitance C _OX of the gate oxide layer, the higher the Miller capacitance C _Miller , so that the switching behavior is difficult to control and the switching loss is difficult to reduce. At the same time, since the bottom of the trench is usually a high electric field region, carriers are constantly bombarded and injected into the gate oxide layer at the bottom of the trench during the transport process, thereby affecting the long-range reliability of the gate and the entire device. The structure of the gate oxide layer of a conventional MOS power device is shown in Figure 1. The entire gate oxide layer is a thin oxide layer 111 formed by a single thermal oxidation, and the gate body is formed of polysilicon 12, which is arranged in the trench. 12 and the collector 13 between the equivalent series capacitance C _OX and C _S .

Contents of the invention

In order to solve the high Miller capacitance of trench gate MOS power devices in the prior art, it is difficult to control the switching behavior and reduce the switching loss; the carrier bombards the gate oxide layer and affects the long-term reliability of the gate and the entire device. Problem, the present invention provides a trench gate MOS power device and its gate manufacturing method, the specific scheme is as follows:

A method for manufacturing a gate of a trench gate MOS power device, comprising the steps of:

Step S1: forming a channel region and a trench;

Step S2: primary oxidation, forming a thick oxide layer in the trench;

Step S3: removing the unnecessary thick oxide layer;

Step S4: secondary oxidation, forming a thin oxide layer above the thick oxide layer;

Step S5: forming a gate body.

Further, in the step S3, the photoresist is used as a mask to control the final etching position of the thick oxide layer.

Further, in the step S2, the thick oxide layer is formed on the top of the bulk material;

Described step S3 comprises the following steps:

Step S301: filling the trench with the photoresist, and disposing the photoresist on the upper surface of the thick oxide layer;

Step S302: exposing the photoresist, and controlling the exposure depth of the photoresist;

Step S303: removing the exposed photoresist;

Step S304: using the remaining photoresist as a mask to etch the thick oxide layer;

Step S305: removing the remaining photoresist in the trench.

Further, in the step S302, the bottom surface of the exposed photoresist is close to and higher than the bottom surface of the channel region.

Further, in the step S1, a carrier injection region is also formed, and in the step S302, the bottom surface of the exposed photoresist is close to and higher than the bottom surface of the carrier injection region.

Further, in the step S304, the thick oxide layer is etched by over-etching.

Further, in the step S304, the overetching amount of the thick oxide layer is controlled by the etching time.

Further, in the step S5, polysilicon is deposited in the trench and on the upper surface of the gate oxide layer, so that the polysilicon fills the trench, and then the polysilicon is etched so that the upper surface of the polysilicon is lower than the upper surface of the thin oxide layer. surface.

A trench gate MOS power device fabricated by the gate manufacturing method as described above is characterized in that it includes a channel region, the gate oxide layer corresponding to the channel region is a thin oxide layer, and the thin oxide layer The gate oxide layer below the layer is thick oxide.

Further, a carrier injection region adjacent to the channel region is provided below the channel region, and the gate oxide layer corresponding to the carrier injection region is the thin oxide layer.

Compared with the prior art, the present invention provides a trench-gate MOS power device and its gate manufacturing method. Two kinds of gate oxide layers with different thicknesses are formed at different positions through two thermal oxidation processes. The setting of the oxide layer enables the threshold voltage to meet the normal working requirements of the trench gate MOS power devices and ensure the normal switching action of the MOS power devices. The thick oxide layer can reduce the Miller capacitance, solve the problem that the switching behavior is difficult to control and reduce the Switching loss, and the thick oxide layer has a strong ability to withstand carrier bombardment, which improves the long-term reliability of the entire device. While ensuring the normal switching action of the MOS power device, the invention reduces the Miller capacitance, solves the problem that the switching behavior is difficult to control, reduces the switching loss, and improves the long-distance reliability without being limited by the threshold voltage.

Description of drawings

Hereinafter, the present invention will be described in more detail based on the embodiments with reference to the accompanying drawings. in:

FIG. 1 is a schematic diagram of the structure of an IGBT in the prior art;

Fig. 2 is a schematic diagram of the structure of an IGBT in an embodiment of the present invention;

Fig. 3 is a schematic structural diagram formed after implementing step S1 in the embodiment of the present invention;

Fig. 4 is a schematic structural view of forming a thick oxide layer after one thermal oxidation in an embodiment of the present invention;

Fig. 5 is a schematic diagram of the structure formed after adding photoresist in the embodiment of the present invention;

6 is a schematic structural view of the photoresist after exposure in the embodiment of the present invention;

FIG. 7 is a schematic diagram of the structure after removing the exposed photoresist in the embodiment of the present invention;

FIG. 8 is a schematic diagram of the structure after etching the thick oxide layer using the remaining photoresist as a mask in the embodiment of the present invention;

FIG. 9 is a schematic structural diagram of removing remaining photoresist in an embodiment of the present invention;

FIG. 10 is a schematic structural view of FIG. 7 showing the formation of a thin oxide layer above the thick oxide layer by secondary oxidation in an embodiment of the present invention;

FIG. 11 is a schematic diagram of the structure after depositing polysilicon in an embodiment of the present invention;

FIG. 12 is a schematic structural view of etching polysilicon to form a gate body in an embodiment of the present invention.

In the drawings, the same components are given the same reference numerals, and the drawings are not drawn to scale.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings.

The channel region in the present invention refers to a well region capable of forming an inversion layer under the action of a gate voltage;

The gate in the present invention includes a gate body and a gate oxide layer.

The thickness and thinness of the gate oxide layer in the present invention are relative concepts, and the thickness of a thick oxide layer is thicker than that of a thin oxide layer.

Embodiment one:

As shown in Figure 2, this embodiment provides a trench gate MOS power device, taking a trench gate IGBT (InsulatedGate Bipolar Transistor) as an example, which includes a channel region, specifically, the trench gate IGBT in this embodiment The channel region is the P well region 15 . Usually, in order to form a complete trench gate IGBT structure, an N+ source region (not shown in the figure) contacting the emitter electrode is also provided above the P well region 15, which is common knowledge and will not be discussed in detail.

In this embodiment, a carrier injection region next to the P well region 15 is also provided below the P well region 15. Specifically, the carrier injection region in this embodiment is the N well region 14, and the N well region 14 When the trench gate IGBT works, the carrier injection level can be increased. The gate oxide layer corresponding to the P well region 15 and the N well region 14 is the same thin oxide layer 111 as the gate oxide layer of the conventional trench gate MOS power device, therefore, the threshold voltage of the conventional trench gate MOS power device can be The working requirements of the P well region 15 and the N well region 14 are met, so that under the action of the gate voltage, the P well region 15 forms an inversion layer, and the N well region 14 forms a depletion layer. The gate oxide layer below the thin oxide layer 111 is a thick oxide layer 112. The setting of the thick oxide layer 112 avoids the positions of the P well region 15 and the N well region 14, and avoids the gate due to the limitation of the threshold voltage. The extremely thick oxide layer should not be too thick. At the same time, it can be seen from the calculation formula of Miller capacitance that setting a thick oxide layer 112 under the thin oxide layer 111, that is, at the bottom of the trench 16, reduces the Miller capacitance, thereby solving the problem that the switching behavior is difficult to control. and reduce the switching loss; the thick oxide layer 112 has a strong ability to withstand carrier bombardment, which improves the long-range reliability of the entire device.

Preferably, the bottom surface of thin oxide layer 111 is lower than the bottom surface of N well region 14, and the top surface of thin oxide layer 111 is higher than the top surface of P well region 15, to ensure that P well region 15 and N well region 14 can be completely connected with The thin oxide layer 111 corresponds. In this embodiment, a P well region 15 and an N well region 14 are arranged symmetrically on both sides of the trench 16 .

As shown in FIG. 3-FIG. 12, this embodiment also provides a gate fabrication method of a trench gate IGBT, the method comprising the following steps:

Step S1 : forming a P well region 15 as a channel region and an N well region 14 as a carrier injection region, and etching a trench 16 . Preferably, the P well region 15 and the N well region 14 may be formed first, and then the trench 16 is etched according to the depth of the bottom surface of the N well region 14 , and the bottom surface of the trench 16 is lower than the bottom surface of the N well region 14 . The depth _d2 of the bottom surface of the N well region 14 is 1.5 μm-5 μm, preferably 2.5 μm in this embodiment. The depth d ₁ of the etched bottom surface of the trench 16 is 2 μm-6 μm, preferably 3.5 μm in this embodiment. The starting reference for each depth is the same in this embodiment.

Step S2: performing a primary oxidation by a thermal oxidation process to form a thick oxide layer 112 in the trench 16, and also form a thick oxide layer 112 on the top of the bulk material. The thickness of the thick oxide layer 112 is 100nm-300nm, preferably 200nm .

Step S3: removing the unnecessary thick oxide layer 112 .

Specific steps include:

Step S301: fill the trench 16 with photoresist 17, arrange the photoresist 17 on the upper surface of the thick oxide layer 112, the thickness of the photoresist above the upper surface of the thick oxide layer 112 is 0.5 μm-2 μm, this Examples are preferably 1 μm.

Step S302: Exposing the front side of the photoresist 17, and precisely controlling the exposure depth of the photoresist 17 by controlling the exposure parameters. Specifically, how to control the exposure depth of the photoresist 17 by controlling the exposure parameters is common knowledge in the art, and will not be repeated here. Expand. Exposure depth refers to the depth of the bottom surface of the exposed photoresist 171. The bottom surface of the exposed photoresist 171 can be located near the bottom surface of the N well region 14, which can be slightly higher than the bottom surface of the N well region 14, and can be higher than the bottom surface of the N well region 14. The bottom surface of the well region 14 is slightly lower, and may also be flush with the bottom surface of the N well region, for example, the exposure depth is 2.5 μm. The bottom surface of the exposed photoresist 171 is slightly higher than the bottom surface of the N well region 14, which is more conducive to controlling the final etching position of the thick oxide layer 112 by means of over-etching, that is, the upper surface of the thick oxide layer 112 is relative to the N well region. The position of the bottom surface of the well region 14 , the position of the upper surface of the thick oxide layer 112 is the position of the bottom surface of the thin oxide layer 111 .

Step S303: removing the exposed photoresist 171 by developing.

Step S304 : the remaining photoresist 172 is not exposed, and the entire surface of the thick oxide layer 112 is wet-etched using the remaining photoresist 172 as a mask, so as to remove the unnecessary thick oxide layer 112 . Specifically, the thick oxide layer 112 at the top of the bulk material and the thick oxide layer 112 at the top inside the trench are removed. The thick oxide layer 112 is etched by overetching and the overetching amount of the thick oxide layer 112 is controlled by the etching time. Overetching is to etch the thick oxide layer 112 to its upper surface and the remaining unexposed Continue to etch the thick oxide layer 112 after the upper surface of the photoresist 172 is flush, and finally the upper surface of the etched thick oxide layer 112 is slightly lower than the bottom surface of the N well region 14, for example, the upper surface of the thick oxide layer 112 The depth of the surface is 2.8 μm.

Step S305 : removing the remaining photoresist 172 in the trench 16 .

After step S3 is completed, perform step S4: secondary oxidation, forming a thin oxide layer 111 above the thick oxide layer 112, the thickness of the thin oxide layer is 50nm-150nm, preferably 100nm;

Step S5: Deposit polysilicon 12 on the upper surface of the thin oxide layer 111 and in the trench 16, so that the polysilicon 12 fills the trench, etch the entire surface of the polysilicon 12, so that the upper surface of the polysilicon 12 is slightly lower than the upper surface of the thin oxide layer , thereby forming a gate body composed of polysilicon 12 .

In this embodiment, the bulk material for forming the trench gate IGBT may be one of Si, SiC or GaN, and each well region is formed by doping on the basis of the bulk material. The material of the gate body is not limited to polysilicon, and other materials for making the gate body in the prior art can also be applied to the present invention.

Embodiment two:

The N well region 14 only serves to increase the carrier injection level, and removing the N well region 14 does not affect the basic functions of the trench gate IGBT. The trench gate IGBT provided in this embodiment does not have a carrier injection region, that is, the N well region 14 is removed. When making the gate of the trench gate IGBT device, the N well region 14 is no longer formed in step S1, and the bottom surface of the trench 16 is lower than the bottom surface of the P well region 15; in step S302, the exposed photoresist 171 The bottom surface of the P well region 15 is located near the bottom surface of the P well region 15, and may be slightly higher or lower than the bottom surface of the P well region 15 or even. In step S304 , the upper surface of the finally etched thick oxide layer 112 is slightly lower than the bottom surface of the P-well region 15 . All the other are the same as the first embodiment.

The trench gate IGBT in the above two embodiments is an N channel, and the present invention is applicable to any trench gate MOS power devices such as a P channel trench gate IGBT and VDMOS (vertical double diffused metal-oxide semiconductor) .

In other embodiments, the gate oxide layer corresponding to the region above the channel region may be a thin oxide layer or a thick oxide layer, which is not limited in the present invention. For the gate oxide layer corresponding to the region above the channel region where a thick oxide layer is formed, steps of etching the oxide layer and multiple oxidations may be added between step S4 and step S5.

In other embodiments, the channel region may be provided only on one side of the trench, and no channel region shall be provided on the other side of the trench, and the gate oxide layer on the side without the channel region may be all thick oxide layers.

Although the present invention has been described with reference to preferred embodiments, various modifications can be made thereto and some or all of the technical features can be equivalently substituted without departing from the scope of the present invention. In particular, as long as there is no logical or structural conflict, the technical features mentioned in the various embodiments can be combined in any manner. The present invention is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims (9)

1. The method for manufacturing the grid of the trench gate MOS power device is characterized by comprising the following steps of:

step S1: forming a channel region, a trench, and a carrier injection region, the carrier injection region disposed below and immediately adjacent to the channel region, the channel region having an opposite polarity to the carrier injection region;

step S2: performing primary oxidation, and forming a thick oxide layer in the groove;

step S3: removing the unnecessary thick oxide layer; the method comprises the following substeps:

s301: filling photoresist in the groove, and arranging the photoresist on the upper surface of the thick oxide layer;

s302: exposing the photoresist and controlling the exposure depth of the photoresist; the bottom surface of the exposed photoresist is close to and higher than the bottom surface of the carrier injection region;

s303: removing the exposed photoresist;

s304: etching the thick oxide layer by taking the residual photoresist as a mask;

s305: removing the residual photoresist in the groove;

step S4: secondary oxidation, forming a thin oxide layer above the thick oxide layer; the bottom surface of the thin oxide layer is lower than the bottom surface of the carrier injection region, and the top surface of the thin oxide layer is higher than the top surface of the channel region;

step S5: a gate body is formed.

2. The method according to claim 1, wherein in the step S3, the final etching position of the thick oxide layer is controlled using photoresist as a mask.

3. The method according to claim 2, wherein in the step S2, the thick oxide layer is formed on top of the gate body material.

4. A gate fabrication method according to any one of claims 1 to 3, wherein in the step S302, a bottom surface of the exposed photoresist is close to and higher than a bottom surface of the channel region.

5. A gate fabrication method according to any one of claims 1 to 3, wherein in step S304, the thick oxide layer is etched by means of over-etching.

6. The method according to claim 5, wherein in step S304, the over etching amount of the thick oxide layer is controlled by etching time.

7. A method of fabricating a gate electrode according to any one of claims 1 to 3, wherein in step S5 polysilicon is deposited in the trench and on the upper surface of the gate oxide layer such that the trench is filled with polysilicon, and then the polysilicon is etched such that the upper surface of the polysilicon is below the upper surface of the thin oxide layer.

8. A trench gate MOS power device fabricated by the method of any of claims 1 to 7, comprising a channel region, wherein the gate oxide layer corresponding to the channel region is a thin oxide layer, and the gate oxide layer below the thin oxide layer is a thick oxide layer.

9. The trench-gate MOS power device of claim 8, wherein a carrier injection region is disposed below the channel region and immediately adjacent to the channel region, and wherein a gate oxide layer corresponding to the carrier injection region is the thin oxide layer.