CN111384005A - Microelectronic package, flip-chip process and application thereof, and microelectronic device - Google Patents
Microelectronic package, flip-chip process and application thereof, and microelectronic device Download PDFInfo
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- CN111384005A CN111384005A CN202010210354.4A CN202010210354A CN111384005A CN 111384005 A CN111384005 A CN 111384005A CN 202010210354 A CN202010210354 A CN 202010210354A CN 111384005 A CN111384005 A CN 111384005A
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- 238000004377 microelectronic Methods 0.000 title claims abstract description 60
- 238000000034 method Methods 0.000 title claims abstract description 41
- 230000008569 process Effects 0.000 title claims abstract description 41
- 239000000853 adhesive Substances 0.000 claims abstract description 91
- 230000001070 adhesive effect Effects 0.000 claims abstract description 91
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 238000004806 packaging method and process Methods 0.000 claims abstract description 32
- 238000003825 pressing Methods 0.000 claims abstract description 10
- 239000011248 coating agent Substances 0.000 claims abstract description 9
- 238000000576 coating method Methods 0.000 claims abstract description 9
- 239000012790 adhesive layer Substances 0.000 claims description 30
- 229910000679 solder Inorganic materials 0.000 claims description 22
- 239000003292 glue Substances 0.000 claims description 16
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 230000004907 flux Effects 0.000 description 11
- 238000005476 soldering Methods 0.000 description 11
- 150000002500 ions Chemical class 0.000 description 10
- 239000002245 particle Substances 0.000 description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 238000004140 cleaning Methods 0.000 description 4
- 238000002844 melting Methods 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000005012 migration Effects 0.000 description 3
- 238000013508 migration Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 230000002950 deficient Effects 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000009974 thixotropic effect Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/111—Manufacture and pre-treatment of the bump connector preform
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
The invention relates to the field of chip packaging, and particularly provides a microelectronic packaging body, a flip-chip process, application of the microelectronic packaging body and a microelectronic device. The flip-chip process of the microelectronic package comprises the following steps: (a) providing a substrate provided with conductive blocks; (b) sequentially coating conductive adhesive and non-conductive adhesive on the surface of the conductive block; (c) and pressing the chip provided with the bumps and the substrate, and then curing to obtain the microelectronic packaging body. The process adopts the cooperation of the conductive adhesive and the non-conductive adhesive, and has the advantages of simple process, high packaging efficiency, stable and reliable chip function, difficult warpage and deformation of the packaging body and long service life.
Description
Technical Field
The invention relates to the field of chip packaging, in particular to a microelectronic packaging body, a flip-chip process, application of the microelectronic packaging body and a microelectronic device.
Background
The flip chip packaging process is a packaging technology for improving the packaging speed and the component reliability, and the traditional soldering paste flip chip assembly process flow comprises the following steps: flux coating, chip placement, solder paste reflow and underfill, etc., the primary design considerations include solder bumps and under bump structures, the solder bumps serving as mechanical, electrical and sometimes thermal interconnections between the IC and the circuit board.
The existing flip-chip process has the following defects: firstly, in the process of flip-chip mounting, when the soldering flux (such as solder balls) or the bumps are excessive, the bottom needs to be filled with glue with fine particles, and then plastic packaging is carried out, so that the soldering flux or the bumps are easy to be not contacted with the bottom conductive blocks, and are solidified singly, and the efficiency is low. Secondly, the flux needs to be cleaned before the underfill, and if the flux is not cleaned, gaps or holes are formed, so that the flux is easy to lose effectiveness directly when the flux is used for mounting a substrate. In addition, during the underfill process, the filler is required to have no wire gap, and even if the nano-scale layering occurs, ion migration occurs, so that the electrical loss is excessive, the model distortion is caused, and even the function failure is caused. Furthermore, the reflow temperature generally exceeds 250 ℃, the temperature is high, the requirement on the mechanical performance of an unprotected chip is high, the internal tin bumps are also re-melted when the product is finally mounted on a board, and if the tin is not fully melted during packaging, the tin is re-distributed, a circuit can be disconnected, and the electrical performance of the chip is seriously affected. In addition, the conventional tin is adopted for conducting electricity, the temperature is high, special material requirements are required for a substrate and a chip, different materials in packaging can generate different warps at different temperatures, the warping degree of the whole material needs to be matched in design, the whole warping degree is reduced, the height of the inverted bump is generally 10-50 micrometers, and the height of a tin paste coating on the bump is 10-50 micrometers, so that the inverted bump is particularly sensitive to the deformation of the materials.
In view of the above, the present invention is particularly proposed.
Disclosure of Invention
The first objective of the present invention is to provide a microelectronic package, in which a conductive adhesive layer is used to electrically connect a substrate and a chip, so as to change the traditional structure of using a solder bump to electrically connect a substrate and a chip, and the microelectronic package has a novel structure, high bonding strength between a chip and a substrate, and stable and reliable functions, and conductive ions in the conductive adhesive layer are not easy to migrate.
The second purpose of the invention is to provide a flip-chip process of a microelectronic package, which adopts the cooperation of conductive adhesive and non-conductive adhesive, and has the advantages of simple process, high packaging efficiency, stable and reliable chip function, difficult warpage and deformation of the package and long service life.
A third object of the present invention is to provide an application of the microelectronic package.
It is a fourth object of the invention to provide a microelectronic device.
In order to achieve the above purpose of the present invention, the following technical solutions are adopted:
in a first aspect, the present invention provides a microelectronic package, which includes a substrate and a chip, wherein a conductive block is disposed on the substrate, a conductive adhesive layer and a non-conductive adhesive layer are sequentially disposed on a surface of the conductive block, a bump is disposed on the chip, and the bump is pressed on the conductive block.
As a further preferable technical solution, the substrate is further provided with solder mask ink, and the solder mask ink is disposed on the periphery of the conductive block.
As a further preferable technical solution, the height of the solder resist ink is greater than the height of the conductive block.
As a further preferred technical solution, the conductive block is provided with a groove, and an opening of the groove faces the chip.
In a second aspect, the present invention provides a flip-chip process of the microelectronic package, including the following steps:
(a) providing a substrate provided with conductive blocks;
(b) sequentially coating conductive adhesive and non-conductive adhesive on the surface of the conductive block;
(c) and pressing the chip provided with the bumps and the substrate, and then curing to obtain the microelectronic packaging body.
As a further preferable technical scheme, the volume resistance of the conductive adhesive is lower than 0.05 omega/cm.
In a more preferable embodiment, the height of the conductive paste is 1/4-2/3.
As a further preferable technical scheme, the Ti values of the conductive adhesive and the non-conductive adhesive are not less than 3 and not more than 6;
preferably, the Ti value of the non-conductive glue is higher than that of the conductive glue;
preferably, the conductive paste comprises conductive silver paste;
preferably, the pressure for pressing in the step (c) is 0.5-10N;
preferably, the curing temperature in step (c) is 150 ℃ and 180 ℃, and the curing time is 15-120 min.
In a third aspect, the invention provides an application of the microelectronic package or the microelectronic package obtained by the flip-chip process in the preparation of a microelectronic device.
In a fourth aspect, the present invention provides a microelectronic device comprising the above microelectronic package or a microelectronic package obtained by the above flip-chip process.
Compared with the prior art, the invention has the beneficial effects that:
the microelectronic packaging body provided by the invention is pressed above the conductive blocks through the bumps, and the bumps are connected with the conductive blocks through the conductive adhesive layer, so that the substrate is electrically connected with the chip. The packaging body adopts the conductive adhesive layer to electrically connect the substrate and the chip, changes the traditional structure of adopting a tin block to electrically connect the substrate and the chip, has novel structure, high bonding strength between the chip and the substrate, difficult migration of conductive ions in the conductive adhesive layer and stable and reliable functions of the chip; the bumps are pressed above the conductive blocks, reflow soldering is not needed, the problems of warping deformation and the like caused by mismatching of thermal expansion coefficients of the chip and the base material due to high temperature are avoided, and the service life is long; the deformation of the conductive adhesive layer and the non-conductive adhesive layer is small, and the thickness of the packaging body is small.
In the flip-chip process provided by the invention, the substrate is provided with the conductive block which has conductivity, so that the substrate is electrically connected with the chip. The conductive adhesive has conductivity, and the conductive adhesive coated on the surface of the conductive block can ensure that the glue has conductivity after being cured, so that the bump of the chip is electrically connected with the conductive block of the substrate. The non-conductive adhesive has no conductivity, can isolate ions which are easy to migrate in the conductive adhesive, and provides adhesive force together with the conductive adhesive and the non-conductive adhesive to bond the substrate and the chip. And curing the chip and the substrate after pressing to complete the packaging of the chip.
The process has the following advantages:
(1) the conductive adhesive is matched with the non-conductive adhesive, the conductive adhesive is electrically connected with the protrusions and the conductive blocks, the non-conductive adhesive isolates the conductive medium, and bonding strength of the chip and the substrate is improved.
(2) The process does not use soldering flux, so that the step of cleaning the soldering flux is not needed, the process is simpler, and the risk of chip failure caused by unclean cleaning can not be generated. And the subsequent glue sealing process is not needed, and the plastic sealing can be directly carried out or not.
(3) The main non-conductive component playing a role in bonding in the conductive adhesive has a low proportion, the conductivity of the conductive adhesive cannot be influenced, but conductive ions easy to migrate in the adhesive can be effectively isolated, and the ions can be prevented from migrating without using too much non-conductive adhesive, so that the electric loss is avoided, and the function of the chip is prevented from losing efficacy.
(4) The conductive adhesive and the non-conductive adhesive are cured at one time, reflow soldering is not needed, secondary melting is avoided when the conductive adhesive and the non-conductive adhesive are finally mounted on a board, and the situation of re-melting disconnection is avoided (a good product is obtained when a single product is tested for electrical property, and a defective product is possibly obtained after the conductive adhesive and the non-conductive adhesive are mounted on the board).
(5) The flip-chip electrical connection with lower temperature can be realized by utilizing the conductive adhesive electrical connection, the temperature is lower than the deformation transition temperature (160-.
(6) The deformation of the conductive adhesive and the non-conductive adhesive is small, so that a flexible space does not need to be reserved for deformation of the substrate, and the substrate can be thinner, so that the thickness of the whole packaging body is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a microelectronic package according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of step (a) of a flip-chip process according to one embodiment of the present invention;
FIG. 3 is a schematic diagram of step (b) of a flip-chip process according to one embodiment of the present invention;
fig. 4 is a schematic diagram of step (c) of the flip-chip process according to an embodiment of the present invention.
Icon: 1-a substrate; 101-a conductive block; 1011-groove; 102-solder mask ink; 103-a conductive adhesive layer; 1031-conductive adhesive; 104-a non-conductive glue layer; 1041-a non-conductive glue; 2-chip; 201-bump.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to examples, but it will be understood by those skilled in the art that the following examples are only illustrative of the present invention and should not be construed as limiting the scope of the present invention. The examples, in which specific conditions are not specified, were conducted under conventional conditions or conditions recommended by the manufacturer.
According to an aspect of the present invention, there is provided a microelectronic package, as shown in fig. 1, including a substrate 1 and a chip 2, wherein a conductive block 101 is disposed on the substrate 1, a conductive adhesive layer 103 and a non-conductive adhesive layer 104 are sequentially disposed on a surface of the conductive block 101, a bump 201 is disposed on the chip 2, and the bump 201 is pressed on the conductive block 101.
The microelectronic packaging body is pressed above the conductive blocks through the bumps, and the conductive adhesive layer enables the bumps and the conductive blocks to be connected, so that the substrate is electrically connected with the chip. The packaging body adopts the conductive adhesive layer to electrically connect the substrate and the chip, changes the traditional structure of adopting a tin block to electrically connect the substrate and the chip, has novel structure, high bonding strength between the chip and the substrate, difficult migration of conductive ions in the conductive adhesive layer and stable and reliable functions of the chip; the bumps are pressed above the conductive blocks, reflow soldering is not needed, the problems of warping deformation and the like caused by mismatching of thermal expansion coefficients of the chip and the base material due to high temperature are avoided, and the service life is long; the deformation of the conductive adhesive layer and the non-conductive adhesive layer is small, and the thickness of the packaging body is small.
It should be noted that:
the conductive adhesive layer refers to a coating formed after the conductive adhesive is cured or dried, and the conductive adhesive refers to an adhesive with certain conductivity after being cured or dried.
The term "non-conductive adhesive" refers to a coating formed by curing or drying a non-conductive adhesive, and the term "non-conductive adhesive" refers to an adhesive that is not electrically conductive after curing or drying.
"press-fit" refers to a process that uses pressure to integrate two separate parts or assemblies.
The "surface of the conductive block" means all surfaces of the conductive block except for the surface directly contacting the substrate. The conductive adhesive layer and the non-conductive adhesive layer are sequentially arranged on the surface of the conductive block, namely the conductive adhesive layer and the non-conductive adhesive layer are sequentially arranged on the periphery of the surface of the conductive block, the conductive adhesive layer completely covers the surface of the conductive block, and the non-conductive adhesive layer completely covers the conductive adhesive layer.
In a preferred embodiment, solder mask ink 102 is further disposed on the substrate 1, and the solder mask ink 102 is disposed on the periphery of the conductive block 101. The solder mask ink is mainly used for preventing the problems of line oxidation on the chip, open circuit or short circuit of lines and the like, thereby realizing the packaging and protection of the chip lines.
Preferably, the height of the solder resist ink 102 is greater than the height of the conductive bumps 101.
The "height of the solder mask ink" refers to the vertical distance between the top end of the solder mask ink and the bottom end of the solder mask ink.
The "height of the conductive block" refers to the vertical distance between the top end of the conductive block and the bottom end of the conductive block.
The top end refers to the end with the largest vertical distance between the solder resist ink or the conductive block and the horizontal plane when the substrate is horizontally placed on the horizontal plane; conversely, the "bottom end" refers to the end of the substrate that has the smallest vertical distance from the horizontal for solder resist ink or conductive bumps when the substrate is laid flat on the horizontal.
In a preferred embodiment, the conductive block 101 is provided with a recess 1011, the recess 1011 opening towards the chip 2. When the conductive block is provided with the groove, more conductive adhesive can be contained in the groove, so that more conductive particles can be contained, and the conductive adhesive layer can be thinner by using the same amount of conductive adhesive, so that the whole thickness of the packaging body can be thinner.
Of course, the surface of the conductive block may be flat without grooves. When the surface of the conductive block is not provided with the groove, under the condition that the conductive adhesive layer is very thin, conductive particles in the conductive adhesive are more easily extruded to the side surface, the amount of the conductive particles left between the conductive block and the bump is less, and the electric connection effect between the conductive block and the bump is slightly poor. As mentioned in the above paragraphs, when the conductive block is provided with the groove, the amount of the conductive particles remaining between the conductive block and the bump is increased, which is not only beneficial to maintaining better electrical connection between the conductive block and the bump, but also reduces the thickness of the conductive adhesive layer.
Fig. 1 is a schematic structural diagram of a microelectronic package with a typical structure according to the present invention, and it can be seen from the diagram that the amount of the non-conductive adhesive is large enough to sufficiently bond the chip and the bottom plate without a subsequent process such as plastic encapsulation. Obviously, the microelectronic package may have another structure, in which the non-conductive adhesive is also present in a space surrounded by the solder resist ink after being cured, the space includes the conductive block, the conductive adhesive, and the non-conductive adhesive, and at this time, the package needs subsequent processes such as plastic encapsulation.
According to an aspect of the present invention, there is provided a flip-chip process of the above-mentioned microelectronic package, as shown in fig. 2 to 4, comprising the steps of:
(a) providing a substrate 1 provided with conductive bumps 101;
(b) coating conductive adhesive 1031 and non-conductive adhesive 1041 on the surface of the conductive block 101 in sequence;
(c) and pressing the chip 2 provided with the bump 201 and the substrate 1, and then curing to obtain the microelectronic package.
In the flip-chip process, the substrate is provided with the conductive blocks, and the conductive blocks have conductivity so as to realize the electrical connection between the substrate and the chip. The conductive adhesive has conductivity, and the conductive adhesive coated on the surface of the conductive block can ensure that the glue has conductivity after being cured, so that the bump of the chip is electrically connected with the conductive block of the substrate. The non-conductive adhesive has no conductivity, can isolate ions which are easy to migrate in the conductive adhesive, and provides adhesive force together with the conductive adhesive and the non-conductive adhesive to bond the substrate and the chip. And curing the chip and the substrate after pressing to complete the packaging of the chip. Typically, but not by way of limitation, a schematic diagram of a package is shown in fig. 1.
The process has the following advantages:
(1) the conductive adhesive is matched with the non-conductive adhesive, the conductive adhesive is electrically connected with the protrusions and the conductive blocks, the non-conductive adhesive isolates the conductive medium, and bonding strength of the chip and the substrate is improved.
(2) The process does not use soldering flux, so that the step of cleaning the soldering flux is not needed, the process is simpler, and the risk of chip failure caused by unclean cleaning can not be generated. And the subsequent glue sealing process is not needed, and the plastic sealing can be directly carried out or not.
(3) The main non-conductive component playing a role in bonding in the conductive adhesive has a low proportion, the conductivity of the conductive adhesive cannot be influenced, but conductive ions easy to migrate in the adhesive can be effectively isolated, and the ions can be prevented from migrating without using too much non-conductive adhesive, so that the electric loss is avoided, and the function of the chip is prevented from losing efficacy.
(4) The conductive adhesive and the non-conductive adhesive are cured at one time, reflow soldering is not needed, secondary melting is avoided when the conductive adhesive and the non-conductive adhesive are finally mounted on a board, and the situation of re-melting disconnection is avoided (a good product is obtained when a single product is tested for electrical property, and a defective product is possibly obtained after the conductive adhesive and the non-conductive adhesive are mounted on the board).
(5) The flip-chip electrical connection with lower temperature can be realized by utilizing the conductive adhesive electrical connection, the temperature is lower than the deformation transition temperature (160-.
(6) The deformation of the conductive adhesive and the non-conductive adhesive is small, so that a flexible space does not need to be reserved for deformation of the substrate, and the substrate can be thinner, so that the thickness of the whole packaging body is reduced.
In a preferred embodiment, the volume resistance of the conductive paste is less than 0.05 Ω/cm. The low volume resistance is beneficial to ensuring the conductivity of the cured conductive adhesive.
Preferably, the height of the conductive paste is 1/4-2/3 of the height of the conductive bumps. The height of the conductive adhesive is controlled, the lower limit of 1/4 is to ensure that the conductive particles in the conductive adhesive can have a sufficient ratio between the bumps of the chip and the conductive bumps of the substrate, and the upper limit of 2/3 is to prevent the conductive adhesive from contacting the surface of the chip to cause the diffusion of the conductive particles and affect the electrical property.
The "height of the conductive paste" refers to a vertical distance between the top end of the conductive paste and the top end of the conductive block.
The "height of the conductive block" refers to the vertical distance between the top end of the conductive block and the bottom end of the conductive block.
The "top end" refers to the end of the conductive adhesive or the conductive block with the largest vertical distance to the horizontal plane when the substrate is flatly placed on the horizontal plane; conversely, the "bottom end" refers to the end of the conductive bump that has the smallest vertical distance from the horizontal plane when the substrate is laid flat on the horizontal plane.
Alternatively, the conductive particles can be spherical, ellipsoidal, flaky or columnar, and the length of the conductive particles in the diameter direction is less than or equal to 0.3 micrometer.
In a preferred embodiment, the Ti values of the conductive and non-conductive pastes are not less than 3 and not more than 6. The Ti value is the thixotropic index, which means the ratio of the viscosity at low rotational speeds (6r/min) to the viscosity at high rotational speeds (60 r/min). For example, the conductive and non-conductive pastes each independently have a Ti value of 3, 3.5, 4, 4.5, 5, 5.5, or 6.
Preferably, the Ti value of the non-conductive paste is higher than the Ti value of the conductive paste. When the Ti value of the non-conductive adhesive is higher than that of the conductive adhesive, the thixotropy of the non-conductive adhesive is relatively higher, so that the non-conductive adhesive can diffuse to the periphery during pressing, the space around the conductive block is filled, the coverage of the non-conductive adhesive on the surface of the conductive adhesive is ensured, meanwhile, the non-conductive adhesive between the conductive adhesive and the bump is reduced as much as possible, and the electrical connection between the substrate and the chip is enhanced.
Preferably, the conductive paste comprises conductive silver paste.
Preferably, the pressure of the pressing in step (c) is 0.5-10N. The above pressure is typically, but not limited to, 0.5, 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10N.
Preferably, the curing temperature in step (c) is 150 ℃ and 180 ℃, and the curing time is 15-120 min. The above curing temperature is typically, but not limited to, 150, 155, 160, 165, 170, 175 or 180 ℃ and the curing time is typically, but not limited to, 15, 20, 25, 30, 35, 40, 50, 60, 70, 80, 90, 100, 110 or 120 min.
It should be noted that the protection of the welding spot can be finished by adopting the process, the plastic package can be directly carried out, and special bottom filling is not needed. If the glue coating amount is large, plastic package is not needed, electric connection and protection of the chip are completed, and if the chip is required to be filled with glue, the thickness of the non-conductive glue/the thickness of the conductive glue is larger than 1/4 in the height direction of the side wall of the chip bump, so that the conductive glue is ensured not to contact the surface of the chip.
According to another aspect of the present invention, there is provided a use of the above-described microelectronic package for the manufacture of a microelectronic device. The microelectronic packaging body is applied to the preparation of a microelectronic device, and has the advantages of simple preparation process, capability of effectively reducing the thickness of the device, stable and reliable function of the device, difficult deformation, long service life and the like.
According to another aspect of the invention, there is provided a microelectronic device comprising the microelectronic package described above. The microelectronic device comprises the microelectronic packaging body, so that the microelectronic device at least has the advantages of stable and reliable function, small thickness, difficulty in warping and deformation and long service life.
The microelectronic device is mainly a miniaturized electronic system chip and device realized by using a microelectronic process technology, and the microelectronic device can comprise one or more microelectronic packaging bodies, and the microelectronic packaging bodies are connected in series or in parallel or independently exist to form a microelectronic device whole together.
While particular embodiments of the present invention have been illustrated and described, it would be obvious that various other changes and modifications can be made without departing from the spirit and scope of the invention. It is therefore intended to cover in the appended claims all such changes and modifications that are within the scope of this invention.
Claims (10)
1. A microelectronic package is characterized by comprising a substrate and a chip, wherein conductive blocks are arranged on the substrate, a conductive adhesive layer and a non-conductive adhesive layer are sequentially arranged on the surfaces of the conductive blocks, and bumps are arranged on the chip and are pressed above the conductive blocks.
2. The microelectronic package according to claim 1, wherein said substrate further has solder mask ink disposed thereon, said solder mask ink being disposed on the periphery of said conductive bumps.
3. The microelectronic package of claim 2, wherein a height of the solder mask ink is greater than a height of the conductive bumps.
4. The microelectronic package according to any of claims 1 to 3, characterized in that said conductive blocks are provided with recesses, the openings of the recesses facing the chip.
5. The flip-chip process of the microelectronic package according to any of claims 1 to 4, comprising the steps of:
(a) providing a substrate provided with conductive blocks;
(b) sequentially coating conductive adhesive and non-conductive adhesive on the surface of the conductive block;
(c) and pressing the chip provided with the bumps and the substrate, and then curing to obtain the microelectronic packaging body.
6. The flip-chip process according to claim 5, wherein the volume resistance of the conductive paste is less than 0.05 Ω/cm.
7. The flip-chip process of claim 5, wherein the height of the conductive paste is 1/4-2/3 of the height of the conductive bumps.
8. The flip-chip process according to any one of claims 5 to 7, wherein the Ti values of the conductive and non-conductive pastes are not lower than 3 and not higher than 6;
preferably, the Ti value of the non-conductive glue is higher than that of the conductive glue;
preferably, the conductive paste comprises conductive silver paste;
preferably, the pressure for pressing in the step (c) is 0.5-10N;
preferably, the curing temperature in step (c) is 150 ℃ and 180 ℃, and the curing time is 15-120 min.
9. Use of a microelectronic package according to any of claims 1 to 4 or obtained by a flip-chip process according to any of claims 5 to 8 for the production of a microelectronic device.
10. A microelectronic device comprising the microelectronic package according to any of the claims 1 to 4 or a microelectronic package obtained by a flip-chip process according to any of the claims 5 to 8.
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| CN113161242A (en) * | 2021-02-23 | 2021-07-23 | 青岛歌尔微电子研究院有限公司 | Chip packaging process |
| CN115472576A (en) * | 2022-08-31 | 2022-12-13 | 珠海格力电器股份有限公司 | chip structure |
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| CN111384005B (en) | 2022-03-04 |
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