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JP2001307555A - Anisotropic conductive film, its assembly method, and circuit board using the same - Google Patents

Anisotropic conductive film, its assembly method, and circuit board using the same

Info

Publication number
JP2001307555A
JP2001307555A JP2000115250A JP2000115250A JP2001307555A JP 2001307555 A JP2001307555 A JP 2001307555A JP 2000115250 A JP2000115250 A JP 2000115250A JP 2000115250 A JP2000115250 A JP 2000115250A JP 2001307555 A JP2001307555 A JP 2001307555A
Authority
JP
Japan
Prior art keywords
filler
film
film layer
anisotropic conductive
conductive particles
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000115250A
Other languages
Japanese (ja)
Inventor
Yasuharu Nakamura
康春 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP2000115250A priority Critical patent/JP2001307555A/en
Publication of JP2001307555A publication Critical patent/JP2001307555A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
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    • H01L2224/73201—Location after the connecting process on the same surface
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    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
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Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
  • Non-Insulated Conductors (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide an anisotropic conductive film which is free from connection failures due to filler inclusion to prevent thermal expansion, and an assembly method using it. SOLUTION: (1) An anisotropic conductive film 11 laminatedly made of a film layer 1 in which an insulative filer 3 is included and a film layer 2 in which no filler is included, containing conductive particles in both layers. (2)An anisotropic conductive film laminatedly made of a film layer in which an insulative filler is included without conductive particles and a film layer in which no filer is included with conductive particles. (3) In an assembly of semiconductor chips onto a circuit board, (1) or (2) is used so that (1) or (2) is sandwitched in between a semiconductor chip and the circuit board in the position that the circuit board faces the layer in which no filler is included. (4)A circuit board on which (1) or (2) is arranged in the position that the circuit board faces the layer in which no filler is included.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、異方性導電フィル
ム及びこれを用いた実装方法、ならびに配線用の基板に
関する。本発明はたとえば、電子機器の実装の際に、好
ましく適用することができる。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an anisotropic conductive film, a mounting method using the same, and a wiring substrate. The present invention can be preferably applied, for example, when mounting an electronic device.

【０００２】[0002]

【従来の技術】従来より電子機器等の分野で、小型化・
高密度化等の要求が大きく、これに伴い数々の技術が提
案されている。たとえば、電子機器のデジタル化及び信
号の高速化といったシステムの変化等に伴い、近年では
ノイズの減少や機器の小型化の要請により、半導体チッ
プの実装手段として、フリップチップ実装等のベアチッ
プ実装技術が用いられるようになっている。2. Description of the Related Art Conventionally, miniaturization and
There is a great demand for high density and the like, and along with this, various technologies have been proposed. For example, with the change of the system such as the digitization of electronic devices and the speeding up of signals, etc., in recent years, due to the demand for reduction of noise and miniaturization of devices, bare chip mounting technology such as flip chip mounting has been used as semiconductor chip mounting means. Is being used.

【０００３】従来よりフリップチップ実装技術として、
各種の接続手段が知られている。代表的には、半導体チ
ップの接続パッド上にはんだ、たとえば高融点はんだに
よるバンプを形成し、実装配線基板上にはんだプリコー
トを行って、両者をはんだ接続するはんだバンプ方式
や、半導体チップの接続パッド上に金（Ａｕ）ワイヤボ
ンディングを用いて金バンプ等を形成し、銀（Ａｇ）ペ
ーストなどの導電性ペーストをバンプ上に適量転写した
のち、直接、実装配線基板上にマウント接続する導電性
ペースト方式などがある。しかしこれらはんだバンプ方
式や導電性ペースト方式は、アンダーフィルム樹脂等の
充填硬化工程を要し、効率の点で問題がある。[0003] Conventionally, as flip chip mounting technology,
Various connection means are known. Typically, a solder bump is formed on a connection pad of a semiconductor chip, for example, a bump made of a high melting point solder, a solder precoat is performed on a mounting wiring board, and the two are connected by soldering. A conductive paste such as a gold (Au) wire bonding is used to form a gold bump or the like, and a conductive paste such as a silver (Ag) paste is transferred onto the bump in an appropriate amount, and then directly mounted on a mounting wiring board. There are methods. However, the solder bump method and the conductive paste method require a step of filling and curing an underfilm resin or the like, and have a problem in efficiency.

【０００４】他のフリップチップ実装接続技術として、
半導体チップの接続パッド上に金（Ａｕ）ワイヤボンデ
ィングを用いて金バンプ等を形成し、光硬化性樹脂を接
続媒体として半導体チップと配線基板とを圧接すること
により当該光硬化性樹脂の硬化収縮作用に基づいて電気
的接続を確保するＭＢＢ（Ｍｉｃｒｏ−Ｂｕｍｐ−Ｂｏ
ｎｄｉｎｇ）方式があり、これは別のアンダーフィルム
樹脂硬化工程は不要であるが、光硬化させるために光透
過性の基板を用いなければならないと言う材料上の制約
があり、汎用性に欠ける。As another flip chip mounting connection technology,
A gold bump or the like is formed on a connection pad of a semiconductor chip by using gold (Au) wire bonding, and the photocurable resin is press-contacted with the semiconductor chip and a wiring board by using the photocurable resin as a connection medium to cure and shrink the photocurable resin. MBB (Micro-Bump-Bo) that secures an electrical connection based on the action
Although there is no need for another under-film resin curing step, there is a material limitation that a light-transmissive substrate must be used for photo-curing, and thus lacks versatility.

【０００５】上記とは別のフリップチップ実装接続技術
として、異方性導電フィルム（ＡＣＦ，Ａｎｉｓｏｔｒ
ｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ）を接続媒
体とする技術が知られている。この異方性導電フィルム
を接続媒体とする実装技術は、上記した他のフリップチ
ップ実装技術と異なり、アンダーフィルム樹脂等の充填
硬化工程が不要であり非常に効率が良く、しかも特に透
明基板を用いる必要もなくて制約が小さく汎用性に富
む。なお異方性導電フィルムとは、方向によって導電性
が異なるフィルムを言い、特開平１１−１９５３２５号
公報などに記載がある。実装技術に用いる異方性導電フ
ィルムは、接続方向に導電性を有し、それ以外の方向で
は導電性を有さないものであり、半導体チップの実装構
造に異方性導電フィルムを用いる提案例として、たとえ
ば特開平１１−１６３０５１号公報に記載のものがあ
る。As another flip-chip mounting connection technology, anisotropic conductive films (ACF, Anisotr) are used.
A technology using an optical conductive film as a connection medium is known. The mounting technology using this anisotropic conductive film as a connection medium is different from the other flip-chip mounting technologies described above, and does not require a step of filling and curing an under film resin or the like, is very efficient, and particularly uses a transparent substrate. There is no need and there are few restrictions and it is versatile. Note that an anisotropic conductive film refers to a film having different conductivity depending on the direction, and is described in JP-A-11-195325 and the like. The anisotropic conductive film used for mounting technology has conductivity in the connection direction and does not have conductivity in other directions. For example, there is one described in JP-A-11-163051.

【０００６】接続媒体として特に異方性導電フィルムを
用いるフリップチップ実装の構成の一例を、図５に示
す。図５の例示においては、半導体チップ５側のワイヤ
バンプ７と、配線基板９側のランド１０とが、異方性導
電フィルム１１によって接続され、プリント回路基板８
を構成する。詳しくは、このプリント回路基板８におい
ては、半導体チップ５の回路面５Ａに複数のたとえばア
ルミニウム（Ａｌ）でなる接続パッド６が所定パターン
で形成され、当該接続パッド６に対してそれぞれたとえ
ば金（Ａｕ）等でなるワイヤバンプ７が形成されてい
る。また、たとえばガラスエポキシ樹脂でなる配線基板
９の基板面９Ａには複数のランド１０が所定パターンで
形成され、当該ランド１０を覆うように異方性導電フィ
ルム１１が貼り付けられている。この異方性導電フィル
ム１１は、所定の厚みを有し、内部に複数の導電粒子４
が分散して混入された構成をとる。またこの異方性導電
フィルム１１は、内部に導電粒子４が分散されるととも
に、絶縁性のフィラー３が充填されている。これら導電
粒子４及び絶縁性のフィラー３は、模式的に各図に示し
ている。FIG. 5 shows an example of a configuration of flip-chip mounting using an anisotropic conductive film as a connection medium. In the example of FIG. 5, the wire bumps 7 on the semiconductor chip 5 side and the lands 10 on the wiring board 9 side are connected by an anisotropic conductive film 11, and the printed circuit board 8
Is configured. More specifically, in the printed circuit board 8, a plurality of connection pads 6 made of, for example, aluminum (Al) are formed in a predetermined pattern on the circuit surface 5A of the semiconductor chip 5, and each of the connection pads 6 is made of, for example, gold (Au). ) Etc. are formed. A plurality of lands 10 are formed in a predetermined pattern on a substrate surface 9A of a wiring substrate 9 made of, for example, a glass epoxy resin, and an anisotropic conductive film 11 is attached so as to cover the lands 10. The anisotropic conductive film 11 has a predetermined thickness and includes a plurality of conductive particles 4 therein.
Are dispersed and mixed. The anisotropic conductive film 11 has conductive particles 4 dispersed therein and an insulating filler 3 filled therein. These conductive particles 4 and insulating filler 3 are schematically shown in each figure.

【０００７】この配線基板９を実装基体とするフリップ
チップ実装工程を、図６（ａ）〜（ｃ）に示す。まず配
線基板９の基板面９Ａに所定パターンで形成された複数
のランド１０（図６（ａ））を覆うように、異方性導電
フィルム１１を貼り付ける（図６（ｂ））。FIGS. 6A to 6C show a flip chip mounting process using the wiring substrate 9 as a mounting base. First, the anisotropic conductive film 11 is attached so as to cover a plurality of lands 10 (FIG. 6A) formed in a predetermined pattern on the substrate surface 9A of the wiring substrate 9 (FIG. 6B).

【０００８】続いて半導体チップ５を配線基板９に実装
するため、まず半導体チップ５の回路面５Ａを配線基板
９の基板面９Ａに対向させた後、各々の金（Ａｕ）ワイ
ヤバンプ７を当該基板面９Ａに形成された各ランド１０
に対向させて位置合わせする。この状態において、熱圧
着を行う。たとえば上記位置合わせした状態において、
１６０〜２４０℃、５〜４０ｓｅｃ．、及び１バンプ当
たりの圧力５〜１００ｇで熱圧着することにより、半導
体チップ５と配線基板９との間に異方性導電フィルム１
１が充填され、この結果、半導体チップ５は簡単に配線
基板９の基板面９Ａにフリップチップ実装される。実装
後の状態を図６（ｃ）に示す。Subsequently, in order to mount the semiconductor chip 5 on the wiring board 9, first, the circuit surface 5A of the semiconductor chip 5 is opposed to the substrate surface 9A of the wiring board 9, and then each gold (Au) wire bump 7 is attached to the substrate. Each land 10 formed on the surface 9A
And position it. In this state, thermocompression bonding is performed. For example, in the above-mentioned alignment state,
160-240 ° C, 5-40 sec. And an anisotropic conductive film 1 between the semiconductor chip 5 and the wiring board 9 by thermocompression bonding at a pressure of 5 to 100 g per bump.
1 is filled, and as a result, the semiconductor chip 5 is easily flip-chip mounted on the substrate surface 9A of the wiring substrate 9. The state after mounting is shown in FIG.

【０００９】以上説明したようなフリップチップ実装に
用いられる異方性導電フィルムには、一般に絶縁性のフ
ィラーが、ある一定量充填されている。これは、熱膨張
率の差に基づく問題を避けるため、フィルム自体の熱膨
張を制御するためである。すなわちたとえば異方性導電
フィルムの主成分が高熱膨張率のエポキシ樹脂で形成さ
れていると、実装後の高温環境下で接続不良を起こし易
くなるので、フィルム自体の熱膨張を抑制する必要があ
る。このため、低熱膨張率のフィラーを充填することに
より、フィルム自体の熱膨張を抑えるようにする。この
ために使用できる絶縁性のフィラーとしては、好ましく
はたとえばシリカ等を挙げることができ、また、アルミ
ナ（アルミニウム酸化物）を挙げることができる。The anisotropic conductive film used for flip-chip mounting as described above is generally filled with a certain amount of insulating filler. This is to control the thermal expansion of the film itself in order to avoid problems due to differences in the coefficient of thermal expansion. That is, for example, if the main component of the anisotropic conductive film is formed of an epoxy resin having a high coefficient of thermal expansion, connection failure easily occurs in a high-temperature environment after mounting, and thus it is necessary to suppress the thermal expansion of the film itself. . For this reason, by filling a filler having a low thermal expansion coefficient, the thermal expansion of the film itself is suppressed. As the insulating filler that can be used for this purpose, preferably, for example, silica or the like can be used, and alumina (aluminum oxide) can be used.

【００１０】上記熱膨張率の差に基づく問題について、
図７に示す概念図を用いて説明すると、次のとおりであ
る。室温時（Ａ）においては、半導体チップ５（ＩＣチ
ップ等）側の金等のバンプ７は、配線基板９（ＰＷＢ）
側のランド１０と、異方性導電フィルム１１中の導電粒
子４（たとえばＮｉ粉等）により、接続される。ところ
が高温時（Ｂ）になると、異方性導電フィルム１１が高
熱膨張率である場合、図に矢印Ｉで示すように当該異方
性導電フィルム１１が接続方向にも膨張し、導電粒子４
のランド１０への接触がはずれ、ランド１０から離れて
接続不良となるおそれがある。また、配線基板９は矢印
ＩＩで示すように長手方向に熱膨張する傾向が大きく、
このためバンプ７とランド１０との位置がずれて、これ
も接続不良を起こすおそれをもたらし得る。Regarding the problem based on the difference in the coefficient of thermal expansion,
This will be described with reference to the conceptual diagram shown in FIG. At room temperature (A), the bumps 7 of gold or the like on the semiconductor chip 5 (IC chip or the like) side are connected to the wiring board 9 (PWB).
The lands 10 are connected by conductive particles 4 (for example, Ni powder or the like) in the anisotropic conductive film 11. However, when the temperature is high (B), when the anisotropic conductive film 11 has a high coefficient of thermal expansion, the anisotropic conductive film 11 also expands in the connection direction as shown by the arrow I in the figure, and
There is a possibility that the contact with the land 10 may be lost and the connection may be separated from the land 10 to cause a connection failure. Further, the wiring board 9 has a large tendency to thermally expand in the longitudinal direction as shown by the arrow II,
For this reason, the positions of the bumps 7 and the lands 10 are displaced, which may also cause a connection failure.

【００１１】一般に、絶縁性のフィラーは、異方性導電
フィルム中に３０〜５０重量％程度充填される。この範
囲未満であるとフィラー充填の効果が不十分であること
があり、またこの範囲を超えると、樹脂が硬くなりすぎ
る傾向が出て来る。たとえば異方性導電フィルムの主成
分がエポキシ樹脂であり、絶縁性のフィラーとしてシリ
カを充填する場合、上記のようにフィラーは３０〜５０
重量％充填するのが好ましい。Generally, the insulating filler is filled in the anisotropic conductive film in an amount of about 30 to 50% by weight. If it is less than this range, the effect of filler filling may be insufficient, and if it exceeds this range, the resin tends to be too hard. For example, when the main component of the anisotropic conductive film is an epoxy resin and silica is filled as an insulating filler, the filler is 30 to 50 as described above.
It is preferable to fill by weight%.

【００１２】しかし絶縁性のフィラーが異方性導電フィ
ルム中に含有されていると、フリップチップ実装の際
に、導電粒子と接続部との間にフィラーが挟まれるおそ
れがある。すなわち、たとえば金（Ａｕ）ワイヤバンプ
と導電粒子間、導電粒子と配線基板のランド間にフィラ
ーが挟まれるおそれがある。図８に模式的に示すよう
に、絶縁性のフィラー３と導電粒子４とを含有する異方
性導電フィルム１１を用いて半導体チップ５側の金等の
バンプ７と配線基板９側のランド１０とを接続しようと
すると（図８（ａ））、図８（ｂ）のようにバンプ７と
導電粒子４との間にフィラー３が挟まる可能性がある。
導電粒子４と配線基板９のランド１０との間にフィラー
が挟まれる可能性もある。これはフィラーが多く充填さ
れていると、その傾向が大きくなる。これによって、接
続不良のおそれが出るという問題点がある。特に配線基
板のランドがファインピッチである場合、影響が大き
い。However, if an insulating filler is contained in the anisotropic conductive film, the filler may be sandwiched between the conductive particles and the connecting portion during flip chip mounting. That is, for example, a filler may be interposed between a gold (Au) wire bump and a conductive particle and between a conductive particle and a land of a wiring board. As schematically shown in FIG. 8, a bump 7 made of gold or the like on the semiconductor chip 5 and a land 10 on the wiring board 9 are formed using an anisotropic conductive film 11 containing an insulating filler 3 and conductive particles 4. (FIG. 8A), the filler 3 may be interposed between the bump 7 and the conductive particles 4 as shown in FIG. 8B.
Fillers may be interposed between the conductive particles 4 and the lands 10 of the wiring board 9. This tendency is increased when a large amount of filler is filled. As a result, there is a problem that a connection failure may occur. In particular, when the land of the wiring board has a fine pitch, the influence is great.

【００１３】[0013]

【発明が解決しようとする課題】本発明は、前記したよ
うな問題点を解消し、絶縁性のフィラーを含有させて異
方性導電フィルムを用いる場合の熱膨張の問題を解決す
るとともに、絶縁性のフィラーを含有させた場合の上記
接続不良のおそれの問題を解決した異方性導電フィルム
を提供することを目的とし、またかかる異方性導電フィ
ルムを用いた実装方法、ならびに配線用の基板を提供す
ることを目的とする。SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems and solves the problem of thermal expansion when using an anisotropic conductive film containing an insulating filler. To provide an anisotropic conductive film that has solved the problem of the possibility of poor connection when a conductive filler is contained, and a mounting method using such an anisotropic conductive film, and a wiring board The purpose is to provide.

【００１４】[0014]

【課題を解決するための手段】本発明に係る異方性導電
フィルムは、少なくとも２層のフィルム層が積層され、
前記少なくとも２層のフィルム層のうちの一方のフィル
ム層には絶縁性を有するフィラーと導電性粒子とが含有
され、他方のフィルム層には前記導電性粒子が含有され
ていることを特徴とするものである。The anisotropic conductive film according to the present invention has at least two film layers laminated,
One of the at least two film layers contains an insulating filler and conductive particles, and the other film layer contains the conductive particles. Things.

【００１５】本発明に係る他の異方性導電フィルムは、
少なくとも２層のフィルム層が積層され、前記少なくと
も２層のフィルム層のうちの一方のフィルム層には絶縁
性を有するフィラーが含有され、他方のフィルム層には
導電性粒子が含有されていることを特徴とするものであ
る。Another anisotropic conductive film according to the present invention comprises:
At least two film layers are laminated, one of the at least two film layers contains an insulating filler, and the other film layer contains conductive particles. It is characterized by the following.

【００１６】本発明の異方性導電フィルムによれば、各
発明の前記した他方のフィルム層である導電性粒子が含
有されている層（絶縁性のフィラーを含有しないフィル
ム層）を、フィラーによる問題の生じやすい側に位置さ
せて用いることによって、フィラーが挟まることによる
問題を解決することができる。According to the anisotropic conductive film of the present invention, the other film layer of the present invention, which is a layer containing conductive particles (a film layer containing no insulating filler), is made of a filler. By using it on the side where a problem is likely to occur, it is possible to solve the problem caused by the filler being sandwiched.

【００１７】本発明に係る実装方法は、配線基板に半導
体チップを実装する実装方法であって、上記本発明に係
る各異方性導電フィルムを用い、かつ、配線基板と各発
明に係る前記他方のフィルム層である導電性粒子が含有
されている層とが対向する位置関係で前記異方性導電フ
ィルムを前記配線基板と前記半導体チップとの間に挟ん
で該異方性導電フィルムにより接続をとることを特徴と
するものである。A mounting method according to the present invention is a mounting method for mounting a semiconductor chip on a wiring board, wherein each of the anisotropic conductive films according to the present invention is used, and the wiring board and the other one according to each invention are used. The anisotropic conductive film is sandwiched between the wiring board and the semiconductor chip in a positional relationship in which the layer containing the conductive particles, which is a film layer, faces each other, and the connection is established by the anisotropic conductive film. It is characterized by taking.

【００１８】本発明の実装方法によれば、前記した他方
のフィルム層である導電性粒子が含有されている層（絶
縁性のフィラーを含有しないフィルム層）を、配線基板
の側に向けて配置して実装を行うので、フィラーによる
問題の生じやすい配線基板の側にはその問題は防がれ、
よって、フィラーが挟まることによる問題を解決するこ
とができる。According to the mounting method of the present invention, the layer containing the conductive particles (the film layer containing no insulating filler), which is the other film layer, is disposed facing the wiring board. Since the mounting is performed, the problem is prevented on the side of the wiring board where the problem due to the filler is likely to occur,
Therefore, the problem caused by the filler being sandwiched can be solved.

【００１９】本発明に係る配線用の基板は、配線基板の
実装面上に上記本発明に係る各異方性導電フィルムを配
し、かつ、配線基板と各発明に係る前記他方のフィルム
層である導電性粒子が含有されている層とが対向する位
置関係で前記異方性導電フィルムを前記配線基板に配す
ることを特徴とするものである。The wiring board according to the present invention comprises the above-described anisotropic conductive film according to the present invention disposed on the mounting surface of the wiring board, and the wiring board and the other film layer according to each invention. The anisotropic conductive film is disposed on the wiring substrate in a positional relationship in which a layer containing certain conductive particles is opposed to the layer.

【００２０】本発明の配線用の基板によれば、前記した
他方のフィルム層である導電性粒子が含有されている層
（絶縁性のフィラーを含有しないフィルム層）を、配線
基板の側に向けて配置して実装を行うことができ、フィ
ラーによる問題の生じやすい配線基板の側にはその問題
は防がれ、よって、フィラーが挟まることによる問題を
解決することができる。According to the wiring board of the present invention, the other film layer, which is a layer containing conductive particles (film layer containing no insulating filler), is directed toward the wiring board. Therefore, the problem can be prevented on the side of the wiring board where the problem due to the filler is likely to occur, so that the problem caused by the filler being sandwiched can be solved.

【００２１】なお、前掲の特開平１１−１６３０５１号
公報にには、半導体チップの実装構造に異方性導電フィ
ルムを用いることは記載されているが、該異方性導電フ
ィルムの構造については特に記述はなく、もちろん本発
明のごとき２層フィルムを備えることについての記述も
ない。The use of an anisotropic conductive film in the mounting structure of a semiconductor chip is described in the aforementioned Japanese Patent Application Laid-Open No. 11-163051, but the structure of the anisotropic conductive film is particularly limited. There is no description, and of course, no provision for having a two-layer film as in the present invention.

【００２２】[0022]

【発明の実施の形態】以下、本発明の実施の形態につい
てさらに説明し、また、その好ましい具体例を図面を参
照して説明する。なお当然のことではあるが、本発明は
図示実施の形態例に限定されるものではない。DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be further described below, and preferred specific examples will be described with reference to the drawings. Needless to say, the present invention is not limited to the illustrated embodiment.

【００２３】本発明においては、異方性導電フィルム
は、絶縁性のフィラーを含有するフィラー含有フィルム
層と、導電性粒子を含有する層（絶縁性のフィラーを含
有しない層。以下実施の形態の説明においてこれを「フ
ィラーフリーフィルム層」と称する。）とが積層されて
なる。本発明においては該両フィルム層の各々が導電粒
子を含有するか、あるいはフィラーフリーフィルム層の
みが導電粒子を含有する構成とする。In the present invention, the anisotropic conductive film includes a filler-containing film layer containing an insulating filler and a layer containing conductive particles (a layer containing no insulating filler. In the description, this is referred to as a “filler-free film layer”). In the present invention, each of the two film layers contains conductive particles, or only the filler-free film layer contains conductive particles.

【００２４】本発明において、フィラー含有フィルム層
は、熱膨張率制御に適合する量で絶縁性のフィラーを含
有することが好ましい。その最適値は、フィルムの材
料、絶縁性のフィラー、実装方法等により、定めること
ができる。一般には、従来技術にあって全層に絶縁性の
フィラーを含有させて場合に対比すれば、それに見合う
分でフィラー含有フィルム層に絶縁性のフィラーを含有
させればよい。In the present invention, the filler-containing film layer preferably contains an insulating filler in an amount suitable for controlling the coefficient of thermal expansion. The optimum value can be determined depending on the material of the film, the insulating filler, the mounting method, and the like. Generally, when compared with the prior art in which an insulating filler is contained in all layers, the filler-containing film layer may contain an insulating filler in an amount corresponding thereto.

【００２５】本発明において、フィラー含有フィルム層
と、前記フィラーフリーフィルム層とは、同じ樹脂成分
からなることが好ましい。樹脂成分としてはエポキシ樹
脂を採用できるが、これに限られるものではない。絶縁
性のフィラーとしては、シリカを採用できるが、これも
シリカに限られるものではなく、たとえばアルミナ等、
適宜のものを用いてよい。In the present invention, the filler-containing film layer and the filler-free film layer are preferably made of the same resin component. An epoxy resin can be used as the resin component, but is not limited to this. As the insulating filler, silica can be employed, but this is not limited to silica, and for example, alumina, etc.
Any appropriate one may be used.

【００２６】以下、図面を参照して、本発明の好ましい
具体的な実施の形態例について、説明する。Hereinafter, preferred specific embodiments of the present invention will be described with reference to the drawings.

【００２７】実施の形態例１ 図１にこの実施の形態例の異方性導電フィルムの断面構
成を示す。図２及び図３に、この実施の形態例における
実装工程を示す。Embodiment 1 FIG. 1 shows a cross-sectional structure of an anisotropic conductive film of this embodiment. 2 and 3 show a mounting process in this embodiment.

【００２８】図１を参照する。本実施の形態例における
異方性導電フィルム（ＡＣＦ）１１は、シリカ等でなる
絶縁性のフィラー３が充填されたフィラー含有フィルム
層１と、絶縁性のフィラーが充填されないフィラーフリ
ーフィルム層２とが積層された、２層タイプの異方性導
電フィルムとして形成されている。本実施の形態例に係
る異方性導電フィルム１１にあっては、上記フィラー含
有フィルム層１及びフィラーフリーフィルム層２との両
フィルム層の各々に、導電粒子４が充填されている。Referring to FIG. The anisotropic conductive film (ACF) 11 in the present embodiment includes a filler-containing film layer 1 filled with an insulating filler 3 made of silica or the like, and a filler-free film layer 2 not filled with an insulating filler. Are laminated as a two-layer type anisotropic conductive film. In the anisotropic conductive film 11 according to the present embodiment, both the filler-containing film layer 1 and the filler-free film layer 2 are filled with conductive particles 4.

【００２９】本実施の形態例のフィラー含有フィルム層
１は、熱膨張率制御に適合する量で絶縁性のフィラー３
を含有している。特にここでは、エポキシ樹脂等の高熱
膨張率の樹脂材料の膨張率を抑制するために適した量
で、絶縁性のフィラー３を含有する。従来技術で全層に
絶縁性のフィラーを含有させた場合と同様な効果を呈し
得る最適な量を選択する。フィラーフリーフィルム層２
に充填されるべきフィラーに見合う分を補填する形で、
フィラー含有フィルム層１に絶縁性のフィラーを含有さ
せればよい。たとえば各層１，２の厚さ比率が同じであ
る場合には、従来の含有量（重量％）の２倍量を充填す
る。ただし、従来技術において含有量が５０重量％であ
れば、その不足分を補おうとすると１００重量％含有に
なって、異方性導電フィルムの形成が不可能なので、本
実施の形態例では上限７５重量％を目安として、各層
１，２の厚さ比率を変更する（フィラー含有フィルム層
１の厚さをフィラーフリーフィルム層２より厚くする）
こととした。このようにしたことで、異方性導電フィル
ム内のフィラー充填量を従来と同様にすることができ
る。好ましくは、３０重量％以上５０重量％以下の絶縁
性のフィラーを充填していた場合、フィラー含有フィル
ム層１とフィラーフリーフィルム層２との膜厚の比にも
よるが、５０重量％以上７５重量％以下の絶縁性のフィ
ラーを充填する形態が好ましい。The filler-containing film layer 1 of the present embodiment has an insulating filler 3 in an amount suitable for controlling the coefficient of thermal expansion.
It contains. In particular, here, the insulating filler 3 is contained in an amount suitable for suppressing the expansion coefficient of a resin material having a high thermal expansion coefficient such as an epoxy resin. An optimum amount is selected which can exhibit the same effect as in the case where the insulating filler is contained in all the layers in the prior art. Filler-free film layer 2
In a form to compensate for the amount of filler to be filled into
What is necessary is just to make the filler containing film layer 1 contain an insulating filler. For example, when the thickness ratio of each of the layers 1 and 2 is the same, twice the amount of the conventional content (% by weight) is filled. However, if the content is 50% by weight in the prior art, if the content is to be compensated for, the content will be 100% by weight, making it impossible to form an anisotropic conductive film. The thickness ratio of each of the layers 1 and 2 is changed based on the weight% (the thickness of the filler-containing film layer 1 is made larger than that of the filler-free film layer 2).
I decided that. By doing so, the filler filling amount in the anisotropic conductive film can be made the same as in the conventional case. Preferably, when 30% by weight or more and 50% by weight or less of an insulating filler is filled, 50% by weight or more and 75% by weight or more depending on the thickness ratio between the filler-containing film layer 1 and the filler-free film layer 2. A form in which an insulating filler of not more than% by weight is filled is preferable.

【００３０】本実施の形態例においては、フィラー含有
フィルム層１とフィラーフリーフィルム層２とは、同じ
樹脂成分とする。これにより、２層の適合性を保証でき
る。ただし、異なる樹脂成分とする構成も可能である。
樹脂成分としては、たとえばエポキシ系樹脂、アクリル
系樹脂、ウレタン系樹脂を用いることができる。導電粒
子としては、たとえばニッケル粒子、はんだ粒子、銀粒
子、金プラスチック粒子（プラスチック粒子表面をＮｉ
−Ａｕメッキ処理したもの）を用いることができる。一
般的に好ましく用いることができる組み合わせは、樹脂
成分がエポキシ系樹脂で、導電粒子がニッケル粒子また
は金プラスチック粒子である場合である。本実施の形態
例ではベース樹脂をエポキシ樹脂とし、フィラーを粉末
シリカとし、導電粒子を粉末ニッケルとした。In this embodiment, the filler-containing film layer 1 and the filler-free film layer 2 have the same resin component. This guarantees compatibility of the two layers. However, a configuration using different resin components is also possible.
As the resin component, for example, an epoxy resin, an acrylic resin, or a urethane resin can be used. Examples of the conductive particles include nickel particles, solder particles, silver particles, and gold plastic particles (the surface of the plastic particles is Ni
-Au plating treatment) can be used. In general, a combination that can be preferably used is a case where the resin component is an epoxy resin and the conductive particles are nickel particles or gold plastic particles. In this embodiment, the base resin is epoxy resin, the filler is powdered silica, and the conductive particles are powdered nickel.

【００３１】次に図２及び図３を参照して、本実施の形
態例における異方性導電フィルム利用の実装方法につい
て述べる。図２及び図３は、本実施の形態例の異方性導
電フィルムを用いた場合のフリップチップ接続部を概念
的に図示して、フリップチップ実装の工程を示したもの
である。本実施の形態例では、用いる異方性導電フィル
ム以外については、基本的には上記説明した従来技術と
同様のものを使用する。Next, a mounting method using an anisotropic conductive film in the present embodiment will be described with reference to FIGS. 2 and 3 conceptually illustrate a flip-chip connecting portion when the anisotropic conductive film of the present embodiment is used, and show a flip-chip mounting process. In the present embodiment, those other than the anisotropic conductive film to be used are basically the same as those of the above-described prior art.

【００３２】まず、配線基板９の基板面９Ａに所定パタ
ーンで形成された複数のランド１０を覆うように、本実
施の形態例の異方性導電フィルム１１を、そのフィラー
フリーフィルム層２を基板面９Ａに向けて、貼り付ける
（図２）。First, the anisotropic conductive film 11 of the present embodiment is coated with the filler-free film layer 2 so as to cover a plurality of lands 10 formed in a predetermined pattern on the substrate surface 9A of the wiring substrate 9. Affix to surface 9A (FIG. 2).

【００３３】その後は上記説明した従来技術における異
方性導電フィルムによる接続と同様にして、実装を行
う。すなわち、半導体チップ５の回路面５Ａを配線基板
９の基板面９Ａに対向させた後、各々の金（Ａｕ）ワイ
ヤバンプ７を当該基板面９Ａに形成された各ランド１０
に対向させて位置合わせする。この状態において、熱圧
着を行う。たとえば上記位置合わせした状態において、
１６０〜２４０℃、５〜４０ｓｅｃ．、及び１バンプ当
たりの圧力５〜１００ｇで熱圧着する。これにより、半
導体チップ５と配線基板９との間に異方性導電フィルム
１１が充填され、この結果、半導体チップ５は簡単に配
線基板９の基板面９Ａにフリップチップ実装される。実
装後の状態を図３に示す。After that, mounting is performed in the same manner as the connection using the anisotropic conductive film in the above-described conventional technique. That is, after the circuit surface 5A of the semiconductor chip 5 is opposed to the substrate surface 9A of the wiring substrate 9, each gold (Au) wire bump 7 is formed on each land 10A formed on the substrate surface 9A.
And position it. In this state, thermocompression bonding is performed. For example, in the above-mentioned alignment state,
160-240 ° C, 5-40 sec. And thermocompression bonding at a pressure of 5 to 100 g per bump. Thereby, the anisotropic conductive film 11 is filled between the semiconductor chip 5 and the wiring board 9, and as a result, the semiconductor chip 5 is easily flip-chip mounted on the substrate surface 9 </ b> A of the wiring board 9. FIG. 3 shows a state after mounting.

【００３４】この熱圧着の際に、絶縁性のフィラー３が
充填されたフィラー含有フィルム層１が半導体チップ５
の回路面５Ａ側に存在するため、フリップチップ接続部
分においてフィラー３を挟み込む可能性は低い。仮にフ
ィラー含有フィルム層１が配線基板９のランド１０側に
存在すると、フリップチップ接続部分にフィラー３が挟
み込まれる可能性は高くなるが、本実施の形態例では逆
であるので、フリップチップ接続部分にフィラー３が挟
み込まれるおそれは小さく、フィラー３により接続不良
が生じることを防止できる。At the time of the thermocompression bonding, the filler-containing film layer 1 filled with the insulating filler 3 is
Therefore, the possibility that the filler 3 is sandwiched in the flip chip connection portion is low. If the filler-containing film layer 1 exists on the land 10 side of the wiring board 9, the possibility that the filler 3 is sandwiched in the flip chip connection portion increases, but in the present embodiment, it is the opposite, so the flip chip connection portion The possibility that the filler 3 is caught in the filler 3 is small, and it is possible to prevent the connection failure due to the filler 3 from occurring.

【００３５】なお、導電粒子充填層と、導電粒子を充填
しない層との２層構成の異方性導電フィルムを用いて、
導電粒子充填層を配線基板のランド側に向けて接続する
ことによりより多くの導電粒子をワイヤバンプと配線基
板パッドに挟み込ませる試みがあり、その効果がうたわ
れているが、この技術ではフィラーについては問題にし
ていない。It should be noted that an anisotropic conductive film having a two-layer structure of a conductive particle-filled layer and a layer not filled with conductive particles was used.
Attempts have been made to connect more conductive particles to the wire bumps and wiring board pads by connecting the conductive particle filling layer toward the land side of the wiring board, and the effect has been claimed, but this technology has a problem with fillers Not.

【００３６】本実施の形態例によれば、本発明を適用し
たことにより、シリカ等でなる絶縁性のフィラーが充填
されたフィルム層と、フィラーが充填されていないフィ
ルム層とが積層されている異方性導電フィルムを用い、
配線基板への異方性導電フィルム貼り付けの際には、配
線基板のランド側に未充填のフィルム層側を貼り付ける
ため、フリップチップ実装時に配線基板側には当該フィ
ラーは存在しない。したがって、フリップチップ実装の
際に、当該フィラーが金等のワイヤバンプと配線基板の
ランドとの間に挟まれる可能性が低く、接続性が安定す
る。According to this embodiment, by applying the present invention, a film layer filled with an insulating filler such as silica and a film layer not filled with a filler are laminated. Using an anisotropic conductive film,
When the anisotropic conductive film is attached to the wiring board, the unfilled film layer is attached to the land side of the wiring board, so that the filler does not exist on the wiring board side during flip chip mounting. Therefore, at the time of flip-chip mounting, the possibility that the filler is caught between the wire bumps of gold or the like and the land of the wiring board is low, and the connectivity is stabilized.

【００３７】実施の形態例２ 図３にこの実施の形態例の異方性導電フィルムの断面構
成を示す。図３に示すように、本実施の形態例における
異方性導電フィルム（ＡＣＦ）１１は、シリカ等でなる
絶縁性のフィラー３が充填されたフィラー含有フィルム
層１と、絶縁性のフィラーが充填されないフィラーフリ
ーフィルム層２とが積層された、２層タイプの異方性導
電フィルムとして形成され、この点は上記実施の形態例
１と同様である。ただし、本実施の形態例に係る異方性
導電フィルム１１にあっては、上記フィラーフリーフィ
ルム層２のみに、導電粒子４が充填されている。Embodiment 2 FIG. 3 shows a cross-sectional structure of an anisotropic conductive film of this embodiment. As shown in FIG. 3, the anisotropic conductive film (ACF) 11 in the present embodiment includes a filler-containing film layer 1 filled with an insulating filler 3 made of silica or the like, and an insulating filler filled with an insulating filler. It is formed as a two-layer type anisotropic conductive film in which a filler-free film layer 2 not laminated is laminated, and this point is the same as in the first embodiment. However, in the anisotropic conductive film 11 according to the present embodiment, only the filler-free film layer 2 is filled with the conductive particles 4.

【００３８】その他の構成は、実施の形態例１と同様で
あり、実施の形態例１と同様に、フリップチップ実装を
行うことができる。本実施の形態例も、実施の形態例１
と同様の効果を発揮できる。なお実装に当たっては、導
電粒子はワイヤバンプと配線基板のランド間に挟み込む
必要があり、フィラーの方はできる限り挟み込みたくな
いので、本実施の形態例を用いて導電粒子が配線基板の
ランド側に存在し、フィラーはその逆の側にしか存在し
ないようにすることは、信頼性上、好ましいことであ
る。また、本実施の形態例ではフィラーフリーフィルム
層のみに導電粒子４を充填すればよいので、コスト的に
もメリットがある。Other configurations are the same as those of the first embodiment, and flip-chip mounting can be performed as in the first embodiment. This embodiment is also the first embodiment.
The same effect can be exhibited. In mounting, the conductive particles need to be sandwiched between the wire bumps and the land of the wiring board, and the filler is not desired to be sandwiched as much as possible. Therefore, the conductive particles are present on the land side of the wiring board using the present embodiment. However, it is preferable in terms of reliability that the filler be present only on the opposite side. Further, in the present embodiment, since only the filler-free film layer needs to be filled with the conductive particles 4, there is an advantage in cost.

【００３９】[0039]

【発明の効果】上述したように、本発明の異方性導電フ
ィルム及びこれを用いた実装方法、ならびに配線用の基
板によれば、絶縁性のフィラーを含有させて異方性導電
フィルムの熱膨張の問題を解決できるとともに、該絶縁
性のフィラーを含有させた場合の接続不良のおそれを解
決できるという効果が発揮される。As described above, according to the anisotropic conductive film of the present invention, the mounting method using the same, and the wiring substrate, an insulating filler is contained to heat the anisotropic conductive film. The effect of solving the problem of expansion and solving the possibility of poor connection when the insulating filler is contained is exhibited.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 本発明の実施の形態例１に係る異方性導電フ
ィルムを示す断面図である。FIG. 1 is a cross-sectional view illustrating an anisotropic conductive film according to Embodiment 1 of the present invention.

【図２】 本発明の実施の形態例１における実装工程を
示す断面図であり、異方性導電フィルムによるフリップ
チップ接続のプロセス概念を断面図で示したものである
（１）。FIG. 2 is a cross-sectional view showing a mounting step in the first embodiment of the present invention, and is a cross-sectional view showing a concept of a process of flip-chip connection using an anisotropic conductive film (1).

【図３】 本発明の実施の形態例１における実装工程を
示す断面図であり、異方性導電フィルムによるフリップ
チップ接続のプロセス概念を断面図で示したものである
（２）。FIG. 3 is a cross-sectional view showing a mounting step according to the first embodiment of the present invention, and is a cross-sectional view showing a concept of a process of flip-chip connection using an anisotropic conductive film (2).

【図４】 本発明の実施の形態例２に係る異方性導電フ
ィルムを示す断面図である。FIG. 4 is a sectional view showing an anisotropic conductive film according to Embodiment 2 of the present invention.

【図５】 従来の技術を示す図で、異方性導電フィルム
を接続媒体としたプリント回路基板の断面図である。FIG. 5 is a view showing a conventional technique, and is a cross-sectional view of a printed circuit board using an anisotropic conductive film as a connection medium.

【図６】 異方性導電フィルムを接続媒体としたフリッ
プチップ実装を示す断面図である。FIG. 6 is a cross-sectional view showing flip-chip mounting using an anisotropic conductive film as a connection medium.

【図７】 熱膨張が与えるフリップチップ実装への影響
を概念図で示すものである。FIG. 7 is a conceptual diagram showing the effect of thermal expansion on flip chip mounting.

【図８】 従来技術の問題点を示す図で、従来の異方性
導電フィルムによるフリップチップ接続のプロセス概念
を断面図で示したものである。FIG. 8 is a view showing a problem of the prior art, and is a cross-sectional view showing a concept of a process of flip-chip connection using a conventional anisotropic conductive film.

【符号の説明】[Explanation of symbols]

１・・・フィラー含有フィルム層、２・・・導電粒子含
有フィルム層（フィラーフリーフィルム層）、３・・・
絶縁性のフィラー、４・・・導電粒子、５・・・半導体
チップ、６・・・接続パッド、７・・・ワイヤバンプ、
８・・・プリント回路基板、９・・・配線基板、１０・
・・ランド、１１・・・異方性導電フィルム。DESCRIPTION OF SYMBOLS 1 ... Filler containing film layer, 2 ... Conductive particle containing film layer (filler-free film layer), 3 ...
Insulating filler, 4 ... conductive particles, 5 ... semiconductor chip, 6 ... connection pad, 7 ... wire bump,
8 ... printed circuit board, 9 ... wiring board, 10
..Land, 11: anisotropic conductive film.

Claims (24)

【特許請求の範囲】[Claims] 【請求項１】 少なくとも２層のフィルム層が積層され
ている異方性導電フィルムであって、 前記少なくとも２層のフィルム層のうちの一方のフィル
ム層には絶縁性を有するフィラーと導電性粒子とが含有
され、 他方のフィルム層には前記導電性粒子が含有されている
ことを特徴とする異方性導電フィルム。1. An anisotropic conductive film in which at least two film layers are laminated, wherein one of the at least two film layers has an insulating filler and conductive particles. And an anisotropic conductive film, wherein the other film layer contains the conductive particles. 【請求項２】 前記フィラーと導電性粒子とが含有され
ているフィルム層は、熱膨張率制御に適合する量で絶縁
性のフィラーを含有することを特徴とする請求項１に記
載の異方性導電フィルム。2. The anisotropic filler according to claim 1, wherein the film layer containing the filler and the conductive particles contains an insulating filler in an amount suitable for controlling the coefficient of thermal expansion. Conductive film. 【請求項３】 前記フィラーと導電性粒子とが含有され
ているフィルム層のフィラーの含有量は、５０重量％以
上７５重量％以下であることを特徴とする請求項１に記
載の異方性導電フィルム。3. The anisotropic material according to claim 1, wherein the content of the filler in the film layer containing the filler and the conductive particles is 50% by weight or more and 75% by weight or less. Conductive film. 【請求項４】 前記フィラーと導電性粒子とが含有され
ているフィルム層と、前記導電性粒子が含有されている
フィルム層とは、同じ樹脂成分からなることを特徴とす
る請求項１に記載の異方性導電フィルム。4. The film layer containing the filler and the conductive particles and the film layer containing the conductive particles are made of the same resin component. Anisotropic conductive film. 【請求項５】 少なくとも２層のフィルム層が積層され
ている異方性導電フィルムであって、 前記少なくとも２層のフィルム層のうちの一方のフィル
ム層には絶縁性を有するフィラーが含有され、 他方のフィルム層には導電性粒子が含有されていること
を特徴とする異方性導電フィルム。5. An anisotropic conductive film in which at least two film layers are laminated, wherein one of the at least two film layers contains a filler having an insulating property, An anisotropic conductive film, wherein the other film layer contains conductive particles. 【請求項６】 前記フィラーが含有されているフィルム
層は、熱膨張率制御に適合する量で絶縁性のフィラーを
含有することを特徴とする請求項５に記載の異方性導電
フィルム。6. The anisotropic conductive film according to claim 5, wherein the filler-containing film layer contains an insulating filler in an amount suitable for controlling the coefficient of thermal expansion. 【請求項７】 前記フィラーが含有されているフィルム
層のフィラーの含有量は、５０重量％以上７５重量％以
下であることを特徴とする請求項５に記載の異方性導電
フィルム。7. The anisotropic conductive film according to claim 5, wherein the content of the filler in the film layer containing the filler is 50% by weight or more and 75% by weight or less. 【請求項８】 前記フィラーが含有されているフィルム
層と、前記導電性粒子が含有されているフィルム層と
は、同じ樹脂成分からなることを特徴とする請求項５に
記載の異方性導電フィルム。8. The anisotropic conductive film according to claim 5, wherein the film layer containing the filler and the film layer containing the conductive particles are made of the same resin component. the film. 【請求項９】 配線基板に半導体チップを実装する実装
方法であって、 少なくとも２層のフィルム層が積層されている異方性導
電フィルムで、前記少なくとも２層のフィルム層のうち
の一方のフィルム層には絶縁性を有するフィラーと導電
性粒子とが含有され、他方のフィルム層には前記導電性
粒子が含有されている異方性導電フィルムを用い、 配線基板と前記他方のフィルム層である導電性粒子が含
有されている層とが対向する位置関係で前記異方性導電
フィルムを前記配線基板と前記半導体チップとの間に挟
んで該異方性導電フィルムにより接続をとることを特徴
とする実装方法。9. A mounting method for mounting a semiconductor chip on a wiring board, comprising: an anisotropic conductive film in which at least two film layers are laminated; one of the at least two film layers; The layer contains an insulating filler and conductive particles, and the other film layer uses an anisotropic conductive film containing the conductive particles, and is a wiring board and the other film layer. The anisotropic conductive film is sandwiched between the wiring board and the semiconductor chip in a positional relationship in which the layer containing the conductive particles is opposed to the layer, and a connection is made by the anisotropic conductive film. How to implement. 【請求項１０】 前記フィラーと導電性粒子とが含有さ
れているフィルム層は、熱膨張率制御に適合する量で絶
縁性のフィラーを含有することを特徴とする請求項９に
記載の実装方法。10. The mounting method according to claim 9, wherein the film layer containing the filler and the conductive particles contains an insulating filler in an amount suitable for controlling the coefficient of thermal expansion. . 【請求項１１】 前記フィラーと導電性粒子とが含有さ
れているフィルム層のフィラーの含有量は、５０重量％
以上７５重量％以下であることを特徴とする請求項９に
記載の実装方法。11. The content of the filler in the film layer containing the filler and the conductive particles is 50% by weight.
10. The mounting method according to claim 9, wherein the content is not less than 75% by weight. 【請求項１２】 前記フィラーと導電性粒子とが含有さ
れているフィルム層と、前記導電性粒子が含有されてい
るフィルム層とは、同じ樹脂成分からなることを特徴と
する請求項９に記載の実装方法。12. The film layer containing the filler and the conductive particles and the film layer containing the conductive particles are made of the same resin component. How to implement. 【請求項１３】 配線基板に半導体チップを実装する実
装方法であって、 少なくとも２層のフィルム層が積層されている異方性導
電フィルムであり、前記少なくとも２層のフィルム層の
うちの一方のフィルム層には絶縁性を有するフィラーが
含有され、他方のフィルム層には導電性粒子が含有され
ている異方性導電フィルムを用い、 配線基板と前記他方のフィルム層である導電性粒子が含
有されているフィルム層とが対向する位置関係で前記異
方性導電フィルムを前記配線基板と前記半導体チップと
の間に挟んで該異方性導電フィルムにより接続をとるこ
とを特徴とする実装方法。13. A mounting method for mounting a semiconductor chip on a wiring board, comprising: an anisotropic conductive film in which at least two film layers are laminated; and one of the at least two film layers. The film layer contains an insulating filler, and the other film layer uses an anisotropic conductive film containing conductive particles, and contains the wiring substrate and the conductive particles that are the other film layer. A mounting method, wherein the anisotropic conductive film is sandwiched between the wiring substrate and the semiconductor chip in a positional relationship in which the film layer faces each other, and a connection is made by the anisotropic conductive film. 【請求項１４】 前記フィラーが含有されているフィル
ム層は、熱膨張率制御に適合する量で絶縁性のフィラー
を含有することを特徴とする請求項１３に記載の実装方
法。14. The mounting method according to claim 13, wherein the film layer containing the filler contains an insulating filler in an amount suitable for controlling the coefficient of thermal expansion. 【請求項１５】 前記フィラーが含有されているフィル
ム層のフィラーの含有量は、５０重量％以上７５重量％
であることを特徴とする請求項１３に記載の実装方法。15. The content of the filler in the film layer containing the filler is 50% by weight to 75% by weight.
14. The mounting method according to claim 13, wherein: 【請求項１６】 前記フィラーが含有されているフィル
ム層と、前記導電性粒子が含有されているフィルム層と
は、同じ樹脂成分からなることを特徴とする請求項１３
に記載の実装方法。16. The film layer containing the filler and the film layer containing the conductive particles are made of the same resin component.
Implementation method described in. 【請求項１７】 配線基板の実装面上に少なくとも２層
のフィルム層が積層されている異方性導電フィルムを配
してなる配線用の基板であって、 前記異方性導電フィルムの前記少なくとも２層のフィル
ム層のうちの一方のフィルム層には絶縁性を有するフィ
ラーと導電性粒子とが含有され、他方のフィルム層には
前記導電性粒子が含有され、 かつ、前記配線基板と前記他方のフィルム層である導電
性粒子が含有されている層とが対向する位置関係で前記
異方性導電フィルムを前記配線基板に配してなることを
特徴とする配線用の基板。17. A wiring substrate comprising an anisotropic conductive film in which at least two film layers are laminated on a mounting surface of a wiring substrate, wherein the at least one of the anisotropic conductive films One of the two film layers contains a filler having an insulating property and conductive particles, the other film layer contains the conductive particles, and the wiring board and the other A wiring substrate, wherein the anisotropic conductive film is disposed on the wiring substrate in a positional relationship facing a layer containing conductive particles, which is a film layer of (1). 【請求項１８】 前記フィラーと導電性粒子とが含有さ
れているフィルム層は、熱膨張率制御に適合する量で絶
縁性のフィラーを含有することを特徴とする請求項１７
に記載の配線用の基板。18. The film layer containing the filler and the conductive particles contains an insulating filler in an amount suitable for controlling the coefficient of thermal expansion.
4. The wiring substrate according to claim 1. 【請求項１９】 前記フィラーと導電性粒子とが含有さ
れているフィルム層のフィラーの含有量は、５０重量％
以上７５重量％であることを特徴とする請求項１７に記
載の配線用の基板。19. The content of the filler in the film layer containing the filler and the conductive particles is 50% by weight.
The wiring substrate according to claim 17, wherein the content is 75% by weight or more. 【請求項２０】 前記フィラーと導電性粒子とが含有さ
れているフィルム層と、前記導電性粒子が含有されてい
るフィルム層とは、同じ樹脂成分からなることを特徴と
する請求項１７に記載の配線用の基板。20. The film layer according to claim 17, wherein the film layer containing the filler and the conductive particles and the film layer containing the conductive particles are made of the same resin component. Wiring board. 【請求項２１】 配線基板の実装面上に少なくとも２層
のフィルム層が積層されている異方性導電フィルムを配
してなる配線用の基板であって、 前記異方性導電フィルムの前記少なくとも２層のフィル
ム層のうちの一方のフィルム層には絶縁性を有するフィ
ラーが含有され、他方のフィルム層には導電性粒子が含
有され、 かつ、前記配線基板と前記他方のフィルム層である導電
性粒子が含有されている層とが対向する位置関係で前記
異方性導電フィルムを前記配線基板に配してなることを
特徴とする配線用の基板。21. A wiring board comprising an anisotropic conductive film in which at least two film layers are laminated on a mounting surface of a wiring board, wherein the at least one of the anisotropic conductive films One of the two film layers contains a filler having an insulating property, the other film layer contains conductive particles, and the conductive material, which is the wiring board and the other film layer, A wiring substrate, wherein the anisotropic conductive film is disposed on the wiring substrate in a positional relationship facing a layer containing the conductive particles. 【請求項２２】 前記フィラーが含有されているフィル
ム層は、熱膨張率制御に適合する量で絶縁性のフィラー
を含有することを特徴とする請求項２１に記載の配線用
の基板。22. The wiring substrate according to claim 21, wherein the film layer containing the filler contains an insulating filler in an amount suitable for controlling the coefficient of thermal expansion. 【請求項２３】 前記フィラーが含有されているフィル
ム層のフィラーの含有量は、５０重量％以上７５重量％
であることを特徴とする請求項２１に記載の配線用の基
板。23. The content of the filler in the film layer containing the filler is 50% by weight to 75% by weight.
22. The wiring substrate according to claim 21, wherein: 【請求項２４】 前記フィラーが含有されているフィル
ム層と、前記導電性粒子が含有されているフィルム層と
は、同じ樹脂成分からなることを特徴とする請求項２１
に記載の配線用の基板。24. The film layer containing the filler and the film layer containing the conductive particles are made of the same resin component.
4. The wiring substrate according to claim 1.
JP2000115250A 2000-04-17 2000-04-17 Anisotropic conductive film, its assembly method, and circuit board using the same Pending JP2001307555A (en)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7227730B2 (en) 2004-05-28 2007-06-05 Infineon Technolgoies Ag Device for ESD protection of an integrated circuit
KR100731667B1 (en) 2005-05-10 2007-06-22 히다치 가세고교 가부시끼가이샤 Anisotropic conductive film and circuit board using the same
KR100751452B1 (en) * 2007-02-16 2007-08-23 히다치 가세고교 가부시끼가이샤 Anisotropic conductive film and circuit board using same
US20160270225A1 (en) 2013-11-19 2016-09-15 Dexerials Corporation Anisotropic conductive film and connected structure
CN113555334A (en) * 2021-07-20 2021-10-26 京东方科技集团股份有限公司 OLED display panel and display device
KR20220042247A (en) * 2013-11-19 2022-04-04 데쿠세리아루즈 가부시키가이샤 Anisotropic electroconductive film and connection structure
US11591499B2 (en) 2015-01-13 2023-02-28 Dexerials Corporation Anisotropic conductive film

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7227730B2 (en) 2004-05-28 2007-06-05 Infineon Technolgoies Ag Device for ESD protection of an integrated circuit
KR100731667B1 (en) 2005-05-10 2007-06-22 히다치 가세고교 가부시끼가이샤 Anisotropic conductive film and circuit board using the same
KR100751452B1 (en) * 2007-02-16 2007-08-23 히다치 가세고교 가부시끼가이샤 Anisotropic conductive film and circuit board using same
US11139265B2 (en) 2013-11-19 2021-10-05 Dexerials Corporation Anisotropic conductive film and connected structure
US10510711B2 (en) 2013-11-19 2019-12-17 Dexerials Corporation Anisotropic conductive film and connected structure
US10522502B2 (en) 2013-11-19 2019-12-31 Dexerials Corporation Anisotropic conductive film and connected structure
US20160270225A1 (en) 2013-11-19 2016-09-15 Dexerials Corporation Anisotropic conductive film and connected structure
KR20220042247A (en) * 2013-11-19 2022-04-04 데쿠세리아루즈 가부시키가이샤 Anisotropic electroconductive film and connection structure
US11923335B2 (en) 2013-11-19 2024-03-05 Dexerials Corporation Anisotropic conductive film and connected structure
KR102697500B1 (en) * 2013-11-19 2024-08-21 데쿠세리아루즈 가부시키가이샤 Anisotropic electroconductive film and connection structure
US11591499B2 (en) 2015-01-13 2023-02-28 Dexerials Corporation Anisotropic conductive film
CN113555334A (en) * 2021-07-20 2021-10-26 京东方科技集团股份有限公司 OLED display panel and display device
CN113555334B (en) * 2021-07-20 2024-07-02 京东方科技集团股份有限公司 OLED display panel and display device

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