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CN111383990B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN111383990B
CN111383990B CN201811621152.8A CN201811621152A CN111383990B CN 111383990 B CN111383990 B CN 111383990B CN 201811621152 A CN201811621152 A CN 201811621152A CN 111383990 B CN111383990 B CN 111383990B
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layer
conductive
forming
adhesion
semiconductor structure
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CN111383990A (en
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吴轶超
张天豪
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate comprising: a first conductive layer and a dielectric layer on the first conductive layer; forming a trench in the dielectric layer exposing the first conductive layer; forming a barrier layer conformally covering the trench; conformally covering an adhesion layer on the barrier layer; conformally covering a backing layer over the adhesive layer; after forming the liner layer, a second conductive layer is formed within the trench. Because the adhesion between the adhesion layer and the barrier layer and the lining layer is good, the probability of generating holes between the adhesion layer and the lining layer and between the adhesion layer and the barrier layer is reduced, and accordingly, the probability of generating holes between the second conductive layer and the dielectric layer is reduced, the electromigration at the interface of the second conductive layer and the dielectric layer is good, and the reliability and the yield of the device can be improved.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
As semiconductor fabrication technology has become more sophisticated, significant changes have also been made to integrated circuits, and the number of components integrated on the same chip has increased from the first tens, hundreds, to millions today. In order to meet the requirement of circuit density, the fabrication process of semiconductor integrated circuit chips forms various types of complex devices on a substrate by using a batch process technology and connects them to each other to have a complete electronic function, and at present, an ultra-low k interlayer dielectric layer is mostly used between wires as a dielectric material for isolating each metal interconnect, and an interconnection structure is used for providing wiring between devices on the IC chip and the entire package. In this technique, devices such as Field Effect Transistors (FETs) are first formed on a semiconductor substrate surface, and then interconnect structures are formed in a Back End of Line (BEOL) process of integrated circuit fabrication.
As predicted by moore's law, the ever shrinking dimensions of semiconductor substrates and the use of interconnect structures to connect transistors is a necessary option in order to increase the performance of devices where more transistors are formed on the semiconductor substrate. However, compared with the miniaturization and integration of components, the number of conductor wires in a circuit is continuously increased, the formation quality of an interconnection structure greatly affects the reliability of circuit connection, and the normal operation of a semiconductor device can be affected in severe cases.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and optimizes the electrical performance of the semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate comprising: a first conductive layer and a dielectric layer on the first conductive layer; forming a trench in the dielectric layer exposing the first conductive layer; forming a barrier layer conformally covering the trench; conformally covering an adhesion layer on the barrier layer; conformally covering a backing layer over the adhesive layer; after forming the liner layer, a second conductive layer is formed within the trench.
Optionally, the material of the adhesion layer is Ru or W.
Optionally, the thickness of the adhesive layer is 10 to 20 a.
Optionally, the adhesion layer is formed using an atomic layer deposition process or a physical vapor deposition process.
Optionally, the barrier layer is formed using a physical vapor deposition process.
Optionally, the material of the barrier layer is one or more of TaN, ta, ti, tiN, zrN and zrttin.
Optionally, the thickness of the barrier layer is 10 to 40 a.
Optionally, the material of the lining layer includes one or more of Co, al, W, and Ti.
Alternatively, a chemical vapor deposition process is used to form the liner layer.
Optionally, the thickness of the backing layer is 10 to 40 a.
Optionally, the material of the second conductive layer includes Cu, al, or Co.
Optionally, the step of forming the second conductive layer includes: forming a seed layer conformally covering the liner layer; filling a conductive material into the trench in which the seed layer is formed; and removing the conductive material exposing the groove to form a second conductive layer.
Optionally, an electrochemical plating process is used to fill the trench with a conductive material.
Optionally, the method for forming the semiconductor structure further includes: and annealing the semiconductor structure after the second conductive layer is formed.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate comprising a first conductive layer and a dielectric layer on the first conductive layer; a trench in the dielectric layer exposing the first conductive layer; a barrier layer conformally covering the bottom and sidewalls of the trench; an adhesion layer conformally overlying the barrier layer; a backing layer conformally overlying the adhesive layer; and the second conductive layer is filled in the groove.
Optionally, the material of the adhesion layer is Ru or W.
Optionally, the thickness of the adhesive layer is 10 to 20 a.
Optionally, the material of the barrier layer is one or more of TaN, ta, ti, tiN, zrN and zrttin.
Optionally, the material of the lining layer includes one or more of Co, al, W, and Ti.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
after forming a groove in a dielectric layer, forming a blocking layer which conformally covers the groove, and conformally covering an adhesion layer on the blocking layer; and conformally covering a lining layer on the adhesion layer, and forming a second conductive layer in the groove after forming the lining layer. C and O are generally generated during the formation of the backing layer, and the adhesive layer does not react with C and O, so that impurity compounds are not easily generated, and thus the adhesion between the adhesive layer and the backing layer is good; since the adhesion layer is between the liner layer and the barrier layer, C and O are difficult to react with the barrier layer through the adhesion layer, and an impurity compound is difficult to form between the adhesion layer and the barrier layer, the adhesion between the adhesion layer and the barrier layer is good. Because the adhesion between the adhesion layer and the barrier layer and the liner layer is good, the probability of generating holes between the adhesion layer and the liner layer and between the adhesion layer and the barrier layer is reduced, and accordingly, the probability of generating holes between the bottom of the second conductive layer and the first conductive layer is reduced, so that the reliability of the electrical connection between the second conductive layer and the first conductive layer can be improved, and the electrical reliability and yield of the semiconductor structure can be improved.
Drawings
Fig. 1 to 5 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
fig. 6 to 13 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As can be seen from the background art, the devices formed at present still have the problem of poor performance. The reason for the poor performance of the device is analyzed by combining a forming method of a semiconductor structure.
Referring to fig. 1 to 5, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
Referring to fig. 1, a substrate is provided, which includes a first conductive layer 1, an etch-resistant layer 10 on the first conductive layer 1, a dielectric layer 2 on the etch-resistant layer 10, and a mask layer 3 on the dielectric layer 2.
Referring to fig. 2, the dielectric layer 2 and the mask layer 3 on the dielectric layer 2 are etched to form a trench 4 exposing the first conductive layer 1.
Referring to fig. 3, a barrier layer 5 is formed conformally covering the trench 4; a liner layer 6 is conformally coated over the barrier layer 5.
The material of the barrier layer 5 is TaN; the material of the backing layer 6 is Co.
Specifically, the barrier layer 5 is formed using a physical vapor deposition process (Physical Vapor Deposition, PVD), and the liner layer 6 is formed using a chemical vapor deposition process (Chemical Vapor Deposition, CVD).
Referring to fig. 4, a seed layer (not shown) is formed to conformally cover the liner layer 6, and the trench 4 formed with the seed layer is filled with a conductive material; the layer of conductive material exposing the trenches 4 is removed and a second conductive layer 7 is formed.
The material of the second conductive layer 7 is Cu.
Referring to fig. 5, a top barrier layer 8 is formed on the second conductive layer 7; after the formation of the top barrier layer 8, an etch-resistant layer 9 is formed covering the top barrier layer 8 and the dielectric layer 2.
The lining layer 6 is formed by a Precursor (prefursor), carbonyl groups are contained in the lining layer 6, and C and O formed by carbonyl decomposition react with the barrier layer 5 to form impurity compounds. Because the trench 4 has a high Aspect Ratio (Aspect Ratio), the probability of defects occurring at the bottom of the second conductive layer 7 during the formation of the second conductive layer 7 is greater than that of other portions of the second conductive layer 7, and thus the bottom of the trench 4 is easily formed with impurity compounds, so that the adhesion between the barrier layer 5 and the liner layer 6 at the bottom of the second conductive layer 7 is poor. The semiconductor structure is subsequently annealed, which causes Cu in the second conductive layer 7 to recrystallize, and the atoms of Cu polymerize to reduce the volume of the second conductive layer 7, thereby eventually separating the bottom liner layer 6 of the trench 4 from the barrier layer 5 and creating a void 11 (as shown in fig. 5).
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate comprising: a first conductive layer and a dielectric layer on the first conductive layer; forming a trench in the dielectric layer exposing the first conductive layer; forming a barrier layer conformally covering the trench; conformally covering an adhesion layer on the barrier layer; conformally covering a backing layer over the adhesive layer; after forming the liner layer, a second conductive layer is formed within the trench.
After forming a groove in a dielectric layer, forming a blocking layer which conformally covers the groove, and conformally covering an adhesion layer on the blocking layer; and covering a lining layer on the adhesion layer in a conformal manner, and filling a conductive material in the groove after forming the lining layer to form a second conductive layer. C and O are generally generated during the formation of the backing layer, and the adhesive layer does not react with C and O, so that impurity compounds are not easily generated, and thus the adhesion between the adhesive layer and the backing layer is good; since the adhesion layer is between the liner layer and the barrier layer, C and O are difficult to react with the barrier layer through the adhesion layer, and an impurity compound is difficult to form between the adhesion layer and the barrier layer, the adhesion between the adhesion layer and the barrier layer is good. Because the adhesion between the adhesion layer and the barrier layer and the liner layer is good, the probability of generating holes between the adhesion layer and the liner layer and between the adhesion layer and the barrier layer is reduced, and accordingly, the probability of generating holes between the bottom of the second conductive layer and the first conductive layer is reduced, so that the reliability of the electrical connection between the second conductive layer and the first conductive layer can be improved, and the electrical reliability and yield of the semiconductor structure can be improved.
In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, a detailed description of specific embodiments of the present invention is provided below with reference to the accompanying drawings.
Fig. 6 to 13 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 6, a substrate is provided, the substrate comprising: a first conductive layer 100 and a dielectric layer 101 on said first conductive layer 100.
The first conductive layer 100 is a structure to be connected. In this embodiment, the material of the first conductive layer 100 is W. In other embodiments, the material of the first conductive layer may also be Al, co, or Cu.
It should be noted that the substrate further includes: a bottom dielectric layer 104, the first conductive layer 100 being located in the bottom dielectric layer 104. The bottom dielectric layer 104 is used to insulate between the respective first conductive layers 100. The dielectric layer 101 is used to insulate between subsequently formed second conductive layers.
The material Of the dielectric layer 101 is an ultra low K dielectric material (ULK), where the ultra low K dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6, and the dielectric layer 101 is made Of an ultra low K dielectric material, which can effectively reduce the parasitic capacitance Of the second conductive layer formed subsequently, thereby reducing the Back End Of Line (BEOL) RC delay.
The step of forming the dielectric layer 101 includes: forming a layer of dielectric material (not shown) on the first conductive layer 100, the layer of dielectric material comprising a thermally stable material and a thermally unstable pore former; the dielectric material layer is annealed at a temperature between the decomposition temperature of the thermally unstable material and the curing temperature of the thermally stable material, so that the thermally unstable material is decomposed and volatilized to form a single-phase, pore-filled dielectric layer 101. In this embodiment, the thermally stable material is a precursor of silicon oxide.
In other embodiments, the dielectric layer may be directly formed, and the material of the dielectric layer may be SiOCH.
It should be noted that the substrate further includes: a masking material layer 103 is formed on the dielectric layer 101. The masking material layer 103 is used to prepare the trench for the subsequent etching of the dielectric layer 101.
It should be noted that the substrate further includes: an etch stop material layer 102 is formed between the first conductive layer 100 and the dielectric layer 101.
In the subsequent process of etching the dielectric layer 101 to form a trench, the top surface of the etching stop material layer 102 is used to define an etching stop position, and compared with the dielectric layer 101, the etching stop material layer 102 has a higher etching selectivity, so that a good etching stop effect is provided, and the problem of excessive etching or insufficient etching caused by inconsistent etching rates of various regions can be avoided.
In this embodiment, the material of the etching stop material layer 102 is silicon nitride. In other embodiments, the material of the etching stop material layer may be SiON, siBCN, siCN, or the like. The etch stop material layer 102 can reduce the capacitive coupling effect between the first conductive layer 100 and a subsequently formed second conductive layer, thereby reducing the fringe parasitic capacitance.
Referring to fig. 7, a trench 105 is formed in the dielectric layer 101 and exposes the first conductive layer 100.
In this embodiment, a dry etching process is used to etch the dielectric layer 101 to form the trench 105. Specifically, the dry etching process is a plasma dry etching process.
In this embodiment, the etching gas used in the plasma dry etching process is CF 4 、CHF 3 、CH 2 F 2 Or C 4 F 8 The gas flow rate of the etching gas is 10sccm to 200sccm; the auxiliary gas adopted is O 2 The gas flow rate of the auxiliary gas is 0sccm to 100sccm; the dilution gas used is N 2 CO, he or Ar, the gas flow rate of the dilution gas is 10sccm to 1000sccm; the process pressure is 10mTorr to 200mTorr.
It should be noted that the step of forming the trench 105 in the etching the dielectric layer 101 includes: etching the mask material layer 103 on the dielectric layer 101 to form a mask layer 106; and etching the dielectric layer 101 by taking the mask layer 106 as a mask, and forming a groove 105 in the dielectric layer 101.
It should also be noted that the method for forming the semiconductor structure further includes: after forming the trench 105, etching the etching stop material layer 102 with the mask layer 106 as a mask is continued to form an etching stop layer 113 exposing the first conductive layer 100.
Referring to fig. 8, a barrier layer 107 is formed conformally covering the trench 105. The barrier layer 107 reduces the probability of conductive material diffusing into the dielectric layer 101 when the trench 105 is subsequently filled with conductive material, reducing the impact on the back-end circuit performance.
Here, the conformal coating means that the thickness of the thin film formed on each of the inclined patterns is the same regardless of the inclined pattern on the surface of the coated structure. Accordingly, forming the barrier layer 107 conformally covering the trench 105 means forming the same thickness of the barrier layer 107 on the bottom and sidewalls of the trench 105.
In this embodiment, the barrier layer 107 is formed by a physical vapor deposition process. The physical vapor deposition process has the advantages of low deposition temperature (usually below 550 ℃), high deposition speed, controllable composition and structure of a deposition layer, simple operation, high efficiency and low cost, and the physical vapor deposition process has high compatibility with the existing machine and process flow. In other embodiments, the barrier layer may also be formed using a chemical vapor deposition process or an atomic layer deposition process (Atomic Layer Deposition, ALD).
In this embodiment, the material of the barrier layer 107 is TaN. In other embodiments, the material of the barrier layer may be one or more of Ta, ti, tiN, zrN and zrtn.
It should be noted that the barrier layer 107 is not too thick or too thin. If the barrier layer 107 is too thick, the bottom of the trench 105 is not filled in the subsequent process of forming the second conductive layer in the trench 105, and the conductive material at the top of the trench 105 is in contact with the second conductive layer too early to close, so that the formed second conductive layer contains holes and occupies more space of the trench 105, so that the material of the second conductive layer 110 formed subsequently is less, and the conductivity of the interconnection structure is affected; if the barrier layer 107 is thin, then when a second conductive layer is formed in the trench 105, the barrier layer 107 is difficult to prevent the conductive material from penetrating into the dielectric layer 102, which may affect the back-end circuit performance. In this embodiment, the thickness of the barrier layer 107 is 10 to 40 a.
It should be noted that the barrier layer 107 is also formed on the sidewalls and the top wall of the mask layer 106, and the barrier layer 107 on the sidewalls and the top wall of the mask layer 106 is removed later in the step of forming the second conductive layer.
Referring to fig. 9, an adhesion layer 108 is conformally overlaid on the barrier layer 107. For increasing the adhesion strength of the subsequently formed liner layer to the barrier layer 107.
Conformally covering the adhesion layer 108 on the barrier layer 107 means that the adhesion layer 108 is formed with the same thickness throughout the barrier layer 107 in the trench 105.
In the subsequent process, a liner layer is conformally covered on the adhesion layer 108, the liner layer is formed by decomposing and depositing a precursor, the precursor contains carbonyl groups, the carbonyl groups decompose to generate C and O, the adhesion layer 108 is not easy to react with the C and O, and impurity compounds are not easy to generate, so that the adhesion between the adhesion layer 108 and the liner layer is good; since the adhesion layer 108 is between the liner layer and the barrier layer 107, C and O hardly react with the barrier layer 107 through the adhesion layer 108, and an impurity compound is hardly formed between the adhesion layer 108 and the barrier layer 107, adhesion between the adhesion layer 108 and the barrier layer 107 is good. Because the adhesion between the adhesion layer 108 and the barrier layer 107 and the liner layer 109 is good, the probability of generating holes between the adhesion layer 108 and the liner layer 109, and between the adhesion layer 108 and the barrier layer 107 is reduced, and accordingly, the probability of generating holes between the bottom of the second conductive layer 110 and the first conductive layer 100 is reduced, so that the reliability of the electrical connection between the second conductive layer 110 and the first conductive layer 100 can be improved, and thus the electrical reliability and yield of the semiconductor structure can be improved.
In this embodiment, the material of the adhesion layer 108 is Ru. In other embodiments, the material of the adhesion layer may also be W.
Because Ru is an inert Metal (Noble Metal), its surface activity is low, so impurity compounds rich in C and O are not easy to form at the interface between the adhesion layer 108 and the subsequently formed liner layer, and accordingly, the adhesion between the adhesion layer 108 and the liner layer is better than the adhesion when the barrier layer is in direct contact with the adhesion layer, thereby effectively reducing the probability of generating holes at the bottom of the subsequently formed second conductive layer after annealing treatment.
In this embodiment, the adhesion layer 108 is formed by a physical vapor deposition process. The physical vapor deposition process has the advantages of low deposition temperature (usually below 550 ℃), high deposition speed, controllable composition and structure of a deposition layer, simple operation, high efficiency and low cost, and the physical vapor deposition process has high compatibility with the existing machine and process flow. In other embodiments, an atomic layer deposition process may also be used to form the adhesion layer.
It should be noted that the adhesion layer 108 is not too thin or too thick. If the adhesion layer 108 is too thick, the bottom of the trench 105 is not filled in the subsequent process of forming the second conductive layer in the trench 105, and the conductive material at the top of the trench 105 is in contact with each other too early to close, so that the formed second conductive layer contains holes, and if the adhesion layer 108 is too thick, more space of the trench 105 is occupied, so that the material of the subsequently formed second conductive layer is less, and the conductivity of the interconnection structure is affected; if the adhesion layer 108 is thin, C and O in the formed subsequently formed liner layer easily pass through the adhesion layer 108 and react with the barrier layer 107 to form impurity compounds, so that the adhesion between the barrier layer 107 and the adhesion layer 108 is reduced, and holes are easily generated. In this embodiment, the thickness of the adhesion layer 108 is 10 to 20 a.
Referring to fig. 10, a liner layer 109 is conformally overlaid on the adhesion layer 108. The liner layer 109 serves as a wetting metal layer, so that the thickness of a seed layer subsequently formed on the liner layer 109 is uniform, preparation is made for subsequently forming a high-quality second conductive layer, and the difficulty in forming the second conductive layer in the trench 105 is reduced.
Conformally covering the liner layer 109 on the adhesion layer 108 means that the liner layer 109 is formed to the same thickness throughout the adhesion layer 108 in the trench 105.
In this embodiment, the material of the liner layer 109 includes Co. In other embodiments, the material of the lining layer may also be Al, W, ti.
In this embodiment, the liner layer 109 is formed by using an organometallic chemical vapor deposition (Metal-organic Chemical Vapor Deposition, MOCVD), and the organometallic chemical vapor deposition has good step coverage, so that the thickness uniformity of the formed liner layer 109 is good, the thickness of a seed layer formed subsequently is more uniform, and the coverage capability of the conductive material in the electroplating process is improved. In other embodiments, the liner layer may also be formed using an atomic layer deposition process.
The backing layer 109 is preferably not too thin or too thick. If the liner layer 109 is too thick, the bottom of the trench 105 is not filled in the subsequent process of forming the second conductive layer in the trench 105, and the conductive material at the top of the trench 105 is closed too early, so that the formed second conductive layer contains holes and occupies more space of the trench 105, so that the material of the subsequently formed second conductive layer 110 is less, and the conductivity of the interconnection structure is affected; if the liner layer 109 is thinner, the seed layer is formed with poor quality, so that the quality of the second conductive layer 110 is reduced, and the subsequent circuit performance is poor. In this embodiment, the thickness of the lining layer 109 is 10 to 40 a.
Referring to fig. 11 to 12, after the liner layer 109 is formed, a conductive material is filled in the trench 105 (shown in fig. 10), and a second conductive layer 110 (shown in fig. 12) is formed.
The second conductive layer 110 is used to electrically connect with the first conductive layer 100, thereby connecting the first conductive layer 100 to an external circuit.
Specifically, the step of forming the second conductive layer 110 includes: forming a seed layer (not shown) conformally overlying the liner layer 109; filling a conductive material into the trench 105 in which the seed layer is formed; the conductive material exposing the trench 105 is removed to form a second conductive layer 110. The conductive material exposing the trenches 105 is removed in preparation for subsequent formation of an etch resistant layer over the second conductive layer 110 and the dielectric layer 101.
The seed layer provides a good conductive layer for subsequent filling of the conductive material. In this embodiment, the material of the seed layer is Cu. In other embodiments, the material of the seed layer may also be aluminum or nickel.
In this embodiment, the trench 105 is filled with the conductive material by using an electrochemical plating process, which has the advantages of simple operation, fast deposition speed, low cost, and the like.
In this embodiment, a mechanical planarization process (Chemical-Mechanical Planarization, CMP) is used to remove the conductive material that exposes the trench 105, forming the second conductive layer 110.
Specifically, the planarization process is a chemical mechanical polishing process.
In the step of removing the conductive material exposing the trench 105 by using the planarization process, the mask layer 106 and the barrier layer 107 and the liner layer 109 on the mask layer 106 are also removed.
In this embodiment, the material of the second conductive layer 110 includes Cu. In other embodiments, the conductive material may also include Al or Co.
After the second conductive layer 110 is formed, a cap layer 111 is formed on the second conductive layer 110. The cap layer 111 and the second conductive layer 110 have a stable chemical bond therebetween, so that the adhesion between the cap layer 111 and the second conductive layer 110 is good, and therefore Cu atoms are difficult to diffuse rapidly between the cap layer 111 and the second conductive layer 110, and holes are difficult to be generated at the top of the second conductive layer 110, which further is difficult to affect the back-end circuit performance, thereby improving the electrical performance of the semiconductor structure.
The step of forming the cap layer 111 includes: forming a capping material layer (not shown) covering the second conductive layer 110 and the dielectric layer 101; after the cap material layer is formed, the cap material layer on the surface of the dielectric layer 101 is removed by a plasma dry etching process.
In this embodiment, the gas used in the dry plasma etching process is NH 3 . In other embodiments, the gas used in the dry plasma etching process may also be CF 4 、CHF 3 、CH 2 F 2 Or C 4 F 8 。
In this embodiment, the cap layer 111 is formed by an atomic layer deposition process or an organometallic chemical vapor deposition process.
In this embodiment, the material of the cap layer 111 is one or more of TaN, ta, ti, tiN, zrN and zrttin.
Referring to fig. 13, the method for forming the semiconductor structure further includes: after forming the second conductive layer 110, the semiconductor structure is annealed. The annealing process can release the stress of the first conductive layer 100 and the second conductive layer 110.
The process parameters of the annealing treatment comprise: the annealing temperature is 300 ℃ to 350 ℃.
The annealing process recrystallizes the Cu in the second conductive layer 110 and the Cu atoms polymerize, causing the second conductive layer 110 to have a tendency to disengage from the trench 105 (as shown in fig. 10) and form a hole. In this embodiment, the adhesion layer 108 is formed between the barrier layer 107 and the liner layer 109, and the adhesion layer 108 is not easy to react with C and O, and is not easy to generate impurity compounds, so that the adhesion between the adhesion layer 108 and the liner layer 109 is good; and because the adhesion layer 108 is between the liner layer 109 and the barrier layer 107, C and O hardly react with the barrier layer 107 through the adhesion layer 108, and an impurity compound is hardly formed between the adhesion layer 108 and the barrier layer 107, adhesion between the adhesion layer 108 and the barrier layer 107 is good. Because the adhesion between the adhesion layer 108 and the barrier layer 107 and the liner layer 109 is good, the probability of generating holes between the adhesion layer 108 and the liner layer 109, and between the adhesion layer 108 and the barrier layer 107, is reduced, and accordingly, the probability of generating holes between the bottom of the second conductive layer 110 and the first conductive layer 100 is reduced, so that the reliability of the electrical connection between the second conductive layer 110 and the first conductive layer 100 can be improved, and thus the electrical reliability and yield of the semiconductor structure can be improved.
After forming the second conductive layer 110, an etching resist layer 112 is formed to cover the second conductive layer 110 and the dielectric layer 101 before annealing the semiconductor structure. When an interlayer interconnect structure (Via) is subsequently formed on the etch-resistant layer 112, the etch-resistant layer 112 serves as an etch stop, and can prevent the second conductive layer 110 and the dielectric layer 101 from being damaged by subsequent process operations.
In this embodiment, the material of the anti-etching layer 112 is silicon nitride. In other embodiments, the material of the anti-etching layer may be SiON, siBCN, siCN, or the like. The etch-resistant layer 112 can reduce the capacitive coupling effect between the second conductive layer 110 and a conductive layer subsequently formed on the etch-resistant layer 112, thereby reducing the fringe parasitic capacitance.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 13, a schematic structure diagram of an embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate comprising a first conductive layer 100 and a dielectric layer 101 on the first conductive layer 100; a trench 105 (shown in fig. 10) in the dielectric layer 101 and exposing the first conductive layer 100; a barrier layer 107 conformally covering the bottom and sidewalls of the trench 105; an adhesion layer 108 conformally overlying the barrier layer 107; a backing layer 109 conformally overlying the adhesion layer 108; a second conductive layer 110 filled in the trench 105.
The lining layer 109 is formed by a precursor decomposition deposition mode, the lining layer 109 contains carbonyl groups, the carbonyl groups are decomposed to generate C and O, the adhesion layer 108 is not easy to react with the C and O, and impurity compounds are not easy to generate, so that the adhesion between the adhesion layer 108 and the lining layer 109 is good; since the adhesion layer 108 is between the liner layer and the barrier layer 107, C and O hardly react with the barrier layer 107 through the adhesion layer 108, and an impurity compound is hardly formed between the adhesion layer 108 and the barrier layer 107, so that the adhesion between the adhesion layer 108 and the barrier layer 107 is good. Because the adhesion between the adhesion layer 108 and the barrier layer 107 and the liner layer 109 is good, the probability of generating holes between the adhesion layer 108 and the liner layer 109, and between the adhesion layer 108 and the barrier layer 107, is reduced, and accordingly, the probability of generating holes between the bottom of the second conductive layer 110 and the first conductive layer 100 is reduced, so that the reliability of the electrical connection between the second conductive layer 110 and the first conductive layer 100 can be improved, and thus the electrical reliability and yield of the semiconductor structure can be improved.
In this embodiment, the material of the first conductive layer 100 is W. In other embodiments, the material of the first conductive layer may also be Al, co, or Cu.
The substrate further comprises: a bottom dielectric layer 104, the first conductive layer 100 being located in the bottom dielectric layer 104. The bottom dielectric layer 104 is used to achieve electrical isolation between the respective first conductive layers 100.
A dielectric layer 101 is located on the first conductive layer 100. The dielectric layer 101 serves to insulate the second conductive layer 110 formed in the dielectric layer 101 from each other.
The material Of the dielectric layer 101 is an Ultra Low K (ULK) dielectric material, where the Ultra Low K dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6, and the dielectric layer 101 is made Of an Ultra Low K dielectric material, which can effectively reduce parasitic capacitance between the second conductive layers 110, so as to reduce Back End Of Line (BEOL) RC delay. In this embodiment, the material of the dielectric layer 101 is silicon oxide containing pores. In other embodiments, the material of the dielectric layer may be SiOCH.
A trench 105 is located in the dielectric layer 101 and exposes the first conductive layer 100, and the barrier layer 107 conformally covers the bottom and sidewalls of the trench 105. The barrier layer 107 may reduce the probability of conductive material in the second conductive layer 110 diffusing into the dielectric layer 101, reduce the impact on the back-end circuit performance, and further improve the electrical performance of the semiconductor structure.
The barrier layer 107 conformally covers the bottom and sidewalls of the trench 105 means that the thickness of the barrier layer 107 on the bottom and sidewalls of the trench 105 is the same.
In this embodiment, the material of the barrier layer 107 is TaN. In other embodiments, the material of the barrier layer may be one or more of Ta, ti, tiN, zrN and zrtn.
It should be noted that the barrier layer 107 is not too thick or too thin. If the barrier layer 107 is too thick, holes are likely to exist in the formed second conductive layer 110, and more space of the trench 105 is occupied, so that the material of the formed second conductive layer 110 is likely to be less, and the conductivity of the interconnection structure is affected; if the barrier layer 107 is thin, the conductive material of the second conductive layer 110 is likely to penetrate into the dielectric layer 102 through the barrier layer 107, which may affect the back-end circuit performance. In this embodiment, the thickness of the barrier layer 107 is 10 to 40 a.
An adhesive layer 108 conformally covers the barrier layer 107 for increasing the bonding strength of the backing layer 109 to the barrier layer 107.
The adhesion layer 108 conformally covers the barrier layer 107 means that the adhesion layer 108 is formed with the same thickness throughout the barrier layer 107.
In this embodiment, the material of the adhesion layer 108 is Ru. In other embodiments, the material of the adhesion layer may also be W.
Since Ru is an inert Metal (Noble Metal), its surface activity is low, and thus impurity compounds rich in C and O are not easily formed at the interface of the adhesion layer 108 and the liner layer 109, and accordingly, the adhesion between the adhesion layer 108 and the liner layer is better than that when the barrier layer is in direct contact with the adhesion layer, thereby generating a probability of holes at the bottom of the second conductive layer 110.
It should be noted that the adhesion layer 108 is not too thin or too thick. If the adhesion layer 108 is too thick, holes are formed in the formed second conductive layer 110, and if the adhesion layer 108 is too thick, more space of the trench 105 is occupied, so that the material of the formed second conductive layer 110 is easy to be less, and the conductivity of the interconnection structure is affected; if the adhesion layer 108 is thinner, C and O in the liner layer 109 easily pass through the adhesion layer 108 on the sidewall of the trench 105, and react with the barrier layer 107 to generate impurity compounds, so that the adhesion between the barrier layer 107 and the adhesion layer 108 is reduced, and holes are easily generated. In this embodiment, the thickness of the adhesion layer 108 is 10 to 20 a.
A backing layer 109 conformally overlies the adhesion layer 108. The liner layer 109 serves as a wetting metal layer, so that the uniformity of the thickness of the formed seed layer is good, and further, the forming effect of the second conductive layer 110 is good, and the electromigration capability of the second conductive layer 110 can be improved.
The liner layer 109 is conformally coated on the adhesive layer 108, meaning that the liner layer 109 is formed with the same thickness throughout the adhesive layer 108.
In this embodiment, the material of the liner layer 109 includes Co. In other embodiments, the material of the backing layer may also include one or more of Al, W, ti.
The backing layer 109 is preferably not too thick or too thin. If the liner layer 109 is too thick, holes are likely to exist in the formed second conductive layer 110, and more space of the trench 105 is occupied, so that the material of the formed second conductive layer 110 is likely to be less, and the conductivity of the interconnection structure is affected; if the liner layer 109 is thinner, the seed layer is formed with poor quality, and thus holes are formed in the second conductive layer 110, resulting in poor back-end circuit performance. In this embodiment, the thickness of the lining layer is 10 to 40 a.
A seed layer (not shown) is located on the liner layer 109. The seed layer provides a good conductive layer when the second conductive layer 110.
In this embodiment, the material of the seed layer is Cu. In other embodiments, the material of the seed layer may also be Al or Ni.
A second conductive layer 110 fills in the trench 105. The second conductive layer 110 is used to electrically connect with the first conductive layer 100, thereby connecting the first conductive layer 110 to an external circuit.
In this embodiment, the material of the second conductive layer 110 is Cu, and in other embodiments, the second conductive layer may also be Al or Co.
The semiconductor structure further includes: and a cap layer 111 on the second conductive layer 110. The cap layer 111 and the second conductive layer 110 have a stable chemical bond therebetween, so that the cap layer 111 and the second conductive layer 110 have good adhesion. The Cu atoms are difficult to rapidly diffuse between the capping layer 111 and the second conductive layer 110 without creating holes on top of the second conductive layer 110.
In this embodiment, the material of the cap layer 111 is one or more of TaN, ta, ti, tiN, zrN and zrttin.
It should be noted that the substrate further includes: an etch stop layer 113 is located between the first conductive layer 100 and the dielectric layer 101, and the etch stop layer 113 exposes the first conductive layer 100, and the first conductive layer 100 is electrically connected to the second conductive layer 110.
In this embodiment, the material of the etching stop layer 113 is silicon nitride. In other embodiments, the material of the etching stop layer may be SiON, siBCN, siCN, or the like. The etch stop layer 113 can reduce the capacitive coupling effect between the first conductive layer 100 and the second conductive layer 110, thereby reducing the fringe parasitic capacitance.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the embodiments of the invention, and the scope of the embodiments of the invention should be pointed out in the appended claims.

Claims (18)

1. A method of forming a semiconductor structure, comprising:
providing a substrate comprising: a first conductive layer and a dielectric layer on the first conductive layer;
forming a mask layer on top of the dielectric layer;
etching the dielectric layer by taking the mask layer as a mask to form a groove which is positioned in the dielectric layer and exposes the first conductive layer;
forming a barrier layer conformally covering the trench;
conformally covering an adhesion layer on the barrier layer;
conformally covering a liner layer on the adhesion layer, the liner layer also formed on the mask layer;
after forming the lining layer, forming a seed layer which conformally covers the lining layer, and after forming the seed layer, forming a second conductive layer in the groove, wherein the step of forming the second conductive layer comprises the following steps: filling a conductive material into the trench formed with the seed layer, the conductive material also being formed on a liner layer; after the conductive material is formed, the conductive material exposing the trench, the mask layer, and the barrier layer and the liner layer on the mask layer are removed, and the remaining conductive material in the trench is used as a second conductive layer.
2. The method of claim 1, wherein the adhesion layer is formed of Ru or W.
3. The method of forming a semiconductor structure of claim 1, wherein the adhesion layer has a thickness of 10 to 20 a.
4. The method of forming a semiconductor structure of claim 1, wherein the adhesion layer is formed using an atomic layer deposition process or a physical vapor deposition process.
5. The method of forming a semiconductor structure of claim 1, wherein the barrier layer is formed using a physical vapor deposition process.
6. The method of forming a semiconductor structure of claim 1 wherein the material of the barrier layer is one or more of TaN, ta, ti, tiN, zrN and ZrTiN.
7. The method of forming a semiconductor structure of claim 1, wherein the barrier layer has a thickness of 10 to 40 a.
8. The method of forming a semiconductor structure of claim 1, wherein the material of the liner layer comprises one or more of Co, al, W, and Ti.
9. The method of forming a semiconductor structure of claim 1, wherein the liner layer is formed using a chemical vapor deposition process.
10. The method of forming a semiconductor structure of claim 1, wherein a thickness of the liner layer is from 10 to 40 angstroms.
11. The method of forming a semiconductor structure of claim 1, wherein the material of the second conductive layer comprises Cu, al, or Co.
12. The method of forming a semiconductor structure of claim 1, wherein the trench is filled with a conductive material using an electrochemical plating process.
13. The method of forming a semiconductor structure of claim 1, further comprising: and annealing the semiconductor structure after the second conductive layer is formed.
14. A semiconductor structure formed by the method of any one of claims 1 to 13, comprising:
a substrate comprising a first conductive layer and a dielectric layer on the first conductive layer;
a trench in the dielectric layer exposing the first conductive layer;
a barrier layer conformally covering the bottom and sidewalls of the trench;
an adhesion layer conformally overlying the barrier layer;
a backing layer conformally overlying the adhesive layer;
a seed layer conformally overlying the liner layer;
and the second conductive layer is filled in the groove.
15. The semiconductor structure of claim 14, wherein the adhesion layer is of a material Ru
Or W.
16. The semiconductor structure of claim 14, wherein the adhesion layer has a thickness of 10 to 20 angstroms.
17. The semiconductor structure of claim 14 wherein the material of the barrier layer is one or more of TaN, ta, ti, tiN, zrN and zrtn.
18. The semiconductor structure of claim 14, wherein the material of the liner layer comprises one or more of Co, al, W, and Ti.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9177858B1 (en) * 2014-05-08 2015-11-03 GlobalFoundries, Inc. Methods for fabricating integrated circuits including barrier layers for interconnect structures
CN108735797A (en) * 2017-04-25 2018-11-02 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9177858B1 (en) * 2014-05-08 2015-11-03 GlobalFoundries, Inc. Methods for fabricating integrated circuits including barrier layers for interconnect structures
CN108735797A (en) * 2017-04-25 2018-11-02 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

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