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CN111383990A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN111383990A
CN111383990A CN201811621152.8A CN201811621152A CN111383990A CN 111383990 A CN111383990 A CN 111383990A CN 201811621152 A CN201811621152 A CN 201811621152A CN 111383990 A CN111383990 A CN 111383990A
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layer
conductive
forming
semiconductor structure
adhesion
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CN111383990B (en
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吴轶超
张天豪
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate comprising: a first conductive layer and a dielectric layer on the first conductive layer; forming a groove which is positioned in the dielectric layer and exposes the first conducting layer; forming a barrier layer conformally covering the trench; conformally covering an adhesion layer on the barrier layer; conformally covering a backing layer over the adhesive layer; and forming a second conductive layer in the groove after the liner layer is formed. Because the adhesion between adhesion layer and barrier layer and the backing layer is good, so between adhesion layer and the backing layer, and the probability that produces the hole between adhesion layer and the barrier layer reduces, correspondingly, the probability that produces the hole between second conducting layer and the dielectric layer reduces, the electromigration of second conducting layer and the interface department of dielectric layer is good, can improve the reliability and the yields of device.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
As semiconductor manufacturing technology becomes more sophisticated, integrated circuits have also undergone significant changes, and the number of components integrated on the same chip has increased from the first tens, hundreds to the present millions. In order to meet the circuit density requirements, the fabrication process of semiconductor integrated circuit chips utilizes batch processing techniques to form various types of complex devices on a substrate and interconnect them for complete electronic functionality, mostly using ultra-low k interlevel dielectric layers between conductive lines as the dielectric material for isolating the metal interconnects, and interconnect structures for providing wiring between the devices on the IC chip and the entire package. In this technique, devices such as Field Effect Transistors (FETs) are first formed on the surface of a semiconductor substrate, and then interconnect structures are formed in Back End of Line (BEOL) fabrication processes for integrated circuits.
As moore's law predicts, the shrinking dimensions of semiconductor substrates and the formation of more transistors on semiconductor substrates to improve device performance, the use of interconnect structures to connect the transistors is a necessary option. However, compared with the miniaturization and the increase of the integration of components, the number of conductor connecting lines in the circuit is continuously increased, the forming quality of the interconnection structure has great influence on the reliability of circuit connection, and the normal operation of the semiconductor device can be seriously influenced.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which optimize electrical properties of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate comprising: a first conductive layer and a dielectric layer on the first conductive layer; forming a groove which is positioned in the dielectric layer and exposes the first conducting layer; forming a barrier layer conformally covering the trench; conformally covering an adhesion layer on the barrier layer; conformally covering a backing layer over the adhesive layer; and forming a second conductive layer in the groove after the liner layer is formed.
Optionally, the material of the adhesion layer is Ru or W.
Optionally, the adhesion layer has a thickness of 10 to 20 angstroms.
Optionally, the adhesion layer is formed by an atomic layer deposition process or a physical vapor deposition process.
Optionally, a physical vapor deposition process is used to form the barrier layer.
Optionally, the barrier layer is made of one or more of TaN, Ta, Ti, TiN, ZrN, and ZrTiN.
Optionally, the barrier layer has a thickness of 10 to 40 angstroms.
Optionally, the material of the liner layer comprises one or more of Co, Al, W and Ti.
Optionally, the liner layer is formed using a chemical vapor deposition process.
Optionally, the liner layer has a thickness of 10 to 40 angstroms.
Optionally, the material of the second conductive layer includes Cu, Al, or Co.
Optionally, the step of forming the second conductive layer includes: forming a seed layer conformally covering the liner layer; filling a conductive material into the groove formed with the seed layer; and removing the conductive material exposing the groove to form a second conductive layer.
Optionally, an electrochemical plating process is used to fill the trench with a conductive material.
Optionally, the method for forming the semiconductor structure further includes: and after the second conductive layer is formed, annealing the semiconductor structure.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate comprising a first conductive layer and a dielectric layer on the first conductive layer; a trench in the dielectric layer exposing the first conductive layer; the barrier layer is covered on the bottom and the side wall of the groove in a shape-preserving manner; an adhesion layer conformally covering the barrier layer; a liner layer conformally covering the adhesive layer; and the second conducting layer is filled in the groove.
Optionally, the material of the adhesion layer is Ru or W.
Optionally, the adhesion layer has a thickness of 10 to 20 angstroms.
Optionally, the barrier layer is made of one or more of TaN, Ta, Ti, TiN, ZrN, and ZrTiN.
Optionally, the material of the liner layer comprises one or more of Co, Al, W and Ti.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
after a groove is formed in a dielectric layer, a barrier layer which conformally covers the groove is formed, and an adhesion layer is conformally covered on the barrier layer; conformally covering a liner layer on the adhesive layer, and forming a second conductive layer in the groove after forming the liner layer. C and O are generally generated during the formation of the backing layer, the adhesive layer does not react with C and O, and impurity compounds are not easily generated, so that the adhesion between the adhesive layer and the backing layer is good; since the adhesive layer is between the liner layer and the barrier layer, C and O are difficult to react with the barrier layer through the adhesive layer, and impurity compounds are not easily formed between the adhesive layer and the barrier layer, so that the adhesion between the adhesive layer and the barrier layer is good. Because the adhesion between the adhesion layer and the barrier layer and the lining layer is good, the probability of generating holes between the adhesion layer and the lining layer and between the adhesion layer and the barrier layer is reduced, and correspondingly, the probability of generating holes between the bottom of the second conductive layer and the first conductive layer is reduced, so that the reliability of the electrical connection between the second conductive layer and the first conductive layer can be improved, and the electrical reliability and the yield of the semiconductor structure can be improved.
Drawings
Fig. 1 to 5 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
fig. 6 to 13 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As can be seen from the background art, the performance of the devices formed at present is still not good. The reason for the poor performance of the device is analyzed in combination with a method for forming a semiconductor structure.
Referring to fig. 1 to 5, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
Referring to fig. 1, a substrate is provided, which includes a first conductive layer 1, an anti-etching layer 10 on the first conductive layer 1, a dielectric layer 2 on the anti-etching layer 10, and a mask layer 3 on the dielectric layer 2.
Referring to fig. 2, the dielectric layer 2 and the mask layer 3 on the dielectric layer 2 are etched to form a trench 4 exposing the first conductive layer 1.
Referring to fig. 3, a barrier layer 5 is formed conformally covering the trench 4; a liner layer 6 is conformally covered on the barrier layer 5.
The barrier layer 5 is made of TaN; the material of the liner layer 6 is Co.
Specifically, the barrier layer 5 is formed by a Physical Vapor Deposition (PVD) process, and the liner layer 6 is formed by a Chemical Vapor Deposition (CVD) process.
Referring to fig. 4, a seed layer (not shown) is formed to conformally cover the liner layer 6, and the trench 4 formed with the seed layer is filled with a conductive material; and removing the conductive material layer exposing the groove 4 to form a second conductive layer 7.
The material of the second conductive layer 7 is Cu.
Referring to fig. 5, a top barrier layer 8 is formed on the second conductive layer 7; after the top barrier layer 8 is formed, an etch resist layer 9 is formed overlying the top barrier layer 8 and the dielectric layer 2.
The liner layer 6 is formed by a Precursor (Precursor), the liner layer 6 contains a carbonyl, and C and O formed by decomposition of the carbonyl react with the barrier layer 5 to form impurity compounds. Since the trench 4 has a high aspect ratio (AspectRatio), the bottom of the second conductive layer 7 has a higher probability of generating defects than other portions of the second conductive layer 7 during the formation of the second conductive layer 7, and therefore impurity compounds are easily formed at the bottom of the trench 4, so that the adhesion between the barrier layer 5 and the liner layer 6 at the bottom of the second conductive layer 7 is poor. Subsequently, the semiconductor structure is annealed, and the annealing process causes the Cu in the second conductive layer 7 to recrystallize, and Cu atoms polymerize to make the volume of the second conductive layer 7 smaller, so that the liner layer 6 at the bottom of the trench 4 is finally separated from the barrier layer 5 and a hole 11 is generated (as shown in fig. 5).
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate comprising: a first conductive layer and a dielectric layer on the first conductive layer; forming a groove which is positioned in the dielectric layer and exposes the first conducting layer; forming a barrier layer conformally covering the trench; conformally covering an adhesion layer on the barrier layer; conformally covering a backing layer over the adhesive layer; and forming a second conductive layer in the groove after the liner layer is formed.
After a groove is formed in a dielectric layer, a barrier layer which conformally covers the groove is formed, and an adhesion layer is conformally covered on the barrier layer; and conformally covering a lining layer on the adhesive layer, and filling a conductive material in the groove after the lining layer is formed to form a second conductive layer. C and O are generally generated during the formation of the backing layer, the adhesive layer does not react with C and O, and impurity compounds are not easily generated, so that the adhesion between the adhesive layer and the backing layer is good; since the adhesive layer is between the liner layer and the barrier layer, C and O are difficult to react with the barrier layer through the adhesive layer, and impurity compounds are not easily formed between the adhesive layer and the barrier layer, so that the adhesion between the adhesive layer and the barrier layer is good. Because the adhesion between the adhesion layer and the barrier layer and the lining layer is good, the probability of generating holes between the adhesion layer and the lining layer and between the adhesion layer and the barrier layer is reduced, and correspondingly, the probability of generating holes between the bottom of the second conductive layer and the first conductive layer is reduced, so that the reliability of the electrical connection between the second conductive layer and the first conductive layer can be improved, and the electrical reliability and the yield of the semiconductor structure can be improved.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 6 to 13 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 6, a substrate is provided, the substrate comprising: a first conductive layer 100 and a dielectric layer 101 on the first conductive layer 100.
The first conductive layer 100 is a structure to be connected. In this embodiment, the material of the first conductive layer 100 is W. In other embodiments, the material of the first conductive layer may also be Al, Co, or Cu.
It should be noted that the substrate further includes: a bottom dielectric layer 104, the first conductive layer 100 being located in the bottom dielectric layer 104. The bottom dielectric layer 104 is used to achieve insulation between the respective first conductive layers 100. The dielectric layer 101 is used to realize insulation between subsequently formed second conductive layers.
The dielectric layer 101 is made Of an Ultra Low K (ULK) dielectric material, where the ultra low K dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6, and the dielectric layer 101 is made Of the ultra low K dielectric material, so that the parasitic capacitance Of the second conductive layer formed subsequently can be effectively reduced, and the Back End Of Line (BEOL) RC delay is further reduced.
The step of forming the dielectric layer 101 includes: forming a dielectric material layer (not labeled) on the first conductive layer 100, the dielectric material layer including a thermally stable material and a thermally unstable pore-forming agent; the dielectric material layer is annealed at a temperature between the decomposition temperature of the thermally unstable material and the curing temperature of the thermally stable material, so that the thermally unstable material is decomposed and volatilized to form the single-phase pore-filled dielectric layer 101. In this embodiment, the thermally stable material is a precursor of silicon oxide.
In other embodiments, the dielectric layer may be formed directly, and the material of the dielectric layer may be SiOCH.
It should be noted that the substrate further includes: and a mask material layer 103 formed on the dielectric layer 101. The masking material layer 103 is used to prepare for subsequent etching of the dielectric layer 101 to form a trench.
It should be noted that the substrate further includes: and an etching stop material layer 102 formed between the first conductive layer 100 and the dielectric layer 101.
In the subsequent process of etching the dielectric layer 101 to form a trench, the top surface of the etch stop material layer 102 is used to define an etch stop position, and the etch stop material layer 102 has a higher etch selectivity than the dielectric layer 101, so that a good etch stop effect is achieved, and the problem of excessive etching or insufficient etching caused by inconsistent etching rates of various regions can be avoided.
In this embodiment, the material of the etching stop material layer 102 is silicon nitride. In other embodiments, the material of the etching stop material layer may be SiON, SiBCN, or SiCN. The etching stop material layer 102 can reduce the capacitive coupling effect between the first conductive layer 100 and a subsequently formed second conductive layer, thereby reducing the edge parasitic capacitance.
Referring to fig. 7, a trench 105 is formed within the dielectric layer 101 and exposing the first conductive layer 100.
In this embodiment, the dielectric layer 101 is etched by a dry etching process to form a trench 105. Specifically, the dry etching process is a plasma dry etching process.
In this embodiment, the etching gas used in the plasma dry etching process is CF4、CHF3、CH2F2Or C4F8The gas flow of the etching gas is 10sccm to 200 sccm; the auxiliary gas used is O2The gas flow of the auxiliary gas is 0sccm to 100 sccm; the diluent gas used is N2CO, He or Ar, orThe gas flow of the diluent gas is 10sccm to 1000 sccm; the process pressure is 10mTorr to 200 mTorr.
It should be noted that the step of forming the trench 105 by etching the dielectric layer 101 includes: firstly, etching the mask material layer 103 on the dielectric layer 101 to form a mask layer 106; and etching the dielectric layer 101 by taking the mask layer 106 as a mask, and forming a groove 105 in the dielectric layer 101.
It should be further noted that the method for forming the semiconductor structure further includes: after the trench 105 is formed, the etching stop material layer 102 is continuously etched by using the mask layer 106 as a mask, so that an etching stop layer 113 exposing the first conductive layer 100 is formed.
Referring to fig. 8, a barrier layer 107 is formed conformally covering the trench 105. The barrier layer 107 reduces the probability of conductive material diffusing into the dielectric layer 101 during subsequent filling of the trench 105 with conductive material, reducing the impact on the performance of the back-end circuitry.
Here, the conformal coating means that the thickness of the thin film formed on each portion of the inclined pattern is the same regardless of the inclined pattern on the surface of the structure to be coated. Accordingly, forming the barrier layer 107 to conformally cover the trench 105 means that the same thickness of the barrier layer 107 is formed on the bottom and sidewalls of the trench 105.
In this embodiment, the barrier layer 107 is formed by a physical vapor deposition process. The physical vapor deposition process has the advantages of low deposition temperature (usually below 550 ℃), high deposition speed, controllable components and structure of a deposition layer, simple operation, high efficiency and low cost, and the physical vapor deposition process has high compatibility with the existing machine and process flow. In other embodiments, the barrier Layer may be formed by chemical vapor Deposition (cvd) or Atomic Layer Deposition (ALD).
In this embodiment, the material of the barrier layer 107 is TaN. In other embodiments, the material of the barrier layer may be one or more of Ta, Ti, TiN, ZrN, and ZrTiN.
It should be noted that the barrier layer 107 is not too thick nor too thin. If the blocking layer 107 is too thick, the bottom of the trench 105 is not filled during the subsequent process of forming the second conductive layer in the trench 105, and the conductive material at the top of the trench 105 is prematurely contacted to achieve closing, so that the formed second conductive layer contains holes and occupies more space of the trench 105, which is easy to reduce the material of the subsequently formed second conductive layer 110, thereby affecting the conductivity of the interconnection structure; if the barrier layer 107 is thin, it is difficult for the barrier layer 107 to prevent conductive material from penetrating into the dielectric layer 102 when a second conductive layer is subsequently formed in the trench 105, which may affect the performance of the back-end circuit. In this embodiment, the thickness of the barrier layer 107 is 10 to 40 angstroms.
It should be noted that the blocking layer 107 is also formed on the side wall and the top wall of the mask layer 106, and the blocking layer 107 on the side wall and the top wall of the mask layer 106 is subsequently removed in the step of forming the second conductive layer.
Referring to fig. 9, an adhesion layer 108 is conformally covered on the barrier layer 107. For increasing the strength of the subsequent liner layer to conform to the barrier layer 107.
Conformal coverage of adhesion layer 108 over the barrier layer 107 means that the same thickness of adhesion layer 108 is formed throughout the barrier layer 107 in the trench 105.
In the subsequent process, a liner layer is conformally covered on the adhesive layer 108, the liner layer is formed by a precursor decomposition deposition mode, the precursor contains carbonyl, C and O are generated by the decomposition of the carbonyl, the adhesive layer 108 is not easy to react with the C and the O, and impurity compounds are not easy to generate, so that the adhesion between the adhesive layer 108 and the liner layer is good; since the adhesive layer 108 is between the liner layer and the barrier layer 107, C and O are difficult to react with the barrier layer 107 through the adhesive layer 108, and it is difficult to form impurity compounds between the adhesive layer 108 and the barrier layer 107, and thus the adhesion between the adhesive layer 108 and the barrier layer 107 is good. Since the adhesion between the adhesive layer 108 and the barrier layer 107 and the liner layer 109 is good, the probability of generating voids between the adhesive layer 108 and the liner layer 109 and between the adhesive layer 108 and the barrier layer 107 is reduced, and accordingly, the probability of generating voids between the bottom of the second conductive layer 110 and the first conductive layer 100 is reduced, so that the reliability of the electrical connection between the second conductive layer 110 and the first conductive layer 100 can be improved, and the electrical reliability and the yield of the semiconductor structure can be improved.
In this embodiment, the material of the adhesion layer 108 is Ru. In other embodiments, the material of the adhesion layer may also be W.
Because Ru is an inert Metal (Noble Metal), its surface activity is low, so impurity compounds rich in C and O are not easily formed at the boundary between the adhesion layer 108 and the subsequently formed liner layer, and accordingly, the adhesion between the adhesion layer 108 and the liner layer is better than that when the barrier layer is in direct contact with the adhesion layer, thereby effectively reducing the probability of generating voids at the bottom of the subsequently formed second conductive layer after the annealing treatment.
In this embodiment, the adhesion layer 108 is formed by a physical vapor deposition process. The physical vapor deposition process has the advantages of low deposition temperature (usually below 550 ℃), high deposition speed, controllable components and structure of a deposition layer, simple operation, high efficiency and low cost, and the physical vapor deposition process has high compatibility with the existing machine and process flow. In other embodiments, an atomic layer deposition process may also be used to form the adhesion layer.
It should be noted that the adhesion layer 108 is not too thin nor too thick. If the adhesion layer 108 is too thick, the bottom of the trench 105 is not filled with the conductive material during the subsequent formation of the second conductive layer in the trench 105, and the conductive material at the top of the trench 105 contacts prematurely to be closed, so that the formed second conductive layer contains holes, and if the adhesion layer 108 is too thick, the space occupied by the formed second conductive layer is large, so that the material of the subsequently formed second conductive layer is easy to be small, and the conductivity of the interconnection structure is affected; if the adhesive layer 108 is thin, C and O in the formed liner layer to be formed later are likely to pass through the adhesive layer 108 to react with the barrier layer 107 to form impurity compounds, so that the adhesion between the barrier layer 107 and the adhesive layer 108 is reduced, and voids are likely to be generated. In this embodiment, the adhesion layer 108 has a thickness of 10 to 20 angstroms.
Referring to fig. 10, a liner layer 109 is conformally covered on the adhesive layer 108. The liner layer 109 acts as a wetting metal layer, so that a seed layer subsequently formed on the liner layer 109 has a uniform thickness, thereby providing for the subsequent formation of a high-quality second conductive layer and reducing the difficulty of forming the second conductive layer in the trench 105.
By conformally covering the liner layer 109 on the adhesive layer 108 is meant that the liner layer 109 is formed to the same thickness throughout the adhesive layer 108 in the trench 105.
In this embodiment, the material of the liner layer 109 comprises Co. In other embodiments, the material of the liner layer may also be Al, W, Ti.
In this embodiment, a Metal-organic Chemical vapor deposition (MOCVD) process is used to form the liner layer 109, and the Metal-organic Chemical vapor deposition process has good step coverage, so that the thickness uniformity of the formed liner layer 109 is good, the thickness of the subsequently formed seed layer is uniform, and the coverage of the conductive material during the electroplating process is improved. In other embodiments, the liner layer can also be formed using an atomic layer deposition process.
It should be noted that the liner layer 109 is not too thin nor too thick. If the liner layer 109 is too thick, the bottom of the trench 105 is not filled during the subsequent process of forming the second conductive layer in the trench 105, and the conductive material on the top of the trench 105 contacts prematurely to close, so that the formed second conductive layer contains voids and occupies more space of the trench 105, which easily causes less material of the subsequently formed second conductive layer 110, thereby affecting the conductivity of the interconnect structure; if the liner layer 109 is thinner, the quality of the seed layer formed is poor, and the quality of the second conductive layer 110 formed is reduced, so that the performance of the back-end circuit is poor. In this embodiment, the liner layer 109 has a thickness of 10 to 40 angstroms.
Referring to fig. 11 to 12, after the liner layer 109 is formed, the trench 105 (shown in fig. 10) is filled with a conductive material to form a second conductive layer 110 (shown in fig. 12).
The second conductive layer 110 is used to electrically connect with the first conductive layer 100, thereby connecting the first conductive layer 100 to an external circuit.
Specifically, the step of forming the second conductive layer 110 includes: forming a seed layer (not shown) conformally covering the liner layer 109; filling a conductive material into the trench 105 formed with the seed layer; the conductive material exposing the trench 105 is removed to form a second conductive layer 110. The conductive material exposing the trench 105 is removed in preparation for a subsequent formation of an etch-resistant layer on the second conductive layer 110 and the dielectric layer 101.
The seed layer provides a good conductive layer for subsequent filling with conductive material. In this embodiment, the seed layer is made of Cu. In other embodiments, the material of the seed layer may also be aluminum or nickel.
In this embodiment, the groove 105 is filled with a conductive material by an electrochemical plating process, which has the advantages of simple operation, fast deposition speed, low cost, etc.
In this embodiment, a Mechanical Planarization process (CMP) is used to remove the conductive material exposing the trench 105, so as to form the second conductive layer 110.
Specifically, the planarization process is a chemical mechanical polishing process.
It should be noted that, in the step of removing the conductive material exposing the trench 105 by using the planarization process, the mask layer 106, and the barrier layer 107 and the liner layer 109 on the mask layer 106 are also removed.
In this embodiment, the material of the second conductive layer 110 includes Cu. In other embodiments, the conductive material may also include Al or Co.
After the second conductive layer 110 is formed, a cap layer 111 is formed on the second conductive layer 110. The cap layer 111 and the second conductive layer 110 have a stable chemical bond, so that the cap layer 111 and the second conductive layer 110 have good adhesion, Cu atoms are difficult to diffuse rapidly between the cap layer 111 and the second conductive layer 110, holes are difficult to be generated at the top of the second conductive layer 110, the performance of a back-end circuit is not easily affected, and the electrical performance of a semiconductor structure is improved.
The step of forming the cap layer 111 includes: forming a cap material layer (not shown) covering the second conductive layer 110 and the dielectric layer 101; after the cap material layer is formed, the cap material layer on the surface of the dielectric layer 101 is removed by a plasma dry etching process.
In this embodiment, the gas used in the plasma dry etching process is NH3. In other embodiments, the gas used in the plasma dry etching process may also be CF4、CHF3、CH2F2Or C4F8。
In this embodiment, the cap layer 111 is formed by an atomic layer deposition process or an organic metal chemical vapor deposition process.
In this embodiment, the capping layer 111 is made of one or more of TaN, Ta, Ti, TiN, ZrN, and ZrTiN.
Referring to fig. 13, the method of forming the semiconductor structure further includes: after the second conductive layer 110 is formed, an annealing process is performed on the semiconductor structure. The annealing process can relieve stress of the first conductive layer 100 and the second conductive layer 110.
The process parameters of the annealing treatment comprise: the annealing temperature is 300 ℃ to 350 ℃.
The annealing process causes the Cu in the second conductive layer 110 to recrystallize, and Cu atoms polymerize, so that the second conductive layer 110 has a tendency to be separated from the trench 105 (as shown in fig. 10) to form a hole. In this embodiment, the adhesive layer 108 is formed between the barrier layer 107 and the liner layer 109, and the adhesive layer 108 is less likely to react with C and O and less likely to generate impurity compounds, and therefore, the adhesiveness between the adhesive layer 108 and the liner layer 109 is good; and since the adhesive layer 108 is between the liner layer 109 and the barrier layer 107, C and O are difficult to react with the barrier layer 107 through the adhesive layer 108, and it is difficult to form impurity compounds between the adhesive layer 108 and the barrier layer 107, so that the adhesion between the adhesive layer 108 and the barrier layer 107 is good. Since the adhesion between the adhesive layer 108 and the barrier layer 107 and the liner layer 109 is good, the probability of generating voids between the adhesive layer 108 and the liner layer 109 and between the adhesive layer 108 and the barrier layer 107 is reduced, and accordingly, the probability of generating voids between the bottom of the second conductive layer 110 and the first conductive layer 100 is reduced, so that the reliability of the electrical connection between the second conductive layer 110 and the first conductive layer 100 can be improved, and the electrical reliability and the yield of the semiconductor structure can be improved.
After the second conductive layer 110 is formed, and before the semiconductor structure is annealed, an anti-etching layer 112 covering the second conductive layer 110 and the dielectric layer 101 is formed. When an inter-layer interconnect structure (Via) is subsequently formed on the etch-resistant layer 112, the etch-resistant layer 112 stops etching, so as to prevent subsequent process operations from damaging the second conductive layer 110 and the dielectric layer 101.
In this embodiment, the material of the anti-etching layer 112 is silicon nitride. In other embodiments, the material of the etching resist layer may be SiON, SiBCN, SiCN, or the like. The anti-etching layer 112 can reduce the capacitive coupling effect between the second conductive layer 110 and a conductive layer subsequently formed on the anti-etching layer 112, thereby reducing the edge parasitic capacitance.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 13, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate comprising a first conductive layer 100 and a dielectric layer 101 on the first conductive layer 100; a trench 105 (shown in fig. 10) in the dielectric layer 101 and exposing the first conductive layer 100; a barrier layer 107 conformally covering the bottom and sidewalls of the trench 105; an adhesion layer 108 conformally covering the barrier layer 107; a liner layer 109 conformally covering the adhesive layer 108; and a second conductive layer 110 filled in the trench 105.
The liner layer 109 is formed by precursor decomposition deposition, the liner layer 109 contains carbonyl, the carbonyl decomposes to generate C and O, the adhesive layer 108 is not easy to react with the C and O, and impurity compounds are not easy to generate, so that the adhesion between the adhesive layer 108 and the liner layer 109 is good; since the adhesive layer 108 is between the liner layer and the barrier layer 107, C and O are difficult to react with the barrier layer 107 through the adhesive layer 108, and it is difficult to form impurity compounds between the adhesive layer 108 and the barrier layer 107, and thus the adhesion between the adhesive layer 108 and the barrier layer 107 is good. Since the adhesion between the adhesive layer 108 and the barrier layer 107 and the liner layer 109 is good, the probability of generating voids between the adhesive layer 108 and the liner layer 109 and between the adhesive layer 108 and the barrier layer 107 is reduced, and accordingly, the probability of generating voids between the bottom of the second conductive layer 110 and the first conductive layer 100 is reduced, so that the reliability of the electrical connection between the second conductive layer 110 and the first conductive layer 100 can be improved, and the electrical reliability and the yield of the semiconductor structure can be improved.
In this embodiment, the material of the first conductive layer 100 is W. In other embodiments, the material of the first conductive layer may also be Al, Co, or Cu.
The substrate further comprises: a bottom dielectric layer 104, the first conductive layer 100 being located in the bottom dielectric layer 104. The bottom dielectric layer 104 is used to achieve electrical isolation between the respective first conductive layers 100.
A dielectric layer 101 is located on the first conductive layer 100. The dielectric layer 101 serves to insulate the second conductive layers 110 formed in the dielectric layer 101 from each other.
The dielectric layer 101 is made Of an Ultra Low K (ULK) dielectric material, the Ultra Low K dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6, and the dielectric layer 101 is made Of the Ultra Low K dielectric material, so that the parasitic capacitance between the second conductive layers 110 can be effectively reduced, and the Back End Of Line (BEOL) RC delay is further reduced. In this embodiment, the material of the dielectric layer 101 is silicon oxide containing pores. In other embodiments, the material of the dielectric layer may be SiOCH.
A trench 105 is in the dielectric layer 101 and exposes the first conductive layer 100, and the barrier layer 107 conformally covers the bottom and sidewalls of the trench 105. The barrier layer 107 can reduce the probability of the conductive material in the second conductive layer 110 diffusing into the dielectric layer 101, and reduce the influence on the performance of the back-end circuit, thereby improving the electrical performance of the semiconductor structure.
The conformal coverage of the barrier layer 107 over the bottom and sidewalls of the trench 105 means that the thickness of the barrier layer 107 is the same at the bottom and sidewalls of the trench 105.
In this embodiment, the material of the barrier layer 107 is TaN. In other embodiments, the material of the barrier layer may be one or more of Ta, Ti, TiN, ZrN, and ZrTiN.
It should be noted that the barrier layer 107 is not too thick nor too thin. If the blocking layer 107 is too thick, the second conductive layer 110 is prone to have voids and occupy more space of the trench 105, which tends to result in less material for forming the second conductive layer 110, and thus the conductivity of the interconnect structure is affected; if the barrier layer 107 is thin, the conductive material of the second conductive layer 110 may easily penetrate through the barrier layer 107 into the dielectric layer 102, which may affect the performance of the back-end circuit. In this embodiment, the thickness of the barrier layer 107 is 10 to 40 angstroms.
An adhesive layer 108 conformally covers the barrier layer 107 for increasing the strength of the adhesion of the liner layer 109 to the barrier layer 107.
The fact that the adhesion layer 108 conformally covers the barrier layer 107 means that the adhesion layer 108 is formed to the same thickness throughout the barrier layer 107.
In this embodiment, the material of the adhesion layer 108 is Ru. In other embodiments, the material of the adhesion layer may also be W.
Since Ru is an inert Metal (Noble Metal), its surface activity is low, so impurity compounds rich in C and O are not easily formed at the interface of the adhesive layer 108 and the liner layer 109, and accordingly, the adhesion between the adhesive layer 108 and the liner layer is better than that when the barrier layer and the adhesive layer are in direct contact, thereby generating a void at the bottom of the second conductive layer 110.
It should be noted that the adhesion layer 108 is not too thin nor too thick. If the adhesion layer 108 is too thick, the second conductive layer 110 may contain holes, and if the adhesion layer 108 is too thick, the adhesion layer occupies more space in the trench 105, which may easily cause the material of the second conductive layer 110 to be less, thereby affecting the conductivity of the interconnect structure; if the adhesive layer 108 is thin, C and O in the liner layer 109 easily penetrate through the adhesive layer 108 on the side wall of the trench 105, react with the barrier layer 107 to generate impurity compounds, so that the adhesion between the barrier layer 107 and the adhesive layer 108 is reduced, and voids are easily generated. In this embodiment, the adhesion layer 108 has a thickness of 10 to 20 angstroms.
A liner layer 109 conformally covers the adhesive layer 108. The liner layer 109 is used as a wetting metal layer, so that the thickness uniformity of the formed seed layer is good, the forming effect of the second conductive layer 110 is good, and the electromigration capability of the second conductive layer 110 can be improved.
The liner layer 109 conformally covering the adhesive layer 108 means that the liner layer 109 is formed to the same thickness everywhere on the adhesive layer 108.
In this embodiment, the material of the liner layer 109 comprises Co. In other embodiments, the material of the liner layer may also include one or more of Al, W, Ti.
It should be noted that the liner layer 109 is not too thick nor too thin. If the liner layer 109 is too thick, the second conductive layer 110 is prone to have voids and occupy more space in the trench 105, which tends to result in less material for the second conductive layer 110, and thus the conductivity of the interconnect structure is affected; if the liner layer 109 is thin, the quality of the formed seed layer is poor, and a hole is generated in the formed second conductive layer 110, so that the performance of the back-end circuit is poor. In this embodiment, the thickness of the backing layer is 10 to 40 angstroms.
A seed layer (not shown) is located on the liner layer 109. The seed layer provides a good conductive layer when the second conductive layer 110 is present.
In this embodiment, the seed layer is made of Cu. In other embodiments, the material of the seed layer may also be Al or Ni.
The second conductive layer 110 is filled in the trench 105. The second conductive layer 110 is used to electrically connect with the first conductive layer 100, so as to connect the first conductive layer 110 to an external circuit.
In this embodiment, the material of the second conductive layer 110 is Cu, and in other embodiments, the second conductive layer may also be Al or Co.
The semiconductor structure further includes: and a cap layer 111 on the second conductive layer 110. The capping layer 111 and the second conductive layer 110 have a firm chemical bond therebetween, so that the capping layer 111 has good adhesion to the second conductive layer 110. Therefore, Cu atoms are difficult to diffuse rapidly between the cap layer 111 and the second conductive layer 110, and do not generate holes on top of the second conductive layer 110.
In this embodiment, the capping layer 111 is made of one or more of TaN, Ta, Ti, TiN, ZrN, and ZrTiN.
It should be noted that the substrate further includes: and an etching stop layer 113 located between the first conductive layer 100 and the dielectric layer 101, wherein the etching stop layer 113 exposes the first conductive layer 100, and the first conductive layer 100 is electrically connected to the second conductive layer 110.
In this embodiment, the material of the etch stop layer 113 is silicon nitride. In other embodiments, the material of the etch stop layer may be SiON, SiBCN, or SiCN. The etch stop layer 113 can reduce a capacitive coupling effect between the first conductive layer 100 and the second conductive layer 110, thereby reducing an edge parasitic capacitance.
The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present embodiments, and it is intended that the scope of the present embodiments be defined by the appended claims.

Claims (19)

1. A method of forming a semiconductor structure, comprising:
providing a substrate comprising: a first conductive layer and a dielectric layer on the first conductive layer;
forming a groove which is positioned in the dielectric layer and exposes the first conducting layer;
forming a barrier layer conformally covering the trench;
conformally covering an adhesion layer on the barrier layer;
conformally covering a backing layer over the adhesive layer;
and forming a second conductive layer in the groove after the liner layer is formed.
2. The method of claim 1, wherein the adhesion layer is made of Ru or W.
3. The method of forming a semiconductor structure of claim 1, wherein the adhesion layer has a thickness of 10 to 20 angstroms.
4. The method of claim 1, wherein the adhesion layer is formed using an atomic layer deposition process or a physical vapor deposition process.
5. The method of forming a semiconductor structure of claim 1, wherein the barrier layer is formed using a physical vapor deposition process.
6. The method of forming a semiconductor structure of claim 1, wherein the material of the barrier layer is one or more of TaN, Ta, Ti, TiN, ZrN, and ZrTiN.
7. The method of forming a semiconductor structure of claim 1, wherein the barrier layer has a thickness of 10 to 40 angstroms.
8. The method of forming a semiconductor structure of claim 1, wherein a material of the liner layer comprises one or more of Co, Al, W, and Ti.
9. The method of claim 1, wherein the liner layer is formed using a chemical vapor deposition process.
10. The method of forming a semiconductor structure of claim 1, wherein the liner layer has a thickness of 10 to 40 angstroms.
11. The method of forming a semiconductor structure of claim 1, wherein a material of the second conductive layer comprises Cu, Al, or Co.
12. The method of forming a semiconductor structure of claim 1, wherein the step of forming the second conductive layer comprises:
forming a seed layer conformally covering the liner layer;
filling a conductive material into the groove formed with the seed layer;
and removing the conductive material exposing the groove to form a second conductive layer.
13. The method of claim 1, wherein the trench is filled with a conductive material using an electrochemical plating process.
14. The method of forming a semiconductor structure of claim 1, further comprising: and after the second conductive layer is formed, annealing the semiconductor structure.
15. A semiconductor structure, comprising:
a substrate comprising a first conductive layer and a dielectric layer on the first conductive layer;
a trench in the dielectric layer exposing the first conductive layer;
the barrier layer is covered on the bottom and the side wall of the groove in a shape-preserving manner;
an adhesion layer conformally covering the barrier layer;
a liner layer conformally covering the adhesive layer;
and the second conducting layer is filled in the groove.
16. The semiconductor structure of claim 15, wherein a material of the adhesion layer is Ru or W.
17. The semiconductor structure of claim 15, wherein the adhesion layer has a thickness of 10 to 20 angstroms.
18. The semiconductor structure of claim 15, wherein the material of the barrier layer is one or more of TaN, Ta, Ti, TiN, ZrN, and ZrTiN.
19. The semiconductor structure of claim 15, wherein a material of the liner layer comprises one or more of Co, Al, W, and Ti.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9177858B1 (en) * 2014-05-08 2015-11-03 GlobalFoundries, Inc. Methods for fabricating integrated circuits including barrier layers for interconnect structures
CN108735797A (en) * 2017-04-25 2018-11-02 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9177858B1 (en) * 2014-05-08 2015-11-03 GlobalFoundries, Inc. Methods for fabricating integrated circuits including barrier layers for interconnect structures
CN108735797A (en) * 2017-04-25 2018-11-02 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

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