CN111354789B - Semiconductor device and manufacturing method - Google Patents

Abstract

Semiconductor devices and manufacturing methods provided by embodiments of the present application. The semiconductor device includes: a substrate; a buffer layer provided on the substrate; a channel layer provided on a side of the buffer layer away from the substrate; and a channel layer provided on a side of the buffer layer away from the substrate. A barrier layer on one side; the semiconductor device includes an active area, an isolation area and a field resistance area, wherein the isolation area is arranged around the active area; a channel layer in the active area A two-dimensional electron gas is formed on a side close to the barrier layer; the field resistance region is provided in the isolation region, and the field resistance region is at least partially located in the buffer layer of the isolation region. The region is connected to a reference low potential for releasing charges in the buffer layer. In the embodiment of the present application, a field resistance region is provided in the buffer layer of the isolation region to ensure that the charges in the buffer layer can be released in time and improve the stability of the semiconductor device.

Description

Semiconductor device and manufacturing method

Technical field

The present application relates to the technical fields of semiconductors and semiconductor manufacturing, and specifically, to a semiconductor device and a manufacturing method.

Background technique

The semiconductor material gallium nitride has become a current research hotspot due to its large bandgap, high electron saturation drift velocity, high breakdown field strength, and good thermal conductivity. In terms of electronic devices, gallium nitride materials are more suitable than silicon and gallium arsenide for manufacturing high-temperature, high-frequency, high-voltage and high-power devices, so gallium nitride-based electronic devices have good application prospects.

A gallium nitride lateral device refers to a type of semiconductor device with electrodes distributed laterally. During the operation of a gallium nitride lateral device, if the semiconductor device is turned off and the drain is subjected to a high withstand voltage, the semiconductor device will Charge accumulates in the substrate and buffer layer. When the semiconductor device transitions from the off state to the on state, the charges accumulated in the substrate and buffer layer cannot be released, causing the potential in the semiconductor device substrate and buffer layer to be non-zero. Non-zero potentials of the buffer layer and substrate can lead to unstable performance of the semiconductor device. Especially in a circuit containing multiple such semiconductor devices, each semiconductor device will interact with each other through the potential of the substrate and buffer layer, affecting the performance of the semiconductor device and the entire circuit. The problem of unstable substrate potential can be solved by connecting the substrate to a fixed potential, but it cannot solve the problem of unstable performance of the semiconductor device caused by the existence of potential in the buffer layer.

Contents of the invention

In view of this, the purpose of this application is to provide a semiconductor device and a method for manufacturing the semiconductor device, so as to solve the above problems.

In a first aspect, embodiments of the present application provide a semiconductor device, including:

substrate;

a buffer layer provided on the substrate;

a channel layer provided on the side of the buffer layer away from the substrate;

a barrier layer provided on the side of the channel layer away from the substrate;

The semiconductor device includes an active area, an isolation area and a field resistance area, wherein the isolation area is arranged around the active area;

The channel layer in the active region forms a two-dimensional electron gas on a side close to the barrier layer;

The field resistance region is disposed in the isolation region, the field resistance region is at least partially located in the buffer layer of the isolation region, and the field resistance region is connected to a reference low potential for releasing charges in the buffer layer .

Optionally, in this embodiment of the present application, the field resistance region penetrates the substrate of the isolation region and extends into the buffer layer of the isolation region, and the field resistance region is located where one end of the substrate is connected. The reference voltage is low.

Optionally, in this embodiment of the present application, the channel layer in the isolation region is provided with a barrier layer for implanting ions on the side away from the substrate, so that the channel layer in the isolation region is close to the substrate. Two-dimensional electron gas cannot form on one side of the barrier layer.

Optionally, in this embodiment of the present application, the field resistance region extends from the barrier layer and the channel layer of the isolation region to the buffer layer of the isolation region, and the field resistance region is located on the barrier One end of the layer is connected to the reference low potential.

Optionally, in this embodiment of the present application, the channel layer of the isolation region is not provided with a barrier layer on the side away from the substrate;

The field resistance region extends from the channel layer of the isolation region to the buffer layer of the isolation region, and one end of the field resistance region located at the channel layer is connected to the reference low potential.

Optionally, in this embodiment of the present application, the field resistance region is located at one end of the channel layer and is connected to the reference low potential through a metal conductive part.

Optionally, in this embodiment of the present application, the field resistance region is provided in the buffer layer of the isolation region, and the field resistance region is connected to the reference low potential.

Optionally, in this embodiment of the present application, the distance between the field resistance region and the active region is greater than or equal to 2um.

Optionally, in this embodiment of the present application, the field resistance region is composed of a metal electrode or a doped semiconductor material.

In a second aspect, embodiments of the present application also provide a method for manufacturing a semiconductor device, the method including:

provide a substrate;

Make a buffer layer on one side of the substrate;

Form a channel layer on the side of the buffer layer away from the substrate;

forming a barrier layer on the side of the channel layer away from the substrate;

The active region is formed based on the semiconductor layer structure sequentially fabricated based on the substrate, buffer layer, channel layer, and barrier layer;

Form an isolation region surrounding the active region based on the semiconductor layer structure;

forming in the isolation region a field resistance region located at least partially in the buffer layer;

Connect the field resistance region to a reference low potential.

Optionally, in this embodiment of the present application, an isolation region surrounding the active region is formed based on the semiconductor layer structure, including:

Perform ion implantation in the portion of the barrier layer located around the periphery of the active region; or

The portion of the barrier layer located around the periphery of the active area is etched away.

Optionally, in this embodiment of the present application, forming a field resistance region at least partially located in the buffer layer in the isolation region includes:

Forming a groove at least partially located in the buffer layer in the isolation region by etching, and forming the field resistance region in the groove by depositing metal in the groove; or

The field blocking region at least partially located in the buffer layer is formed in the isolation region by ion implantation.

Semiconductor devices and manufacturing methods provided by embodiments of the present application. The semiconductor device includes: a substrate; a buffer layer provided on the substrate; a channel layer provided on a side of the buffer layer away from the substrate; and a channel layer provided on a side of the buffer layer away from the substrate. A barrier layer on one side; the semiconductor device includes an active area, an isolation area and a field resistance area, wherein the isolation area is arranged around the active area; a channel layer in the active area A two-dimensional electron gas is formed on a side close to the barrier layer; the field resistance region is provided in the isolation region, and the field resistance region is at least partially located in the buffer layer of the isolation region. The region is connected to a reference low potential for releasing charges in the buffer layer. In the embodiment of the present application, a field resistance region is provided in the buffer layer of the isolation region to ensure that the charges in the buffer layer can be released in time and improve the stability of the semiconductor device.

Description of the drawings

In order to explain the technical solutions of the embodiments of the present application more clearly, the drawings required to be used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, without exerting creative efforts, they can also Other relevant drawings are obtained based on these drawings.

Figure 1 is one of the structural schematic diagrams of a semiconductor device provided by an embodiment of the present application;

Figure 2 is a top view of the semiconductor device in Figure 1;

Figure 3 is a second structural schematic diagram of a semiconductor device provided by an embodiment of the present application;

Figure 4 is a third structural schematic diagram of a semiconductor device provided by an embodiment of the present application;

Figure 5 is a fourth structural schematic diagram of a semiconductor device provided by an embodiment of the present application;

Figure 6 is a fifth structural schematic diagram of a semiconductor device provided by an embodiment of the present application;

Figure 7 is a top view of the semiconductor device in Figure 6;

Figure 8 is a sixth structural schematic diagram of a semiconductor device provided by an embodiment of the present application;

Figure 9 is a seventh structural schematic diagram of a semiconductor device provided by an embodiment of the present application;

Figure 10 is a process flow chart of a semiconductor device provided by an embodiment of the present application;

11A-11D are process diagrams of the semiconductor device provided by the embodiment of the present invention.

Icon: 1-semiconductor device; 11-substrate; 12-buffer layer; 13-channel layer; 14-barrier layer; 15-two-dimensional electron gas; 20-active area; 30-isolation area; 40-field Resistive area; 50-metal conductive part; 60-groove.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations.

Accordingly, the following detailed description of the embodiments of the application provided in the appended drawings is not intended to limit the scope of the claimed application, but rather to represent selected embodiments of the application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without any creative work shall fall within the scope of protection of this application.

It should be noted that similar reference numerals and letters represent similar items in the following figures, therefore, once an item is defined in one figure, it does not need further definition and explanation in subsequent figures.

In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", etc. is based on the orientation or positional relationship shown in the drawings, or is the habitually placed position when the product of the invention is used. The orientation or positional relationship is only for the convenience of describing the present invention and simplifying the description. It does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. In addition, the terms "first", "second", etc. are only used to differentiate descriptions and are not to be understood as indicating or implying relative importance.

In order to solve the technical problems mentioned in the background art, embodiments of the present application provide a semiconductor device described below. The semiconductor device includes:

substrate;

a buffer layer provided on the substrate;

a channel layer provided on the side of the buffer layer away from the substrate;

a barrier layer provided on the side of the channel layer away from the substrate;

The semiconductor device includes an active area, an isolation area and a field resistance area, wherein the isolation area is arranged around the active area;

The channel layer in the active region forms a two-dimensional electron gas on the side close to the barrier layer;

The field resistance region is disposed in the isolation region. The field resistance region is at least partially located in the buffer layer of the isolation region. The field resistance region is connected to a reference low potential for releasing charges in the buffer layer.

Please refer to FIG. 1 , which is a schematic structural diagram of a semiconductor device 1 provided by an embodiment of the present application.

The semiconductor device 1 includes a substrate 11 , a buffer layer 12 , a channel layer 13 and a barrier layer 14 .

The material of the substrate 11 can be gallium nitride, silicon, sapphire, silicon nitride, aluminum nitride, SOI (Silicon-On-Insulator, silicon on an insulating substrate) or other materials that can epitaxially grow III-V nitrides. Material.

The buffer layer 12 is a high-resistance layer. The buffer layer 12 is located on one side of the substrate 11 . The buffer layer 12 can be made of one of gallium nitride, aluminum gallium nitride, aluminum nitride, or a combination of materials.

The channel layer 13 is disposed on the side of the buffer layer 12 away from the substrate 11 . The channel layer 13 can be made of gallium nitride material. The gallium nitride material used to make the channel layer 13 is not ion doped.

The barrier layer 14 is disposed on the side of the channel layer 13 away from the substrate 11 . The barrier layer 14 can be made of aluminum gallium nitride or indium aluminum nitride, or a combination thereof.

Please refer to FIG. 1 and FIG. 2 . FIG. 2 is a top view of the semiconductor device 1 provided by the embodiment of the present application. The semiconductor device 1 includes an active area 20 , an isolation area 30 and a field resistance area 40 , wherein the isolation area 30 is arranged around the active area 20 . Among them, the active area 20 is used to realize the device function of the semiconductor device 1. Specifically, the active area 20 is designed according to actual device requirements. For example, when the semiconductor device 1 is a triode, the source, drain and gate electrodes may be provided on the side of the barrier layer 14 of the active region 20 away from the substrate 11; when the semiconductor device 1 is a Schottky diode, the active A Schottky anode and a Schottky cathode may be provided on the side of the barrier layer 14 of the region 20 away from the substrate 11 . Since the design focus of the embodiment of the present application is not on the active region 20 , the structure of the barrier layer 14 on the side of the active region 20 away from the substrate 11 is not shown in the drawings and will not be described in detail here.

The channel layer 13 and the barrier layer 14 form a heterostructure. A large amount of two-dimensional electron gas 15 is formed at the junction of the heterostructure under the piezoelectric effect. The two-dimensional electron gas 15 is located in the active region 20 The channel layer 13 is close to the side of the barrier layer 14 . The isolation area 30 is used to isolate the active area 20 so that the active areas 20 in adjacent semiconductor devices 1 will not be in direct contact. In order to achieve the isolation effect, there is no two-dimensional electron gas 15 in the isolation area 30 .

In order to prevent the two-dimensional electron gas 15 from being in the isolation region 30, specifically, in the first implementation of the embodiment of the present application, ions can be implanted into the barrier layer 14 corresponding to the isolation region 30, and the barrier layer after the ions are implanted 14 prevents the channel layer 13 in the isolation region 30 from forming a two-dimensional electron gas 15 on the side close to the barrier layer 14; in the second implementation of the embodiment of the present application, the isolation region 30 can be corresponding to the barrier layer 14 is etched away so that the two-dimensional electron gas 15 cannot be formed in the isolation region 30 .

The field resistance region 40 is disposed in the isolation region 30 , and the field resistance region 40 is at least partially located in the buffer layer 12 of the isolation region 30 . The field resistance region 40 is a low resistance region. Specifically, the field resistance region 40 may be composed of metal electrodes or doped semiconductor materials. The buffer layer 12 is a high-resistance layer, and the field resistance region 40 is a low-resistance region. When charges exist in the buffer layer 12 , the charges in the buffer layer 12 can be released by connecting the field resistance region 40 to a reference low potential.

Next, in the embodiment of the present application, the specific structure of the buffer layer 12 in which the field resistance region 40 is at least partially located in the isolation region 30 will be introduced.

Please refer to FIG. 1 again. In the first implementation mode of the embodiment of the present application, ions are implanted into the barrier layer 14 corresponding to the isolation area 30, so that the channel layer 13 in the isolation area 30 is at a position close to the barrier layer 14. The two-dimensional electron gas cannot be formed on the side 15. The field resistance region 40 penetrates the substrate 11 of the isolation region 30 and extends into the buffer layer 12 of the isolation region 30 . The field resistance region 40 is located at one end of the substrate 11 and is connected to a reference low potential, where the reference low potential may be a source or ground. In this embodiment, the field resistance region 40 may be disposed in the isolation region 30 along a direction perpendicular to the substrate 11 . The field resistance region 40 may not be disposed in the isolation region 30 along a direction perpendicular to the substrate 11 . The distance L between the field resistance area 40 and the active area 20 only needs to be greater than or equal to the preset distance. For example, the distance L between the field resistance area 40 and the active area 20 is greater than or equal to 2um. It should be understood that the distance L is the distance L between the field resistance area 40 and the active area 20 . Source area 20 minimum distance. Setting the distance between the field stop region 40 and the active region 20 can ensure mutual isolation between the active regions 20 in different semiconductor devices 1 . In a preferred embodiment, the distance L between the field resistance region 40 and the active region 20 is greater than or equal to 10 μm, which can meet the working requirements of devices with higher breakdown voltages.

Please refer to Figures 3 and 4. In the second implementation of the embodiment of the present application, ions are implanted into the isolation region 30 corresponding to the barrier layer 14, so that the channel layer 13 in the isolation region 30 is located close to the barrier layer 14. The two-dimensional electron gas cannot be formed on the side 15. The field resistance region 40 may be located in the buffer layer 12 and the channel layer 13 of the isolation region 30 , or may be located in the buffer layer 12 , the channel layer 13 and the barrier layer 14 of the isolation region 30 . The field resistance region 40 may be disposed in the isolation region 30 along a direction perpendicular to the buffer layer 12 . The field resistance region 40 may not be disposed in the isolation region 30 along a direction perpendicular to the buffer layer 12 . The field resistance region 40 only needs to be at a distance of The distance L of the source area 20 only needs to be greater than or equal to the preset distance (such as 2um). It should be understood that the distance L is the minimum distance between the field resistance area 40 and the active area 20 . The field resistance region 40 is connected to a reference low potential, where the reference low potential may be the source or ground.

Referring to FIG. 5 or 6 , in the third implementation of the embodiment of the present application, the barrier layer corresponding to the isolation region 30 is etched away. The field resistance region 40 is located in the buffer layer 12 and the channel layer 13 of the isolation region 30. The field resistance region 40 can be disposed in the isolation region along the direction perpendicular to the buffer layer 12. The field resistance region 40 also does not have to be along the direction perpendicular to the buffer layer 12. The vertical direction is set in the isolation area. It only needs that the distance L between the field resistance area 40 and the active area 20 is greater than or equal to the preset distance (such as 2um). It should be understood that the distance L is the distance between the field resistance area 40 and the active area. 20 minimum distance. Please refer to Figure 7. Figure 7 is a top view of the semiconductor device corresponding to Figure 6. One end of the field resistance region 40 located at the channel layer 13 is connected to the reference low potential. Specifically, the field resistance region 40 can be connected to the reference low potential through the metal conductive portion 50. , where the reference low potential can be source or ground.

Please refer to FIG. 8 or FIG. 9 . In the fourth implementation manner of the embodiment of the present application, the field resistance region 40 can be disposed in the buffer layer 12 of the isolation region 30 , and the field resistance region 40 can be disposed in a direction parallel to the buffer layer 12 In the buffer layer 12 , the field resistance region 40 does not need to be arranged in the buffer layer 12 in a direction parallel to the buffer layer 12 , as long as the minimum distance between the field resistance region 40 and the active region 20 is greater than or equal to a preset distance (such as 2um). ). The field resistance region 40 is connected to a reference low potential, where the reference low potential may be the source or ground.

In one embodiment, the device structure of the present application also includes a source and a drain. The field resistance region 40 is at least partially located in the buffer layer of the isolation region, connected to the reference low potential, and the field resistance region 40 is located at a distance from the active region. The minimum distance of 20 is greater than or equal to the minimum distance between the source and drain to ensure that the charge in the buffer layer can be released in time.

It can be understood that the above-mentioned embodiments are only some exemplary structures of the present application, and the embodiments of the present application may also include other structures, as long as the field resistance region 40 is at least partially located in the buffer layer 12 of the isolation region 30 .

Please refer to FIG. 10 , which is a schematic flowchart of a method for manufacturing a semiconductor device 1 provided by an embodiment of the present application. The following takes the production of the semiconductor device in Figure 1 as an example to explain. The method includes the following steps:

Step S101, provide a substrate 11.

Step S102 , please refer to FIG. 11A and FIG. 11B , a buffer layer 12 , a channel layer 13 and a barrier layer 14 are sequentially deposited on one side of the substrate 11 .

Specifically, first, the buffer layer 12 is formed on one side of the substrate 11;

Next, a channel layer 13 is formed on the side of the buffer layer 12 away from the substrate 11;

Finally, a barrier layer 14 is formed on the side of the channel layer 13 away from the substrate 11 .

The channel layer 13 and the barrier layer 14 form a heterostructure. A large amount of two-dimensional electron gas 15 is formed at the junction of the heterostructure under the piezoelectric effect. The two-dimensional electron gas 15 is located in the channel layer 13 and is close to the barrier. side of layer 14.

In step S103, the active region 20 is formed based on the semiconductor layer structure formed sequentially by the substrate 11, the buffer layer 12, the channel layer 13, and the barrier layer 14.

Step S104, please refer to FIG. 11C, forming an isolation region 30 surrounding the active region 20 based on the semiconductor layer structure.

The electrodes of the semiconductor device are formed on the side of the barrier layer 14 away from the substrate 11 , and the area where the electrodes of the semiconductor device are formed forms the active region 20 .

By performing ion implantation on the portion of the barrier layer 14 located around the periphery of the active area 20 or etching away the portion of the barrier layer 14 located around the periphery of the active area 20 , a structure is formed around the active area 20 quarantine area.

Step S105 , please refer to FIG. 1 , forming a field resistance region 40 at least partially located in the buffer layer 12 in the isolation region 30 .

In one implementation of the embodiment of the present application, please refer to FIG. 11D , a groove 60 at least partially located in the buffer layer 12 can be formed in the isolation region 30 by etching, and by etching in the groove 60 The field resistance region 40 is formed in the groove 60 by depositing metal, wherein the distance L between the groove 60 and the active region 20 is greater than or equal to a preset distance (such as 2um).

In another implementation of the embodiment of the present application, the field resistance region 40 at least partially located in the buffer layer 12 can be formed in the isolation region 30 by ion implantation.

Step S106, connect the field resistance region 40 to the reference low potential.

In the embodiment of the present application, the field resistance region 40 can be directly connected to the reference low potential; or the field resistance region 40 can be connected to the reference low potential through the metal conductive portion 50 .

Semiconductor devices and manufacturing methods provided by embodiments of the present application. The semiconductor device includes: a substrate; a buffer layer provided on the substrate; a channel layer provided on a side of the buffer layer away from the substrate; and a channel layer provided on a side of the buffer layer away from the substrate. A barrier layer on one side; the semiconductor device includes an active area, an isolation area and a field resistance area, wherein the isolation area is arranged around the active area; a channel layer in the active area A two-dimensional electron gas is formed on a side close to the barrier layer; the field resistance region is provided in the isolation region, and the field resistance region is at least partially located in the buffer layer of the isolation region. The region is connected to a reference low potential for releasing charges in the buffer layer. In the embodiment of the present application, a field resistance region is provided in the buffer layer of the isolation region to ensure that the charges in the buffer layer can be released in time and improve the stability of the semiconductor device.

The above descriptions are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application shall be included in the protection scope of this application.

Claims (12)

1. A semiconductor device, characterized in that it includes: substrate; a buffer layer provided on the substrate; a channel layer provided on the side of the buffer layer away from the substrate; a barrier layer provided on the side of the channel layer away from the substrate; The semiconductor device includes an active region, an isolation region and a field resistance region, wherein the channel layer in the active region forms a two-dimensional electron gas on a side close to the barrier layer; The isolation area is arranged around the active area, and no two-dimensional electron gas is formed in the isolation area; The field resistance region is disposed in the isolation region. The field resistance region is at least partially located in the buffer layer of the isolation region and is not in contact with the two-dimensional electron gas. The field resistance region is connected to a reference low potential. To release the charge in the buffer layer. 2. The semiconductor device according to claim 1, characterized in that: The field resistance region penetrates the substrate of the isolation region and extends into the buffer layer of the isolation region. One end of the field resistance region located on the substrate is connected to the reference low potential. 3. The semiconductor device according to claim 1, characterized in that: The channel layer in the isolation region is provided with a barrier layer for implanting ions on the side away from the substrate, so that the channel layer in the isolation region cannot form two-dimensional electrons on the side close to the barrier layer. gas. 4. The semiconductor device according to claim 3, characterized in that; The field resistance region extends from the barrier layer and the channel layer of the isolation region to the buffer layer of the isolation region, and one end of the field resistance region located on the barrier layer is connected to the reference low potential. 5. The semiconductor device according to claim 1, characterized in that: The channel layer of the isolation region is not provided with a barrier layer on the side away from the substrate; The field resistance region extends from the channel layer of the isolation region to the buffer layer of the isolation region, and one end of the field resistance region located at the channel layer is connected to the reference low potential. 6. The semiconductor device according to claim 5, characterized in that: The field resistance region is located at one end of the channel layer and is connected to the reference low potential through a metal conductive part. 7. The semiconductor device according to claim 1, characterized in that: The field resistance region is disposed in the buffer layer of the isolation region, and the field resistance region is connected to the reference low potential. 8. The semiconductor device according to any one of claims 1-7, characterized in that: The distance between the field resistance area and the active area is greater than or equal to 2um. 9. The semiconductor device according to any one of claims 1-7, characterized in that: The field resistance region is composed of metal electrodes or doped semiconductor materials. 10. A method for manufacturing a semiconductor device, characterized in that the method includes: provide a substrate; Make a buffer layer on one side of the substrate; Form a channel layer on the side of the buffer layer away from the substrate; forming a barrier layer on the side of the channel layer away from the substrate; An active region is formed based on the semiconductor layer structure formed sequentially based on the substrate, buffer layer, channel layer, and barrier layer. The channel layer in the active region forms two layers on the side close to the barrier layer. dimensional electron gas; An isolation area surrounding the active area is formed based on the semiconductor layer structure, and no two-dimensional electron gas is formed in the isolation area; forming a field resistance region at least partially located in the buffer layer in the isolation region, and the field resistance region is not in contact with the two-dimensional electron gas; Connect the field resistance region to the reference low potential. 11. The manufacturing method of claim 10, wherein forming an isolation region surrounding the active region based on the semiconductor layer structure includes: Perform ion implantation in the portion of the barrier layer located around the periphery of the active region; or The portion of the barrier layer located around the periphery of the active area is etched away. 12. The manufacturing method of claim 10, wherein forming a field resistance region at least partially located in the buffer layer in the isolation region includes: Forming a groove at least partially located in the buffer layer in the isolation region by etching, and forming the field resistance region in the groove by depositing metal in the groove; or The field blocking region at least partially located in the buffer layer is formed in the isolation region by ion implantation.