CN110021661B - Semiconductor device and method of making the same - Google Patents

Abstract

Embodiments of the present application provide a semiconductor device and a method for fabricating the same, wherein an N-type semiconductor is fabricated between a gate electrode and a P-type semiconductor layer in the semiconductor device based on the surface of the P-type semiconductor layer combined with in-situ growth. layer, so that the P-type semiconductor layer and the N-type semiconductor layer can jointly form a reverse biased n/p junction, thereby greatly reducing the gate leakage current and improving the reliability of the semiconductor device.

Description

Semiconductor device and method of making the same

technical field

The present application relates to the technical field of microelectronics, and in particular, to a semiconductor device and a manufacturing method thereof.

Background technique

In existing HEMT (High Electron Mobility Transistor, High Electron Mobility Transistor) devices, such as gallium nitride (GaN) devices, due to the existence of two-dimensional electron gas between the communication layer and the barrier layer, GaN devices In the normally open state, in order to realize the normally closed property of the gallium nitride device, the gate of the gallium nitride device needs to be turned on only when there is a forward bias voltage.

SUMMARY OF THE INVENTION

In view of this, the present application provides a semiconductor device and a manufacturing method thereof, as follows.

In one aspect, a preferred embodiment of the present application provides a semiconductor device including a heterostructure and a source electrode, a drain electrode and a gate electrode connected to the heterostructure, the heterostructure comprising:

base;

A channel layer formed based on the substrate is fabricated;

a barrier layer fabricated on the side of the channel layer away from the substrate;

A P-type semiconductor layer is fabricated based on the side of the barrier layer away from the channel layer;

An N-type semiconductor layer formed by in-situ growth based on the surface of the P-type semiconductor layer away from the barrier layer;

The source electrode and the drain electrode are formed based on the channel layer and are located at opposite ends of the barrier layer, and the gate electrode is fabricated above the N-type semiconductor layer and is connected to the N-type semiconductor layer. type semiconductor layer contacts.

In an option of the embodiment of the present application, a through hole is formed on the N-type semiconductor layer, and the gate is in contact with the P-type semiconductor layer through the through hole.

In a selection of the embodiment of the present application, the N-type semiconductor layer is doped with silicon impurities with a concentration of 1e ¹⁷ -1e ¹⁹ cm ^-3 , and the thickness of the N-type semiconductor layer is 10nm - 200nm.

In an option of the embodiment of the present application, the heterostructure further includes a low-temperature semiconductor cap layer formed by in-situ growth based on the surface of the N-type semiconductor layer away from the P-type semiconductor layer; or,

A low-temperature semiconductor cap layer formed by in-situ growth based on the P-type semiconductor layer being close to the surface of the N-type semiconductor layer.

In the selection of the embodiment of the present application, the formation temperature of the low temperature semiconductor cap layer is 450°C to 600°C.

In the selection of the embodiment of the present application, the thickness of the low-temperature semiconductor cap layer is 2 nm˜50 nm.

In a selection of embodiments of the present application, the substrate includes a substrate, and a buffer layer fabricated and formed based on the substrate, the buffer layer being located between the substrate and the channel layer.

On the other hand, an embodiment of the present application also provides a method for fabricating a semiconductor device, the fabrication method comprising:

provide a base;

Forming a channel layer based on the substrate;

A source electrode, a drain electrode and a barrier layer are formed on one side of the channel layer, the source electrode and the drain electrode are respectively located at two ends of the barrier layer;

A P-type semiconductor layer is formed on the side of the barrier layer away from the channel layer;

An N-type semiconductor layer is formed by in-situ growth on the surface of the P-type semiconductor layer away from the barrier layer;

A gate electrode is formed on the surface of the N-type semiconductor layer away from the P-type semiconductor layer.

In the selection of the embodiment of the present application, before the step of forming the gate on the side of the N-type semiconductor layer away from the P-type semiconductor layer, the manufacturing method further includes:

Etching the N-type semiconductor layer to form a through hole on the N-type semiconductor layer, so that a gate formed based on the N-type semiconductor layer can be in contact with the P-type semiconductor layer through the through hole .

In the selection of the embodiment of the present application, the step of forming a gate on the surface of the N-type semiconductor layer away from the P-type semiconductor layer includes:

A low-temperature semiconductor cap layer is formed by in-situ growth on the surface of the N-type semiconductor layer away from the P-type semiconductor layer;

etching the N-type semiconductor layer and the low-temperature semiconductor cap layer to form through holes on the N-type semiconductor layer and the low-temperature semiconductor cap layer;

A gate electrode is formed based on a side of the low temperature semiconductor cap layer away from the N-type semiconductor layer, and the gate electrode is in contact with the P-type semiconductor layer through the through hole.

Based on the scheme provided above, the application at least has the following beneficial effects:

In the semiconductor device and the manufacturing method thereof provided by the embodiments of the present application, after the epitaxial growth of the P-type semiconductor layer in the semiconductor device is completed, an in-situ growth method is continued to fabricate between the gate and the P-type semiconductor layer to generate a The N-type semiconductor layer makes the N-type semiconductor layer and the P-type semiconductor layer together form a reverse N/P junction, so as to effectively reduce the leakage current, increase the gate bias voltage, and ensure that the semiconductor device is in a normally closed state.

In addition, the present application further forms a low-temperature semiconductor cap layer on the N-type semiconductor layer by in-situ growth, so as to cover the semiconductor layer with inherent threading dislocation and the pits on the surface thereof, thereby further reducing leakage current.

In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the preferred embodiments are exemplified below, and are described in detail as follows in conjunction with the accompanying drawings.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present application more clearly, the following drawings will briefly introduce the drawings that need to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore do not It should be regarded as a limitation of the scope, and for those of ordinary skill in the art, other related drawings can also be obtained according to these drawings without any creative effort.

FIG. 1 is a schematic cross-sectional structure diagram of a conventional P-GaN device.

FIG. 2 is a schematic cross-sectional structure diagram of another conventional P-GaN device.

FIG. 3 is a schematic cross-sectional structure diagram of the semiconductor device provided in Embodiment 1 of the present application.

FIGS. 4(a)-4(b) are schematic diagrams of conduction band edge profiles of the P-GaN device shown in FIG. 2 under different gate bias voltages.

5( a )- FIG. 5( b ) are schematic diagrams of conduction band edge profiles of the semiconductor device provided in the embodiments of the present application under different gate bias voltages.

6( a )- FIG. 6( b ) are schematic diagrams of simulation results of 2DEG densities of the P-GaN device shown in FIG. 2 and the semiconductor device provided in the embodiments of the present application under different gate bias voltages, respectively.

FIG. 7 is a schematic cross-sectional structure diagram of the semiconductor device provided in the second embodiment of the present application.

FIG. 8 is a schematic cross-sectional structure diagram of the semiconductor device provided in Embodiment 3 of the present application.

FIG. 9 is a schematic cross-sectional structure diagram of another semiconductor device provided in Embodiment 3 of the present application.

FIG. 10 is a schematic cross-sectional structure diagram of yet another semiconductor device provided in Embodiment 3 of the present application.

11 is a schematic cross-sectional structure diagram of yet another semiconductor device provided in Embodiment 3 of the present application.

FIG. 12 is a schematic process flow diagram of a method for fabricating a semiconductor device provided by an embodiment of the present application.

FIG. 13 is a schematic diagram of a sub-flow of step S6 shown in FIG. 12 .

Icon: 10-semiconductor device; 11-source; 12-drain; 13-gate; 14-substrate; 140-substrate; 141-buffer layer; 15-channel layer; 16-barrier layer; 17- P-type semiconductor layer; 170-recess; 18-N-type semiconductor layer; 19-low temperature semiconductor cap layer.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments It is only a part of the embodiments of the present application, but not all of the embodiments. The components of the embodiments of the present application generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations.

Thus, the following detailed description of the embodiments of the application provided in the accompanying drawings is not intended to limit the scope of the application as claimed, but is merely representative of selected embodiments of the application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

In the existing P-GaN devices, the formation of ohmic contact or Schottky contact mainly depends on the work function of the metal in contact with the P-GaN layer, that is, the gate leakage current mainly depends on the size of the contact with the P-GaN layer. The metal type of the metal electrode (gate) that is in contact. Therefore, in practical applications, in order to achieve the normally closed property of the P-GaN device, generally try to obtain a larger forward gate on the premise of a smaller leakage current. extreme bias to improve device reliability.

Currently, reverse-biased Schottky contacts have less leakage current than Ohmic contacts, but even with a well-treated metal/P-GaN Schottky junction as shown in Figure 1, when the gate is biased At voltages less than 7V, there is also a full peak electric field inside the depleted P-GaN layer, leading to the risk of avalanche breakdown.

Furthermore, as shown in FIG. 2, in some other embodiments, in order to reduce and redistribute the peak electric field inside the P-GaN layer as shown in FIG. 1, N-type impurities (eg, silicon impurities) may be ion-implanted into a partial region of the P-GaN layer to form an N-GaN edge guard ring after thermal activation. However, in actual implementation, in order to obtain a high dopant activation efficiency, a high implantation dose greater than 5e ¹⁵ cm ^-2 is generally required to generate sufficient electron concentration, resulting in ineffectiveness even at temperatures as high as 1200 °C. Eliminate damage due to ion implantation. In addition, the inherent threading dislocation voids in the P-GaN layer epitaxially grown by MOCVD (Metal-Organic Chemical Vapor Deposition) cause abnormal leakage paths in P-GaN devices, leading to leakage. The current is large and the device reliability is poor.

In this regard, as shown in FIG. 3 , an embodiment of the present application provides a semiconductor device 10 and a manufacturing method thereof, wherein, after the epitaxial growth of the P-type semiconductor layer 17 in the semiconductor device 10 shown in FIG. 3 is completed, continue Based on the surface of the P-type semiconductor layer 17, an N-type semiconductor layer 18 is formed between the gate electrode 13 and the P-type semiconductor layer 17 by in-situ growth, so that the gap between the P-type semiconductor layer 17 and the N-type semiconductor layer 18 is formed. Forming an inverted N/P junction can further reduce gate leakage current while reducing and redistributing the peak electric field inside the P-GaN layer shown in Figure 1, avoiding the implant damage shown in Figure 2 , to improve the gate bias voltage range and ensure the reliability of the semiconductor device 10 . The solution provided in this embodiment will be described in detail below with reference to the accompanying drawings.

Example 1

Please refer to FIG. 3 again. FIG. 3 is a schematic cross-sectional structure diagram of a semiconductor device 10 according to an embodiment of the present application. The semiconductor device 10 includes a heterostructure and a source electrode 11 , a drain electrode 12 and a gate electrode 13 connected to the heterostructure. , the heterostructure includes a substrate 14 , a channel layer 15 , a barrier layer 16 , a P-type semiconductor layer 17 and an N-type semiconductor layer 18 .

The base 14 includes a substrate 140 and a buffer layer 141 fabricated and formed based on the substrate 140 , and the buffer layer 141 is located between the substrate 140 and the channel layer 15 . Optionally, the substrate 140 can be sapphire (sapphire), silicon carbide (SiC), silicon (Si), lithium niobate, silicon insulating substrate, gallium nitride (GaN), aluminum nitride (AlN), etc. It can be made of one of the materials, or formed by using any other materials suitable for growing group III nitrides known to those skilled in the art, which is not specifically limited in this application. The buffer layer 141 may be grown on the substrate 140 by, but not limited to, an epitaxial growth process, and the buffer layer 141 may be, but not limited to, a GaN material layer.

The channel layer 15 is formed based on the buffer layer 141 on the substrate 14 , which may be made of but not limited to GaN material, and the barrier layer 16 is formed based on the channel layer 15 being away from the substrate 14 . One-side fabrication can be made of materials known to semiconductor technicians such as AlGaN, AlN or InAlN that can form a two-dimensional electron gas with the GaN (channel layer 15), such as group III nitride semiconductor materials, etc. . In actual implementation, a two-dimensional electron gas is formed between the channel layer 15 and the barrier layer 16 and disappears directly under the P-type semiconductor layer 17 . It should be noted that, in this embodiment, the dotted line shown in FIG. 3 is a conductive channel formed in the channel layer 15 and used for providing two-dimensional electron gas.

The P-type semiconductor layer 17 is formed on the side of the barrier layer 16 away from the channel layer 15 , and can be made of, but not limited to, GaN or Al GaN material. The N-type semiconductor layer 18 is formed by in-situ growth on the surface of the P-type semiconductor layer 17 away from the barrier layer 16 . The N-type semiconductor layer 18 can be made of but not limited to GaN material. For example, it can be made of a material that can form a reverse-biased n/p junction with the P-type semiconductor layer 17, which is well known to those skilled in the semiconductor industry. Wherein, in the embodiments of the present application, the N-type semiconductor layer 18 is formed by in-situ growth, which means that the N-type semiconductor layer 18 is grown using the same growth environment and the same growth temperature as the P-type semiconductor layer 17 . For example, assuming that the P-type semiconductor layer 17 is grown by MOCVD, and the growth temperature is 950°C to 1050°C, the N-type semiconductor layer 18 is also grown by MOCVD, and the growth temperature is 950°C to 1050°C. Therefore, the problem of out-diffusion of Mg (magnesium) is effectively reduced, and the device performance of the semiconductor device 10 is improved.

In addition, the N-type semiconductor layer 18 may be doped with silicon impurities with a concentration of 1e ¹⁷ to 1e ¹⁹ cm ⁻³ , and in practice, the thickness of the N-type semiconductor layer 18 may be 10 nm to 200 nm, such as 40nm, 45nm, 50nm, etc.

Further, the source electrode 11 and the drain electrode 12 are fabricated based on the channel layer 15 and are located at opposite ends of the barrier layer 16 , and the gate electrode 13 is fabricated from the N-type Above the semiconductor layer 18 and in contact with the N-type semiconductor layer 18 .

Further, in order to verify the performance of the semiconductor device 10 given in the embodiments of the present application, please refer to FIG. 4(a)-FIG. 4(b) and FIG. 5(a)-FIG. 5(b) in conjunction with a) is a schematic diagram of the conduction band edge profile in the P-GaN device shown in Figure 2 when the gate bias voltage is increased from 0V to 6V (step value is 1V). When the voltages are 0V and 6V as shown in Fig. 4(b), respectively, the barrier on the barrier layer in the P-GaN device shown in Fig. 2 disappears. Figure 5(a) is a schematic diagram of the conduction band edge profile in the semiconductor device shown in the present application when the gate bias voltage is increased from 0V to 30V (step value is 3V). When the voltages are respectively 0V and 30V as shown in FIG. 5( b ), the potential barrier on the barrier layer in the semiconductor device 10 presented in this application still exists.

In addition, please refer to FIG. 6(a)-FIG. 6(b), which are respectively the performance simulation diagram of the P-GaN device shown in FIG. 2 and the performance simulation diagram of the semiconductor device 10 given in this application, wherein , it can be seen from Fig. 6(a) that the density of 2DEG (two-dimensional electron gas) reaches 2e ¹² cm for the P-GaN device presented in Fig. 2 when the gate bias voltage (Vgs) reaches a threshold voltage of 1 V ^-2 , 2DEG (two-dimensional electron gas) has a density of 2e ¹³ cm ^-2 and is saturated when the gate bias voltage continues to increase and reaches about 6V. As can be seen from FIG. 6(b), when the gate bias voltage of the semiconductor device 10 given in this application reaches the threshold voltage of 12V, the density of 2DEG can reach 2e ¹² cm ⁻² , but if the 2DEG density is When the density reaches 2e ¹³ cm ⁻² and is saturated, the gate bias voltage can be increased to about 30V. From this, it can be concluded that the semiconductor device 10 given in this application has a large gate voltage range.

To sum up, compared to the scheme of forming an N-GaN layer between the gate 13 and the P-GaN layer by ion implantation based on the P-GaN layer in the P-GaN device shown in FIG. 2, the embodiments of the present application In the first, after the epitaxial growth of the P-type semiconductor layer 17 is completed, the N-type semiconductor layer 18 is formed by in-situ growth to obtain the gate 13, the N-type semiconductor layer 18, and the P-type semiconductor layer 17. The stacked structure can effectively The problem of implant damage due to ion implantation is avoided. At the same time, compared with the reverse biased Schottky junction, since the reverse biased n/p junction with ohmic contact can be formed between the N-type semiconductor layer 18 and the P-type semiconductor layer 17 in the present application, the Effectively reduce the gate leakage current and increase the range of gate 13 voltage when the semiconductor device 10 is within the acceptable range of gate leakage current, even when the gate 13 bias voltage is adjusted to a higher value (eg 30V) , the structures of the N-type semiconductor layer 18 and the P-type semiconductor layer 17 are not damaged, and the two-dimensional electron gas can be maintained.

Embodiment 2

FIG. 7 is a schematic cross-sectional structure diagram of the semiconductor device 10 provided in the second embodiment of the present application, wherein, compared with the semiconductor device 10 shown in FIG. 3 , in the semiconductor device 10 provided in the second embodiment , the heterostructure may further include a low-temperature semiconductor cap layer 19 formed by in-situ growth based on the surface of the N-type semiconductor layer 18 away from the P-type semiconductor layer 17, and the low-temperature semiconductor cap layer 19 is used to cover the crystalline semiconductor Inherent threading dislocation voids on the layer and pits on its surface to eliminate abnormal leakage paths and reduce leakage currents.

Optionally, in actual implementation, the low-temperature semiconductor cap layer 19 may also be fabricated and formed directly based on the surface of the P-type semiconductor layer, and further based on the low-temperature semiconductor cap layer 19 being far away from the surface of the P-type semiconductor layer 17 The N-type semiconductor layer 18 is fabricated and formed, which is not limited in this embodiment.

It should be noted that the growth temperature used in the in-situ growth of the low-temperature semiconductor cap layer 19 needs to be lower than the growth temperature of the P-type semiconductor layer 17. For example, the formation temperature of the low-temperature semiconductor cap layer 19 may be Not limited to 450°C to 600°C, such as 480°C, 490°C, 520°C, etc. Optionally, the low-temperature semiconductor cap layer 19 may be, but not limited to, an N-type GaN layer, and its thickness may be, but not limited to, 2 nm˜50 nm, such as 10 nm, 15 nm, 20 nm, and the like.

Embodiment 3

Compared with the first embodiment and the second embodiment, in the semiconductor device 10 shown in FIG. 8 given in the third embodiment, the N-type semiconductor layer 18 may be provided with a through hole, and the gate 13 passes through the through hole. The holes are in contact with the P-type semiconductor layer 17 . The through hole can be obtained by etching the N-type semiconductor layer 18 to introduce an N-type semiconductor guard ring into the semiconductor device 10 , so that the gate 13 and the P-type semiconductor layer 17 are connected to each other. A Schottky contact is formed between them for control of gate 13 leakage current and gate threshold voltage.

Similarly, when the semiconductor device 10 as shown in FIG. 7 includes the low-temperature semiconductor cap layer 19 , the through hole as shown in FIG. 9 can be formed by simultaneously etching the N-type semiconductor layer 18 and the low-temperature semiconductor cap layer 19 , so that the gate 13 is in Schottky contact with the P-type semiconductor layer 17 through the through hole, so as to control the leakage current of the gate 13 and the gate threshold voltage.

It should be noted that when the through hole is etched to form a Schottky contact between the gate 13 and the P-type semiconductor layer 17, as shown in FIG. 8 and FIG. The etching of the layer 18 ends at the surface of the P-type semiconductor layer 17 , and as shown in FIG. 10 and FIG. 11 , the etching of the N-type semiconductor layer 18 may extend into the P-type semiconductor layer 17 , and a groove 170 is formed on the surface of the P-type semiconductor layer 17 .

Embodiment 4

As shown in FIG. 12 , this embodiment also provides a method for fabricating a semiconductor device 10 , which is used for fabricating the above-mentioned semiconductor device 10 . It should be noted that the method for fabricating the semiconductor device 10 provided by the present invention does not Figure 12 and the specific sequence described below are limiting. It should be understood that the order of some steps in the manufacturing method of the semiconductor device 10 of the present invention may be exchanged according to actual needs, or some steps may be omitted or deleted, which is not limited in this embodiment.

Step S1, providing a substrate 14;

Step S2, fabricating and forming the channel layer 15 based on the substrate 14;

In step S3, a source electrode 11, a drain electrode 12 and a barrier layer 16 are formed on one side of the channel layer 15, and the source electrode 11 and the drain electrode 12 are located at both ends of the barrier layer 16;

Step S4, forming a P-type semiconductor layer 17 on the side of the barrier layer 16 away from the channel layer 15;

Step S5, forming an N-type semiconductor layer 18 on the surface of the P-type semiconductor layer 17 away from the barrier layer 16 by in-situ growth;

Step S6 , forming a gate 13 on the surface of the N-type semiconductor layer 18 away from the P-type semiconductor layer 17 .

It can be understood that the semiconductor device 10 as shown in FIG. 3 can be fabricated through the process flow given in the above-mentioned steps S1 to S6, wherein, for the detailed description of each step, please refer to the semiconductor device in the above-mentioned first embodiment. 10 is not repeated in this embodiment.

According to actual needs, as an implementation manner, in order to obtain the semiconductor device 10 shown in FIG. 7 , the side of the N-type semiconductor layer 18 away from the P-type semiconductor layer 17 as described in step S6 is performed. Before the step of forming the gate 13 , the manufacturing method may further include: using a low temperature of 450° C. to 600° C. to continue the in-situ growth on the side of the N-type semiconductor layer 18 away from the P-type semiconductor layer 17 to obtain a graph. The thickness of the low temperature semiconductor cap layer 19 shown in 7 may be, but not limited to, 2 nm˜50 nm.

As another embodiment, in order to obtain the semiconductor device 10 shown in FIG. 8 , a gate is formed on the side of the N-type semiconductor layer 18 away from the P-type semiconductor layer 17 as shown in step S6 Before the step of forming the pole 13 , the manufacturing method may further include: etching the N-type semiconductor layer 18 to form through holes on the N-type semiconductor layer 18 , so that the N-type semiconductor layer 18 is fabricated based on the N-type semiconductor layer 18 . The gate 13 can be in contact with the P-type semiconductor layer 17 through the through hole.

As yet another embodiment, in order to obtain the semiconductor device 10 shown in FIG. 9 , as shown in FIG. 13 , as shown in step S6 , a part of the N-type semiconductor layer 18 far from the P-type semiconductor layer 17 is shown in step S6 . The steps of forming the gate 13 by side fabrication include:

Step S60, forming a low temperature semiconductor cap layer 19 by in-situ growth on the surface of the N-type semiconductor layer 18 away from the P-type semiconductor layer 17;

Step S61, etching the N-type semiconductor layer 18 and the low-temperature semiconductor cap layer 19 to form through holes on the N-type semiconductor layer 18 and the low-temperature semiconductor cap layer 19;

Step S62 , a gate 13 is formed based on the side of the low temperature semiconductor cap layer 19 away from the N-type semiconductor layer 18 , and the gate 13 is in contact with the P-type semiconductor layer 17 through the through hole.

To sum up, in the semiconductor device 10 and the fabrication method thereof provided by the embodiments of the present application, after the epitaxial growth of the P-type semiconductor layer 17 in the semiconductor device 10 is completed, the in-situ growth method is continued between the gate 13 and the gate 13 . An N-type semiconductor layer 18 is formed between the P-type semiconductor layers 17, so that the N-type semiconductor layer 18 and the P-type semiconductor layer 17 together form a reverse N/P junction, so as to effectively reduce the leakage current and increase the gate bias voltage , to ensure that the semiconductor device 10 is in a normally closed state.

In addition, the present application further forms a low temperature semiconductor cap layer 19 on the N-type semiconductor layer 18 by in-situ growth, so as to cover the semiconductor layer with inherent threading dislocation and the pits on the surface thereof to further reduce leakage current.

The above descriptions are only preferred embodiments of the present application, and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included within the protection scope of this application.

Claims (6)

1. A semiconductor device comprising a heterostructure and source, drain and gate electrodes connected to the heterostructure, the heterostructure comprising:

a substrate;

manufacturing a formed channel layer on the basis of the substrate;

manufacturing a formed barrier layer on the basis of one side of the channel layer away from the substrate;

manufacturing a formed P-type semiconductor layer on the basis of one side of the barrier layer away from the channel layer;

an N-type semiconductor layer formed by in-situ growth on the basis of the surface of the P-type semiconductor layer far away from the barrier layer;

the source electrode and the drain electrode are formed on the basis of the manufacture of the channel layer and are positioned at two opposite ends of the barrier layer, and the grid electrode is manufactured above the N-type semiconductor layer and is in contact with the N-type semiconductor layer;

the heterostructure further comprises a low-temperature semiconductor cap layer formed by in-situ growth on the basis of the surface, far away from the P-type semiconductor layer, of the N-type semiconductor layer; or,

a low-temperature semiconductor cap layer which is formed on the basis that the P-type semiconductor layer is close to the surface of the N-type semiconductor layer and is grown in situ;

and a through hole is formed in the N-type semiconductor layer, and the grid electrode is in contact with the P-type semiconductor layer through the through hole.

2. The semiconductor device according to claim 1, wherein the N-type semiconductor layer is doped with 1e¹⁷～1e¹⁹cm^-3The thickness of the N-type semiconductor layer is 10 nm-200 nm.

3. The semiconductor device according to claim 1, wherein the formation temperature of the low-temperature semiconductor cap layer is 450 ℃ to 600 ℃.

4. The semiconductor device of claim 1, wherein the low temperature semiconductor cap layer has a thickness of 2nm to 50 nm.

5. The semiconductor device according to claim 1, wherein the base includes a substrate, and a buffer layer formed on the basis of the substrate, the buffer layer being located between the substrate and the channel layer.

6. A method for manufacturing a semiconductor device, the method comprising:

providing a substrate;

forming a channel layer on the basis of the substrate;

manufacturing and forming a source electrode, a drain electrode and a barrier layer on one side of the channel layer, wherein the source electrode and the drain electrode are respectively positioned at two ends of the barrier layer;

manufacturing and forming a P-type semiconductor layer on one side of the barrier layer away from the channel layer;

forming an N-type semiconductor layer on the surface of the P-type semiconductor layer far away from the barrier layer through in-situ growth;

forming a grid on the surface of the N-type semiconductor layer far away from the P-type semiconductor layer;

the step of forming a grid electrode on the surface of the N-type semiconductor layer far away from the P-type semiconductor layer comprises the following steps:

forming a low-temperature semiconductor cap layer on the surface of the N-type semiconductor layer far away from the P-type semiconductor layer through in-situ growth;

etching the N-type semiconductor layer and the low-temperature semiconductor cap layer to form through holes on the N-type semiconductor layer and the low-temperature semiconductor cap layer;

and manufacturing and forming a grid electrode on the basis of one side of the low-temperature semiconductor cap layer, which is far away from the N-type semiconductor layer, and enabling the grid electrode to be in contact with the P-type semiconductor layer through the through hole.

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