CN111343398A - CMOS sensor-memory-computing integrated circuit structure based on dynamic visual sensing technology - Google Patents

Abstract

The invention discloses a CMOS (complementary metal oxide semiconductor) sensing and calculating integrated circuit structure based on a dynamic visual sensing technology. The invention mainly comprises a sensing circuit module based on an AER mode and a storage and calculation integrated circuit module, wherein the sensing circuit module based on the AER mode comprises: the dynamic visual sensing active phase element circuit is used for sensing an external light intensity signal and converting the external light intensity signal into a corresponding electric signal; the correlated double sampling circuit is used for carrying out double sampling on the electric signal; the differential comparator is used for making difference on the subsampled data and comparing the subsampled data with a reference voltage; the light intensity detection circuit is used for sensing whether the dynamic light intensity changes or not; the logic decision circuit is used for combining the data of the differential comparator and the light intensity detection circuit to carry out validity decision and outputting a decision result. The purposes of saving storage area, reducing calculation power consumption and improving calculation speed are achieved.

Description

CMOS sensor-memory-computing integrated circuit structure based on dynamic visual sensing technology

technical field

The invention belongs to the field of image sensing technology and integrated circuit technology, and in particular relates to a CMOS sensor-memory-computing integrated circuit structure based on dynamic visual sensing technology.

Background technique

Represented by the development of big data technology and the rise of the deep learning technology wave with neural networks as the core, higher requirements have been placed on the computing power of traditional mainstream hardware platforms. Since the deep learning algorithm needs to process streaming data, when the hardware platform based on the von Neumann computing architecture processes related tasks, a large amount of data will flow between the computing unit and the storage unit. The reading and writing speed of the latter is much slower than the computing speed of the former. The operation process of accessing memory accounts for the vast majority of the overall energy consumption and delay, which limits the processing speed of data, which is called the "von Neumann bottleneck". " or "Memory Bottleneck". The "memory bottleneck" makes the computing system exhibit the disadvantages of high power consumption and slow speed. In computing tasks centered on large amounts of data, the problems brought about by the separation of storage and computing are even more prominent.

In this context, an integrated computing and storage architecture similar to the neural structure of the brain has gradually developed. As a model similar to the human brain, it integrates the data storage unit and the computing unit, which not only reduces data handling, but also It greatly improves the degree of computational parallelism and energy efficiency. What is certain is that, driven by the gradual maturity of technology and application requirements, the integrated computing and storage chips and their specific applications will accelerate their implementation.

At present, the research on the integrated circuit of storage and calculation only focuses on the two aspects of storage and calculation, and there are very few researches on the integrated circuit of storage and calculation combined with other applications, especially the integrated circuit of sensing and storage combined with the sensing circuit. circuit.

SUMMARY OF THE INVENTION

In order to solve the problems of the prior art, through the research on the existing CMOS active phase element circuit, it is found that the CMOS active phase element exists in the form of a large-scale pixel array, that is, the pixel array, the storage unit, and the operation unit are all in the form of a large-scale pixel array. is an independent circuit module. This von Neumann structure will inevitably lead to the need for separate data bus, address bus and control bus between different circuit modules, as well as corresponding decoding circuits and control circuits. This working mode has low operation speed and low power consumption. larger. Therefore, the present invention adopts the idea of integration of sensing, storage and calculation. By combining the CMOS dynamic visual sensing active phase element circuit with the integrated circuit of storage and calculation, the collection, storage and linearity of dynamic visual sensing data can be realized in one unit. operation. To achieve the purpose of saving storage area, reducing computing power consumption and improving computing speed.

The technical scheme adopted in the present invention is:

The CMOS sensor-memory-computing integrated circuit structure based on dynamic visual sensing technology is characterized in that it includes an AER-based sensor circuit module and a memory-computing integrated circuit module;

The sensing circuit module based on the AER method is used for sensing dynamic image data, and specifically includes a dynamic visual sensing active phase element circuit, a correlated resampling circuit, a differential comparator circuit, a light intensity change detection circuit and a logic judgment circuit. ;in,

The dynamic visual sensing active phase element circuit is used to sense the input optical signal and convert it into an electrical signal;

The correlated secondary sampling circuit is coupled to the output end of the dynamic visual sensing active phase element circuit, and is used for sampling and holding the converted output voltage signal in the reset period and the integration period respectively;

the differential comparator circuit, coupled to the output end of the correlated resampling circuit, is used to perform differential operation on the result of the resampling, and compare the operation result with the reference voltage;

The light intensity change detection circuit is used to sense whether the dynamic light intensity changes;

The logic determination circuit is respectively coupled to the differential comparator circuit and the light intensity change detection circuit, and is used for combining the data of the differential comparator and the light intensity detection circuit to perform validity determination and output the determination result; specifically: only when the differential comparison is performed If the detector determines that the light intensity has changed, and the light intensity detection circuit determines that the dynamic light intensity has changed, it will output valid data "1" and store it in the SRAM, otherwise it will store "0";

The integrated circuit module of storage and calculation is used to store and calculate dynamic image data, and specifically includes an SRAM unit, a weight writing circuit, a digital logic unit, an analog accumulator and a linear amplifier; wherein,

the SRAM unit, coupled to the output end of the logic decision circuit, for storing external weight data and sensing data;

the weight writing circuit, coupled to the input end of the SRAM unit, is used for writing external weight data to the SRAM unit;

The digital logic unit is coupled to the output end of the SRAM unit, and its circuit structure includes a multiplier for multiplying external weights and sensing data, a counter for identifying the multiplication result, and a counter for generating a pulse signal. Pulse generating unit;

The analog accumulator, coupled to the output end of the pulse generating unit, is used for accumulating the number of pulse signals in the form of capacitor charging, and converting them into analog voltage signals;

The linear amplifier, coupled to the output end of the analog accumulator, is used to further linearly amplify the analog voltage signal.

Further, the dynamic visual sensing active phase element circuit is mainly composed of a photodiode, a reset diode, a source follower, and a row selection switch; wherein,

The photodiode is used for sensing the external light intensity, and converting the light intensity into an induced current;

Under the control of the reset signal, the reset diode periodically works in the reset period and the integration period; in the reset period, the reset diode is turned on to charge the negative terminal node of the photodiode; in the integration period, the reset diode is turned off , the charge on the parasitic capacitance of the negative terminal node of the photodiode is linearly discharged by the induced current;

The source follower is used as a buffer, which can prevent the charge of the negative terminal node of the photodiode from leaking in the process of reading the signal;

The row selection switch tube is used to control the output of the signal.

Further, the correlated secondary sampling circuit is composed of a MOS switch tube controlled by a clock signal, a sampling capacitor, and a sampling signal reading circuit;

The MOS switch tube controlled by the clock signal is used to control the switch tube to be turned on at the end of the reset period and the integration period respectively, and to sample the voltage signals at these two moments;

the sampling capacitor is used to hold sampling data;

The sampling signal reading circuit is formed by connecting three P-type MOS transistors in series, and is used as a buffer for reading the sampling voltage result and increasing the level.

Further, the differential comparator circuit is composed of a differential operation circuit that realizes a differential function;

The differential operation circuit that realizes the differential function is composed of an operational amplifier and corresponding and four equal resistors, and can perform an equal-proportion difference operation on the two sampled voltages, and output a differential operation result, which represents the light intensity information. .

Further, the light intensity change detection circuit can determine whether the dynamic light intensity has changed, that is, by judging whether the change amount of the light intensity is equal in different periods, the change amount represents whether the image is a dynamic change, and only sampling the dynamic change is realized. light intensity data.

Further, the SRAM unit stores two parts of data respectively, one part is external weight data, and the other part is dynamic image sensing data.

Further, the weight writing circuit is used for writing external weight data to the SRAM cell, which includes 4 writing transistors and 2 parasitic capacitors. Because the SRAM requires that the data line must be precharged and predischarged before writing data to ensure the accuracy and stability of the written data.

Further, the circuit structure of the digital logic unit includes a multiplier for multiplying external weights and sensor data, a counter for identifying the multiplication result, and a pulse generating unit for generating a pulse signal;

The specific algorithm of the multiplier is that the external input weight and each bit of the sensing data perform a phase AND operation;

The counter is used to count the number of "1" in the data of the multiplication result;

The pulse generating unit emits an equal number of short-time pulse signals according to the counting result of the counter.

Further, the analog accumulator is composed of a charging transistor, a discharging transistor, a summing capacitor and a buffer, and its working principle is as follows: every time a pulse is received, the charging transistor will be turned on, and the summing capacitor will be charged once with a small current. When charging, the voltage on the capacitor is accumulated in equal proportions, so the digital signal result can be converted into an analog voltage signal; and when the capacitor is fully charged, all the charges are discharged by turning on the discharge transistor.

Further, the linear amplifier is composed of an operational amplifier and a corresponding resistor. The input of the operational amplifier is coupled to the output end of the analog accumulator, and can perform linear operation on the output result of the analog accumulator for further amplification.

The beneficial effect of the present invention is that: the present invention combines the existing CMOS memory-computing integrated chip with the dynamic visual sensing circuit adopting the Address-Event Representation (AER) technology, so that the present invention has high sampling rate, high Features of speed, high precision, and low latency.

Description of drawings

Figure 1 is a schematic diagram of the overall structure of a CMOS sensor-memory-computing integrated circuit based on dynamic visual sensing technology;

Fig. 2 is the concrete circuit structure schematic diagram of Fig. 1;

FIG. 3 is a schematic diagram of the structure of the active phase element circuit for dynamic vision sensing;

Figure 4 is a schematic diagram of the output voltage of the dynamic visual sensing active phase element circuit;

5 is a schematic diagram of the circuit structure of a correlated secondary sampling circuit;

6 is a schematic diagram of the working principle of the correlated secondary sampling circuit;

7 is a schematic diagram of the circuit structure of the differential comparator circuit;

8 is a schematic diagram of the circuit structure of a light intensity change detection circuit;

9 is a schematic diagram of the circuit structure of a logic decision circuit combining a differential comparator circuit and a light intensity change detection circuit;

Figure 10 is a schematic diagram of the output waveform of the key signal of the logic decision circuit when the light intensity changes in two consecutive cycles are the same;

11 is a schematic diagram of the output waveform of the key signal of the logic decision circuit when the light intensity changes in two consecutive cycles are different;

12 is a schematic diagram of the circuit structure of a weight writing circuit;

13 is a schematic diagram of the circuit structure of the SRAM cell;

14 is a schematic diagram of the overall circuit structure of the weight writing circuit and the SRAM cell;

Figure 15 is a schematic structural diagram of a digital logic circuit;

16 is a schematic diagram of the circuit structure of an analog accumulation circuit;

17 is a schematic diagram of the circuit structure of a linear amplifier;

18 is a schematic diagram of an output waveform of an analog accumulator and a linear amplifier for a pulse signal corresponding to an operation result;

FIG. 19 is another schematic structural diagram of a digital circuit for realizing multiplication of 4-bit weights and 1-bit sensing data.

Detailed ways

On the basis of the prior art, the present invention proposes a CMOS sensor-storage-computing integrated circuit structure based on dynamic visual sensing technology, which can realize the functions of dynamic visual sensing, storage and calculation on the same circuit. The pixel array formed by this circuit can not only realize the sensing and storage of larger-scale dynamic image data, but also realize more complex parallel operation processing.

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below through specific embodiments in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention, not for The invention is limited.

As shown in Figure 1, the overall architecture of a CMOS sensor-memory-computing integrated circuit based on dynamic visual sensing technology is composed of an AER-based sensing circuit module 1 and a memory-computing integrated circuit module 2; The circuit module 1 includes a dynamic visual sensing active phase element unit 3, a correlated secondary sampling circuit 5, a differential comparator circuit 7, a light intensity change detection circuit 9 and a logic judgment circuit 12; the storage-calculation integrated circuit module 2 includes a weight write Input circuit 15, SRAM unit 17, digital logic unit 19, analog accumulator 21 and linear amplifier circuit 23; the signal flow during circuit operation is as follows: first, the light intensity signal 14 from the outside is sensed by the DVS active phase element unit 3 and The induced voltage signal 4 is generated; the correlated secondary sampling circuit 5 samples the induced voltage signal 4 of different cycles respectively twice, and outputs the sampling result 6; the differential comparator circuit 7 performs the differential operation on the sampling result 6, and obtains the differential operation results 8 and 10; The light intensity detection circuit 9 obtains the light intensity change information 11 according to the multiplication result 8; the logic decision circuit 12 comprehensively processes the differential operation result 10 and the light intensity change information 11 to obtain the final sensing data 13; The external input weight 23 and the sensor data 13 written by the value writing circuit 15, and the stored data 18 is transmitted to the digital logic unit 19; in the digital logic unit 19, the external input weight 23 and the sensor data 13 are processed to obtain The multiplication result is sent to the analog accumulation circuit 21 with pulse signal data 20 ; the analog accumulation circuit 21 transmits the accumulated result 22 to the linear amplifier circuit 23 and obtains the final operation result 25 .

As shown in FIG. 2 , it is a schematic diagram of a specific circuit structure corresponding to FIG. 1 .

As shown in FIG. 3 , it is a schematic structural diagram of the dynamic visual sensing active phase element circuit 3 . This dynamic visual sensing active pixel unit is called a 4-tube structure. In addition to the photodiode 31, the pixel unit also includes a reset tube 26, a source follower tube 27 and a row selector tube 28, as well as a bias tube. placed transistor 30. The working principle of the pixel is as follows: under the control of the reset signal 21, the photodiode 31 experiences two cycles in each working process: a charging cycle and an integration cycle. During the charging period, the reset signal 21 is kept at a high level, the reset transistor 26 is turned on and the parasitic capacitance of the node 32 is charged to VDD-Vth, where Vth is the threshold voltage of the reset transistor 26; during the integration period, the reset transistor 26 is turned off, When the photodiode 31 is illuminated with a certain intensity, the charges stored in the parasitic capacitance on the node 32 are discharged by the induced current generated by the photodiode, so that the voltage on the node 32 decreases linearly. These two duty cycles are repeated, and the external light intensity change information can be sensed in real time through the photodiode 31, and the voltage signal on the node 32 can be read out through the source follower 27 and the row selection switch 28 without loss. , which is the output voltage signal 29 .

As shown in FIG. 4 , it is a schematic diagram of the output voltage of the dynamic visual sensing active phase element circuit 3 . Each cycle T is divided into charge cycles and sub-cycles; during charge cycle 0-t1, node 32 is charged to VDD-Vth causing output node 29 to be charged to Vr, where Vr is approximately VDD-2Vth; during integration period t1-t2 , due to the existence of the induced current, the voltage on the node 32 decreases approximately linearly, so the voltage of the output node 39 also decreases approximately linearly to vs1; similarly, the situation of the second cycle T can be analyzed.

As shown in FIG. 5, the correlated secondary sampling circuit 5 has the same two sampling paths, and its circuit consists of sampling tubes 33 and 40, sampling capacitors 35 and 42, source followers 38 and 45, switching tubes 37 and 44, and biasing tubes. Tubes 36 and 43 are formed. The working principle of the circuit is as follows: at the end of the charging cycle, the sampling tube 33 is turned on by the control signal 34, the output voltage 29 is sampled and the sampling voltage is stored in the sampling capacitor 35, the sampling voltage is read out through the source follower 38, at the switch The source node of the tube 37 obtains the sampling voltage 39 of the charging period;

As shown in FIG. 6 , it is a schematic diagram of the working principle of the correlated resampling circuit 5 . According to the change of the output voltage of the dynamic visual sensing active phase element circuit 3, at the end of the charging cycle, when the voltage of the node 29 is charged to vr, the control signal 34 of the sampling tube 33 generates a pulse signal, and the node 29 The voltage vr is sampled into the sampling capacitor 35, because the charging cycle will make the voltage of the node 29 rise to vr each time, so vr remains unchanged after Read out to node VR and keep it unchanged, where VR is about vr+Vth; at the end of the integration period, the voltage of node 29 decreases to the minimum value of a period, and the control signal 41 of the sampling tube 40 generates a pulse signal at this time , the voltage vs1 of node 29 is sampled into the sampling capacitor 42, and the sampled voltage is read out to the node VS through the follower 45 and the switch tube 44 without loss and remains unchanged, where VS is about vs1+Vth until the next sampling. The situation of the second cycle T can be obtained by the same analysis.

As shown in FIG. 7 , which is a schematic diagram of the differential comparator circuit 7 , the differential comparator is mainly composed of a differential circuit and a comparator circuit. The differential circuit consists of three equal resistors 40, 42 and 43 (all resistance values are R), a feedback resistor 42 (resistance value Rf) and a high-precision operational amplifier 44. If the resistance value R=Rf is selected, it is composed of " The principle of "virtual short" and "virtual off" can be deduced that the output of the operational amplifier is: VD=VR-VS, so by comparing VD with the reference voltage Vrefh, it can be concluded whether enough light intensity is induced in a period T. If VD is large, it means that the voltage of VS changes greatly during the integration period, that is, enough light intensity information is sensed, so the comparator 45 outputs a high level, otherwise it outputs a low level.

As shown in FIG. 8, it is a schematic diagram of the light intensity change detection circuit 9, which is also composed of a differential comparison circuit and a double comparator circuit. The differential comparison circuit consists of three equal resistors 46, 47, 48 (all resistance values are R), a feedback resistor 49 (resistance value is Rf) and a high-precision operational amplifier 50. If the resistance value R=Rf is selected, It can be concluded from the same analysis as above: △V=VD2-VD1', where VD2 represents the voltage VD of the node 54 calculated by the differential comparison circuit in the current cycle T, and VD1' represents the previous cycle T calculated by the differential comparison circuit The voltage VD of the node 54, wherein VD1' can be realized by a buffer 53, so that the change of the VD voltage in two adjacent periods T can be detected. Then compare the obtained △V with the two reference voltages ±Vrefl at the same time. As long as the change of △V is higher than ﹢Vrefl or lower than ﹣Vrefl, the circuit will output a high level to indicate that the dynamic change of light intensity is detected. Otherwise, the circuit outputs a low level. Through this circuit, the detection of the dynamic change of light intensity can be realized, that is, the light intensity data in this period T can be detected only when the light intensity change in this period T is different from the light intensity change in the previous period T. .

As shown in FIG. 9 , it is a schematic diagram of the circuit structure of the logic determination circuit 12 combined with the differential comparator circuit 7 and the light intensity change detection circuit 9 . The circuit is mainly composed of the comparator 44 in the differential comparator circuit 7, the comparators 51, 52 in the light intensity conversion detection circuit 9, the logic OR gate 55, and the logic AND gate 56. Its working principle is as follows: only when the differential comparator The circuit 7 senses the light intensity information of sufficient intensity, and the light intensity detection circuit 9 detects that the light intensity change of this cycle T is inconsistent with the light intensity change of the previous cycle T, and it will overall determine that the dynamic light intensity information is detected, and Output high, otherwise output low.

As shown in Figure 10, it is a schematic diagram of the output waveforms of the key signals VC, VCD and VA of the logic decision circuit 12 when the light intensity changes in two consecutive cycles are the same; Within T, sufficient light intensity was sensed, resulting in the same voltage change. Therefore, although the differential comparator circuit 7 outputs a high level indicating that the light intensity is sensed, the light intensity change detection circuit 9 does not sense the dynamically changing light intensity information, so it outputs a low level. At the same time, the logic decision circuit also outputs a low level.

As shown in Figure 11, it is a schematic diagram of the output waveforms of the key signals VC, VCD and VA of the logic decision circuit 12 when the light intensity changes in two consecutive cycles; Within T, sufficient light intensity was sensed, but the amount of voltage change generated in the two periods was not the same. Therefore, the differential comparator circuit 7 outputs a high level to indicate that the light intensity is sensed, and the light intensity change detection circuit 9 also senses the dynamically changing light intensity information, so it also outputs a high level. At the same time, the logic decision circuit also outputs a high level, which means that the dynamic sensing data is recognized, and the data is stored in the SRAM unit 17 .

As shown in FIG. 12, it is a schematic diagram of the structure of the weight writing circuit 15, which is mainly composed of writing tubes 59, 60, and bias tubes 57, 58, of which 61 and 62 are parasitic capacitors, and its working principle is as follows: When the corresponding weight data W needs to be written, the input signal 63 and its inverted signal 64 need to be input at the same time. Assuming that data "1" needs to be written to the SRAM cell 17, the input signal 63 is low level, and its inverted signal 64 is high level, the node 65 (BL) is pulled down to GND, and the node 66 (BLB) is charged to VDD at the same time, the write data "0" can also be analyzed in the same way, and then through the corresponding control with the SRAM cell 17 The weight data can be stably written into the SRAM cell 17 by the coordination of the signals.

As shown in FIG. 13, it is a schematic diagram of the structure of a single storage unit of the SRAM unit 17. The CMOS inverter composed of the PMOS transistor 67 and the NMOS transistor 71 is connected end to end with the CMOS inverter composed of the PMOS transistor 68 and the NMOS transistor 72. The structure is the classic SRAM structure, which can be used to store 1-bit data. To store data "1", signal 65 (BL) is required to remain high and signal 66 (BLB) to remain low; to store data "0", signal 65 (BL) is required to remain low, and Signal 66 (BLB) remains high. When data needs to be stored in the SRAM unit 17, it needs to be preprocessed by the weight writing circuit 15 first, that is, when the weight writing circuit 15 precharges the data node 65 (BL) and the node 66 (BLB), After the write data is ready, the write control signal 73 remains at a high level, allowing data to be written, and at this time, the writing of the weight data is completed; the sensor data is also stored in the SRAM unit 17, and the principle of writing is the same as above. described.

As shown in FIG. 14 , it is a schematic diagram of the overall circuit structure of the weight writing circuit and the SRAM cell.

As shown in FIG. 15 , it is a schematic diagram of the structure of the digital logic unit 19 . The digital logic unit 19 is implemented by a digital circuit and mainly includes a multiplier 76 , a counter 77 , and a pulse generating unit 78 . Assuming that the external weight data and the sensing data are both 1-bit data, the specific algorithm of the multiplier 76 is that the external input weight and the sensing data are summed; the counter is used to count the multiplication result. The number of "1" appears in the data; and the pulse generating unit emits an equal number of short-time pulse signals according to the statistical result of the counter.

As shown in FIG. 16, it is a schematic diagram of the circuit structure of the analog accumulator 21, which is mainly composed of a charging tube 80, a discharging tube 81, a summing capacitor 84 and a buffer 86. The working principle is as follows: the hold signal 83 is at a low level , as long as the above-mentioned pulse generating unit 78 emits a pulse, the charging tube 80 will charge the summing capacitor 84 for an equal time, a short time, and a small current, and the charging current will form a summation on the summing capacitor 84 The voltage is read out to the subsequent circuit by the buffer 86, and the summed voltage can also be cleared by the discharge tube 81.

As shown in FIG. 17, it is a schematic diagram of the linear amplifier 23, which is composed of a high-precision operational amplifier 90, an input resistor 87, a matching resistor 88, and a feedback resistor 89. According to the principle of “virtual short” and “virtual short” of the operational amplifier, the Deduce: VOUT=-R2/R1*Va, namely can carry on the linear operation to the output result of the analog accumulator, further enlarge, obtain the final output VOUT of the system.

As shown in FIG. 18 , it is a schematic diagram of the output voltage when the analog accumulator 21 and the linear amplifier 23 work. As can be seen from the figure, after the digital logic unit 19 obtains the result of the multiplication operation, the pulse generating unit 78 sends a corresponding pulse signal to the analog accumulator 21 to charge the analog accumulator 21 . Each time a pulse signal is generated, the voltage VQ on the analog accumulator 21 increases by Δv, and can be read out by the linear amplifier 23 through the voltage follower 86 and can be amplified by -R2/R1 times.

As shown in FIG. 19 , it is another schematic diagram of the digital circuit structure that realizes the multiplication operation of 4-bit weight and 1-bit sensing data. The structure and working principle of the weight writing circuit 15 , the logic decision circuit 12 , and the SRAM cell remain unchanged, while the external input weight 23 first stores 4-bit weight data into the SRAM cell 17 . The 4-bit weight data and 1-bit sensor data are operated, and the specific rule of the multiplication operation is changed to: the 4-bit weight data and the 1-bit sensor data are ANDed; If a "1" is entered, the 4-bit weight data is accumulated to the 8-bit adder 100 once; if the data stored in the SRAM unit 17 by the logic decision circuit 12 is "0", the previous data in the 8-bit adder 100 is saved. , until the 8-bit adder 100 overflows, and the 8-bit adder 100 is cleared at this time. The initial value of the 8-bit adder 100 is set to 8'b00000000. The digital logic unit 98 can also be implemented by digital circuits.

Claims (10)

1. A CMOS sensor-memory-computing integrated circuit structure based on dynamic visual sensing technology, characterized in that it includes an AER-based sensor circuit module and a memory-computing integrated circuit module; The sensing circuit module based on the AER method is used for sensing dynamic image data, and specifically includes a dynamic visual sensing active phase element circuit, a correlated resampling circuit, a differential comparator circuit, a light intensity change detection circuit and a logic judgment circuit. ;in, The dynamic visual sensing active phase element circuit is used to sense the input optical signal and convert it into an electrical signal; The correlated secondary sampling circuit is coupled to the output end of the dynamic visual sensing active phase element circuit, and is used for sampling and holding the converted output voltage signal in the reset period and the integration period respectively; the differential comparator circuit, coupled to the output end of the correlated resampling circuit, is used to perform differential operation on the result of the resampling, and compare the operation result with the reference voltage; The light intensity change detection circuit is used to sense whether the dynamic light intensity changes; The logic determination circuit is respectively coupled to the differential comparator circuit and the light intensity change detection circuit, and is used for combining the data of the differential comparator and the light intensity detection circuit to perform validity determination and output the determination result; specifically: only when the differential comparison is performed If the detector determines that the light intensity has changed, and the light intensity detection circuit determines that the dynamic light intensity has changed, it will output valid data "1" and store it in the SRAM, otherwise it will store "0"; The integrated circuit module of storage and calculation is used to store and calculate dynamic image data, and specifically includes an SRAM unit, a weight writing circuit, a digital logic unit, an analog accumulator and a linear amplifier; wherein, the SRAM unit, coupled to the output end of the logic decision circuit, for storing external weight data and sensing data; the weight writing circuit, coupled to the input end of the SRAM unit, is used for writing external weight data to the SRAM unit; The digital logic unit is coupled to the output end of the SRAM unit, and its circuit structure includes a multiplier for multiplying external weights and sensing data, a counter for identifying the multiplication result, and a counter for generating a pulse signal. Pulse generating unit; The analog accumulator, coupled to the output end of the pulse generating unit, is used for accumulating the number of pulse signals in the form of capacitor charging, and converting them into analog voltage signals; The linear amplifier, coupled to the output end of the analog accumulator, is used to further linearly amplify the analog voltage signal. 2 . The integrated circuit structure of CMOS sensor storage and calculation based on dynamic visual sensing technology according to claim 1 , wherein the dynamic visual sensing active phase element circuit is mainly composed of a photodiode, a reset diode, and a source follower. 3 . It is composed of a controller and a row selection switch; among them, The photodiode is used for sensing the external light intensity, and converting the light intensity into an induced current; Under the control of the reset signal, the reset diode periodically works in the reset period and the integration period; in the reset period, the reset diode is turned on to charge the negative terminal node of the photodiode; in the integration period, the reset diode is turned off , the charge on the parasitic capacitance of the negative terminal node of the photodiode is linearly discharged by the induced current; The source follower is used as a buffer, which can prevent the charge of the negative terminal node of the photodiode from leaking in the process of reading the signal; The row selection switch tube is used to control the output of the signal. 3. The CMOS sensor-storage-calculation integrated circuit structure based on dynamic visual sensing technology according to claim 2, wherein the correlated secondary sampling circuit is controlled by a clock signal MOS switch tube, sampling capacitor, sampling signal Read circuit composition; The MOS switch tube controlled by the clock signal is used to control the switch tube to be turned on at the end of the reset period and the integration period respectively, and to sample the voltage signals at these two moments; the sampling capacitor is used to hold sampling data; The sampling signal reading circuit is formed by connecting three P-type MOS transistors in series, and is used as a buffer for reading the sampling voltage result and increasing the level. 4. The CMOS sensor-storage-computing integrated circuit structure based on dynamic visual sensing technology according to claim 3, wherein the differential comparator circuit is composed of a differential arithmetic circuit that realizes a differential function; The differential operation circuit that realizes the differential function is composed of an operational amplifier and corresponding and four equal resistors, and can perform an equal-proportion difference operation on the two sampled voltages, and output a differential operation result, which represents the light intensity information. . 5. The CMOS sensor-storage-calculation integrated circuit structure based on dynamic visual sensing technology according to claim 4, wherein the light intensity change detection circuit can determine whether the dynamic light intensity has changed, that is, by judging the light intensity Whether the amount of change of the image is equal in different periods, the amount of change represents whether the image is a dynamic change, and only the light intensity data of the dynamic change can be sampled. 6. The CMOS sensor-storage-calculation integrated circuit structure based on dynamic visual sensing technology according to claim 5, wherein the SRAM unit stores two parts of data respectively, one part of which is external weight data, and the other part is Dynamic image sensor data. 7 . The integrated circuit structure of CMOS sensing and storage based on dynamic visual sensing technology according to claim 6 , wherein the weight writing circuit is used to write external weight data to the SRAM cell, which comprises: 8 . 4 write transistors and 2 parasitic capacitors. 8. The CMOS sensor-memory-calculation integrated circuit structure based on dynamic visual sensing technology according to claim 7, wherein the digital logic unit circuit structure comprises a circuit for multiplying external weights and sensing data. a multiplier, a counter for identifying the multiplication result, a pulse generating unit for generating a pulse signal; The specific algorithm of the multiplier is that the external input weight and each bit of the sensing data perform a phase AND operation; The counter is used to count the number of "1"s in the data of the multiplication result; The pulse generating unit emits an equal number of short-time pulse signals according to the counting result of the counter. 9 . The integrated circuit structure of CMOS sensing and storage based on dynamic visual sensing technology according to claim 8 , wherein the analog accumulator is composed of a charging transistor, a discharging transistor, a summing capacitor and a buffer. The working principle is as follows: every time a pulse is received, the charging transistor will be turned on, the summing capacitor will be charged once with a small current, and the voltage on the capacitor will be accumulated in equal proportions, so the digital signal result can be converted into an analog voltage signal; When the capacitor is fully charged, all the charges are discharged by turning on the discharge transistor. 10. The CMOS sensor-memory-calculation integrated circuit structure based on dynamic visual sensing technology according to claim 9, wherein the linear amplifier is composed of an operational amplifier and a corresponding resistor, and the input of the operational amplifier is the same as the analog signal. The output end of the accumulator is coupled to perform linear operation on the output result of the analog accumulator for further amplification.

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