CN111326516A - Non-volatile memory structure and manufacturing method thereof - Google Patents

Abstract

The invention discloses a non-volatile memory structure and a manufacturing method thereof, wherein the non-volatile memory structure includes a substrate, a selection gate, a first charge storage layer, a control gate and a first dielectric layer. There is a groove extending in the base along the first direction. The select gate is disposed in the trench. The first charge storage layer is disposed on the sidewalls of the trench. The first charge storage layer has a first side and a second side opposite to each other. The first side and the second side are arranged in the first direction. The control gate is disposed on the selection gate and the first charge storage layer in the trench. The control gate covers the first side and the second side. The first dielectric layer is disposed between the control gate and the first charge storage layer.

Description

Non-volatile memory structure and method of making the same

technical field

The present invention relates to a memory structure and a method of fabricating the same, and more particularly, to a non-volatile memory structure and a method of fabricating the same.

Background technique

Because non-volatile memory (non-volatile memory) can perform operations such as storing, reading and erasing data for many times, and when the power supply is interrupted, the stored data will not disappear, the data access time is short, and It has the advantages of low power consumption and so on, so it has become a kind of memory widely used in personal computers and electronic equipment. However, how to further improve the electrical performance of the memory device is a goal that the industry continues to strive for.

SUMMARY OF THE INVENTION

The present invention provides a non-volatile memory structure and a manufacturing method thereof, which can effectively improve the electrical performance of the memory element.

The present invention provides a non-volatile memory structure including a substrate, a selection gate, a first charge storage layer, a control gate and a first dielectric layer. There is a trench in the substrate extending along the first direction. The select gate is disposed in the trench. The first charge storage layer is disposed on the sidewalls of the trench. The first charge storage layer has a first side surface and a second side surface opposite to each other. The first side surface and the second side surface are arranged in the first direction. The control gate is disposed on the select gate and the first charge storage layer in the trench. The control gate covers the first side and the second side. The first dielectric layer is disposed between the control gate and the first charge storage layer.

According to an embodiment of the present invention, in the above non-volatile memory structure, the select gate, the first charge storage layer, the control gate and the substrate can be electrically insulated from each other.

According to an embodiment of the present invention, in the above non-volatile memory structure, the first charge storage layer is, for example, a floating gate.

According to an embodiment of the present invention, in the above non-volatile memory structure, the first charge storage layer may further have a third side surface connected between the first side surface and the second side surface. The control gate may cover the third side.

According to an embodiment of the present invention, the above-mentioned non-volatile memory structure may further include a second charge storage layer. The second charge storage layer is disposed on the other sidewall of the trench. The second charge storage layer may have fourth and fifth sides opposite to each other. The fourth side surface and the fifth side surface may be arranged in the first direction. The control gate may cover the fourth side and the fifth side. The first dielectric layer is disposed between the control gate and the second charge storage layer.

According to an embodiment of the present invention, in the above non-volatile memory structure, the first charge storage layer and the second charge storage layer may be arranged in the second direction. The second direction may intersect the first direction.

According to an embodiment of the present invention, in the above non-volatile memory structure, the second charge storage layer may further have a sixth side surface connected between the fourth side surface and the fifth side surface. The control gate may cover the sixth side surface.

According to an embodiment of the present invention, the above-mentioned non-volatile memory structure may further include a first doped region and a second doped region. The first doped region is located in the substrate below the trench. The second doped region is located in the substrate on one side of the trench.

According to an embodiment of the present invention, the above-mentioned non-volatile memory structure may further include a third doped region. The third doped region is located in the substrate on the other side of the trench.

According to an embodiment of the present invention, the above non-volatile memory structure may further include a second dielectric layer and a third dielectric layer. The second dielectric layer is disposed between the select gate and the substrate. The third dielectric layer is disposed between the first charge storage layer and the substrate.

The present invention provides a method for manufacturing a non-volatile memory structure, which includes the following steps. A trench extending along the first direction is formed in the substrate. A select gate is formed in the trench. A first charge storage layer is formed on the sidewalls of the trench. The first charge storage layer has a first side surface and a second side surface opposite to each other. The first side surface and the second side surface are arranged in the first direction. A control gate is formed on the select gate and the first charge storage layer in the trench. The control gate covers the first side and the second side. A first dielectric layer is formed between the control gate and the first charge storage layer.

According to an embodiment of the present invention, in the above-mentioned manufacturing method of the non-volatile memory structure, the select gate, the first charge storage layer, the control gate and the substrate can be electrically insulated from each other.

According to an embodiment of the present invention, in the above-mentioned manufacturing method of the non-volatile memory structure, the first charge storage layer may further have a third side surface connected between the first side surface and the second side surface. The control gate may cover the third side.

According to an embodiment of the present invention, in the above-mentioned manufacturing method of the non-volatile memory structure, the method for forming the first charge storage layer and the first dielectric layer may include the following steps. A layer of charge storage material is formed conformally in the trench. An etch-back fabrication process is performed on the charge storage material layer to form charge storage spacers on the sidewalls of the trenches. A patterned fabrication process is performed on the charge storage spacers to form a first charge storage layer. After forming the first charge storage layer, a first dielectric layer overlying the first charge storage layer is formed.

According to an embodiment of the present invention, in the above-mentioned manufacturing method of the non-volatile memory structure, the method may further include forming a second charge storage layer on the other sidewall of the trench. The second charge storage layer may have fourth and fifth sides opposite to each other. The fourth side surface and the fifth side surface may be arranged in the first direction. The control gate may cover the fourth side and the fifth side. The first dielectric layer is disposed between the control gate and the second charge storage layer.

According to an embodiment of the present invention, in the above-mentioned manufacturing method of the non-volatile memory structure, the first charge storage layer and the second charge storage layer may be arranged in the second direction. The second direction may intersect the first direction.

According to an embodiment of the present invention, in the above-mentioned manufacturing method of the non-volatile memory structure, the second charge storage layer may further have a sixth side surface connected between the fourth side surface and the fifth side surface. The control gate may cover the sixth side surface.

According to an embodiment of the present invention, the method for fabricating the above non-volatile memory structure may further include the following steps. A first doped region is formed in the substrate below the trench. A second doped region is formed in the substrate on one side of the trench.

According to an embodiment of the present invention, in the above-mentioned manufacturing method of the non-volatile memory structure, the method may further include forming a third doped region in the substrate on the other side of the trench.

According to an embodiment of the present invention, the method for fabricating the above non-volatile memory structure may further include the following steps. A second dielectric layer may be formed between the select gate and the substrate. A third dielectric layer may be formed between the first charge storage layer and the substrate.

Based on the above, in the non-volatile memory structure and the manufacturing method thereof proposed by the present invention, the control gate is disposed on the first charge storage layer and covers the first side and the second side of the first charge storage layer, and the first A dielectric layer is disposed between the control gate and the first charge storage layer. Therefore, the control gate and the first charge storage layer can also be coupled at the first side and the second side of the first charge storage layer, thereby increasing the coupling area between the control gate and the first charge storage layer. In this way, the non-volatile memory structure proposed by the present invention can have a higher coupling ratio, and thus can effectively improve the electrical performance of the memory device.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

Description of drawings

1A to 1J are top views of a manufacturing process of a non-volatile memory structure according to an embodiment of the present invention;

Figures 2A to 2J are cross-sectional views along the section line I-I' in Figures 1A to 1J, respectively;

3A to 3J are cross-sectional views taken along the line II-II' in FIGS. 1A to 1J, respectively.

Symbol Description

10: Non-volatile memory structure

100: base

102: Isolation Structure

104: Patterning the hard mask layer

106: Groove

108, 128, 130: doped regions

110, 110a, 114, 124: Dielectric layers

112: Select the gate material layer

112a: select gate

116: charge storage material layer

118, 120: Charge storage spacers

118a, 120a: charge storage layer

122: Patterned Photoresist Layer

126: Control gate material layer

126a: Control Gate

AA: Active (active) area

D1: first direction

D2: second direction

S1～S6: Side

TS1, TS2: Top surface

Detailed ways

1A to 1J are top views of a manufacturing process of a non-volatile memory structure according to an embodiment of the present invention. 2A to 2J are cross-sectional views along the line I-I' in FIGS. 1A to 1J . 3A to 3J are cross-sectional views along the line II-II' in FIGS. 1A to 1J .

Referring to FIG. 1A , FIG. 2A and FIG. 3A , an isolation structure 102 may be formed in the substrate 100 , and an active area AA may be defined in the substrate 100 by the isolation structure 102 . The substrate 100 may be a semiconductor substrate, such as a silicon substrate. The material of the isolation structure 102 is, for example, silicon oxide. The isolation structure 102 is, for example, a shallow trench isolation (STI) structure, but the invention is not limited thereto. The formation method of the isolation structure 102 is, for example, performing a shallow trench isolation fabrication process. In addition, the active areas AA may be arranged in the first direction D1 and may extend in the second direction D2. The second direction D2 may intersect with the first direction D1. In this embodiment, the second direction D2 is perpendicular to the first direction D1 as an example for description, but the present invention is not limited to this.

Referring to FIG. 1B , FIG. 2B and FIG. 3B , a patterned hard mask layer 104 is formed on the substrate 100 . The material of the patterned hard mask layer 104 is, for example, silicon nitride. The formation method of the patterned hard mask layer 104 is, for example, a combination of deposition process, photolithography process and etching process.

Next, part of the substrate 100 and part of the isolation structure 102 can be removed by using the patterned hard mask layer 104 as a mask, and a trench 106 extending along the first direction D1 is formed in the substrate 100 . A method for removing part of the substrate 100 and part of the isolation structure 102 is, for example, dry etching.

Then, doped regions 108 may be formed in the substrate 100 below the trenches 106 . The doped regions 108 can be used as source lines. In this embodiment, the doped region 108 is described by taking an N-type doped region as an example, but the present invention is not limited thereto. In another embodiment, the doped region 108 can also be a P-type doped region. The method for forming the doped region 108 is, for example, an ion implantation method.

Referring to FIGS. 1C , 2C and 3C , a dielectric layer 110 may be formed on the surface of the trench 106 . The material of the dielectric layer 110 is, for example, silicon oxide. The formation method of the dielectric layer 110 is, for example, a thermal oxidation method.

Next, a select gate material layer 112 filling the trenches 106 may be formed. The material of the selection gate material layer 112 is, for example, a conductor material such as doped polysilicon. The formation method of the selection gate material layer 112 is, for example, a chemical vapor deposition method.

Referring to FIG. 1D , FIG. 2D and FIG. 3D , an etch-back process may be performed on the select gate material layer 112 to remove the select gate material layer 112 outside the trench 106 and form a select gate in the trench 106 112a.

Then, the hard mask layer 104 may be removed. The removal method of the hard mask layer 104 is, for example, a wet etching method. Furthermore, a portion of the dielectric layer 110 not covered by the select gate 112 a may be removed, and the dielectric layer 110 a may be formed between the select gate 112 a and the substrate 100 . The dielectric layer 110a may serve as a gate dielectric layer. Thus, the select gate 112a and the substrate 100 can be electrically insulated from each other. A method for removing part of the dielectric layer 110 is, for example, a wet etching method. In this embodiment, the hard mask layer 104 is removed first, and then part of the dielectric layer 110 is removed, but the invention is not limited to this. In another embodiment, part of the dielectric layer 110 may be removed first, and then the hard mask layer 104 may be removed.

Referring to FIG. 1E , FIG. 2E and FIG. 3E , a dielectric layer 114 may be formed on the surface of the trench 106 . In addition, the dielectric layer 114 may be further formed on the top surface of the substrate 100 and the top surface of the select gate 112a. The dielectric layer 114 may serve as a tunneling dielectric layer. The material of the dielectric layer 114 is, for example, silicon oxide. The formation method of the dielectric layer 114 is, for example, a thermal oxidation method or a chemical vapor deposition method. In this embodiment, the formation method of the dielectric layer 114 is described by taking the thermal oxidation method as an example.

Next, the charge storage material layer 116 may be conformally formed in the trenches 106 . The material of the charge storage material layer 116 may be a floating gate material, such as doped polysilicon or undoped polysilicon.

Referring to FIG. 1F , FIG. 2F and FIG. 3F , an etch-back fabrication process may be performed on the charge storage material layer 116 . Thus, charge storage spacers 118 may be formed on one sidewall of trench 106 and charge storage spacers 120 may be formed on the other sidewall of trench 106 .

Referring to FIGS. 1G , 2G and 3G , a patterned photoresist layer 122 may be formed on the dielectric layer 114 and the charge storage material layer 116 . The patterned photoresist layer 122 may have openings 122a exposing portions of the charge storage material layer 118 and portions of the charge storage material layer 120 . The formation method of the patterned photoresist layer 122 is, for example, a photolithography process.

Referring to FIGS. 1H , 2H and 3H, a portion of the charge storage spacer 118 and a portion of the charge storage spacer 120 may be removed by using the patterned photoresist layer 122 as a mask. Thus, a patterning process can be performed on the charge storage spacers 118 and the charge storage spacers 120 to form the charge storage layer 118 a on the sidewall of the trench 106 and the charge storage layer 118 a on the other sidewall of the trench 106 storage layer 120a. The charge storage layer 118a and the charge storage layer 120a may be arranged in the second direction D2. The charge storage layer 118a and the charge storage layer 120a are, for example, floating gates.

The charge storage layer 118a has a side surface S1 and a side surface S2 opposite to each other. The side surface S1 and the side surface S2 are arranged in the first direction D1. In addition, the charge storage layer 118a may further have a top surface TS1 and a side surface S3 connected between the side surface S1 and the side surface S2. The dielectric layer 114 may be disposed between the charge storage layer 118a and the substrate 100 and between the charge storage layer 118a and the select gate 112a. Therefore, the charge storage layer 118 a and the substrate 100 may be electrically insulated from each other by the dielectric layer 114 , and the charge storage layer 118 a and the select gate 112 a may be electrically insulated from each other by the dielectric layer 114 .

The charge storage layer 120a may have a side surface S4 and a side surface S5 opposite to each other. The side surface S4 and the side surface S5 may be arranged in the first direction D1. In addition, the charge storage layer 120a may further have a top surface TS2 and a side surface S6 connected between the side surface S4 and the side surface S5. The dielectric layer 114 may be disposed between the charge storage layer 120a and the substrate 100 and between the charge storage layer 120a and the selection gate 112a. Thus, the charge storage layer 120a and the substrate 100 may be electrically insulated from each other, and the charge storage layer 120a and the selection gate 112a may be electrically insulated from each other.

Then, the patterned photoresist layer 122 can be removed. The removal method of the patterned photoresist layer 122 is, for example, dry stripping or wet stripping.

Referring to FIGS. 1I, 2I and 3I, after the charge storage layer 118a is formed, a dielectric layer 124 covering the charge storage layer 118a may be formed. The material of the dielectric layer 124 is, for example, silicon oxide, silicon nitride, or a combination thereof. The dielectric layer 124 may be a multi-layer structure or a single-layer structure. For example, the dielectric layer 124 may be a composite layer of a silicon oxide layer/silicon nitride layer/silicon oxide layer (ONO). The formation method of the dielectric layer 124 is, for example, a chemical vapor deposition method. The dielectric layer 124 may cover the top surface TS1, the side surface S1, the side surface S2 and the side surface S3 of the charge storage layer 118a, and may cover the top surface TS2, the side surface S4, the side surface S5 and the side surface S6 of the charge storage layer 120a.

Next, a control gate material layer 126 may be formed in the trenches 106 . The material of the control gate material layer 126 is, for example, a conductor material such as doped polysilicon. The formation method of the control gate material layer 126 is, for example, a chemical vapor deposition method.

Referring to FIGS. 1J , 2J and 3J , a portion of the control gate material layer 126 outside the trench 106 may be removed and formed on the select gate 112 a , the charge storage layer 118 a and the charge storage layer 120 a in the trench 106 Control gate 126a. A method for removing part of the control gate material layer 126 is, for example, chemical mechanical polishing (CMP). The control gate 126a may cover the top surface TS1, the side surface S1, the side surface S2 and the side surface S3 of the charge storage layer 118a, and may cover the top surface TS2, the side surface S4, the side surface S5 and the side surface S6 of the charge storage layer 120a. Dielectric layer 124 may be disposed between control gate 126a and charge storage layer 118a, between control gate 126a and charge storage layer 120a, between control gate 126a and select gate 112a, and between control gate 126a and substrate 100 between. Therefore, the control gate 126a can be electrically insulated from the charge storage layer 118a, the charge storage layer 120a, the select gate 112a, and the substrate 100 at least through the dielectric layer 124 from each other.

Then, doped regions 128 can be formed in the substrate 100 on one side of the trenches 106 and doped regions 130 can be formed in the substrate 100 on the other side of the trenches 106 . The doped region 128 and the doped region 130 can be used as a source electrode or a drain electrode, respectively. In this embodiment, the doped region 128 and the doped region 130 are described by taking the N-type doped region as an example, but the present invention is not limited thereto. In another embodiment, the doped regions 128 and 130 can also be P-type doped regions. The method for forming the doped region 128 and the doped region 130 is, for example, an ion implantation method.

Hereinafter, the non-volatile memory structure 10 of this embodiment will be described with reference to FIG. 1J , FIG. 2J and FIG. 3J . In addition, although the method for forming the non-volatile memory structure 10 is described by taking the above method as an example, the present invention is not limited thereto.

1J , FIG. 2J and FIG. 3J , the non-volatile memory structure 10 includes a substrate 100 , a select gate 112 a , a charge storage layer 118 a , a control gate 126 a and a dielectric layer 124 . There are trenches 106 in the substrate 100 extending along the first direction D1. Select gate 112a is disposed in trench 106 . A charge storage layer 118a is disposed on the sidewalls of the trench 106 and on the select gate 112a. The charge storage layer 118a has a side surface S1 and a side surface S2 opposite to each other. The side surface S1 and the side surface S2 are arranged in the first direction D1. The charge storage layer 118a may also have a top surface TS1 and a side surface S3 connected between the side surface S1 and the side surface S2. The charge storage layer 118a is, for example, a floating gate. Control gate 126a is disposed in trench 106 on select gate 112a and charge storage layer 118a. The control gate 126a may cover the top surface TS1, the side surface S1, the side surface S2 and the side surface S3 of the charge storage layer 118a. A dielectric layer 124 is disposed between the control gate 126a and the charge storage layer 118a.

In addition, the non-volatile memory structure 10 may further include at least one of the isolation structure 102 , the doped region 108 , the dielectric layer 110 a , the dielectric layer 114 , the charge storage layer 120 a , the doped region 128 and the doped region 130 . The select gate 112a, the charge storage layer 118a, the charge storage layer 120a, the control gate 126a and the substrate 100 may be electrically insulated from each other by the dielectric layer 110a, the dielectric layer 114 and the dielectric layer 124. The isolation structure 102 is disposed in the substrate 100 . The doped regions 108 are located in the substrate 100 below the trenches 106 . The dielectric layer 110a is disposed between the select gate 112a and the substrate 100 . The dielectric layer 114 is disposed between the charge storage layer 118 a and the substrate 100 , and may be disposed between the charge storage layer 120 a and the substrate 100 . The charge storage layer 120a is disposed on the other sidewall of the trench 106 . The charge storage layer 118a and the charge storage layer 120a may be arranged in the second direction D2. The second direction D2 may intersect with the first direction D1. The charge storage layer 120a may have a side surface S4 and a side surface S5 opposite to each other. The side surface S4 and the side surface S5 may be arranged in the first direction D1. The charge storage layer 120a may also have a top surface TS2 and a side surface S6 connected between the side surface S4 and the side surface S5. The charge storage layer 120a is, for example, a floating gate. The control gate 126a may cover the top surface TS2, the side surface S4, the side surface S5 and the side surface S6 of the charge storage layer 120a. A dielectric layer 124 may be disposed between the control gate 126a and the charge storage layer 120a. A doped region 128 is located in the substrate 100 on one side of the trench 106 . The doped region 130 is located in the substrate 100 on the other side of the trench 106 .

In addition, the materials, arrangement methods, conductive types, forming methods and functions of the components of the non-volatile memory structure 10 have been described in detail in the above embodiments, and will not be repeated here.

Based on the above embodiments, in the non-volatile memory structure 10 and the manufacturing method thereof, the control gate 126a is disposed on the charge storage layer 118a and covers the side S1 and the side S2 of the charge storage layer 118a, and the dielectric layer 124 is disposed on the charge storage layer 118a. Between the control gate 126a and the charge storage layer 118a. Therefore, the control gate 126a and the charge storage layer 118a can be further coupled at the side S1 and the side S2 of the charge storage layer 118a, thereby increasing the coupling area between the control gate 126a and the charge storage layer 118a. In this way, the non-volatile memory structure 10 can have a higher coupling rate, and thus can effectively improve the electrical performance of the memory element.

In some embodiments, the non-volatile memory structure 10 may also include a charge storage layer 120a. The control gate 126a is disposed on the charge storage layer 120a and covers the side S4 and the side S5 of the charge storage layer 120a, and the dielectric layer 124 is disposed between the control gate 126a and the charge storage layer 120a. Therefore, the control gate 126a and the charge storage layer 120a can also be coupled at the side S4 and the side S5 of the charge storage layer 120a, thereby increasing the coupling area between the control gate 126a and the charge storage layer 120a. In this way, the non-volatile memory structure 10 can have a higher coupling rate, and thus can effectively improve the electrical performance of the memory element.

In addition, since the non-volatile memory structure 10 has the vertical channel and the buried select gate 112a, it can prevent short channel effect and over-erase phenomenon, and can have higher of the memory cell density.

To sum up, in the non-volatile memory structure and the manufacturing method thereof of the above-mentioned embodiments, since the control gate and the charge storage layer can have a larger coupling area, the non-volatile memory structure can have a high coupling rate, and thus can have better electrical performance.

Although the present invention is disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The scope of protection of the present invention should be defined by the appended claims.

Claims (20)

1. A non-volatile memory structure, characterized in that, comprising: a substrate having grooves therein extending along a first direction; a select gate disposed in the trench; a first charge storage layer, disposed on the sidewall of the trench, and having a first side surface and a second side surface opposite to each other, wherein the first side surface and the second side surface are arranged in the first direction ; a control gate disposed on the select gate and the first charge storage layer in the trench and covering the first side and the second side; and A first dielectric layer is disposed between the control gate and the first charge storage layer. 2. The non-volatile memory structure of claim 1, wherein the select gate, the first charge storage layer, the control gate, and the substrate are electrically insulated from each other. 3. The non-volatile memory structure of claim 1, wherein the first charge storage layer comprises a floating gate. 4. The non-volatile memory structure of claim 1, wherein the first charge storage layer further has a third side surface connected between the first side and the second side, and the control gate The pole covers the third side. 5. The non-volatile memory structure of claim 1, further comprising: The second charge storage layer is disposed on the other sidewall of the trench and has a fourth side surface and a fifth side surface opposite to each other, wherein the fourth side surface and the fifth side surface are on the first side Arranged upward, the control gate covers the fourth side surface and the fifth side surface, and the first dielectric layer is disposed between the control gate and the second charge storage layer. 6. The non-volatile memory structure of claim 5, wherein the first charge storage layer and the second charge storage layer are aligned in a second direction, and the second direction intersects the first charge direction. 7. The non-volatile memory structure of claim 5, wherein the second charge storage layer further has a sixth side surface connected between the fourth side and the fifth side, and the control gate The pole covers the sixth side surface. 8. The non-volatile memory structure of claim 1, further comprising: a first doped region in the substrate below the trench; and A second doped region is located in the substrate on one side of the trench. 9. The non-volatile memory structure of claim 8, further comprising: A third doped region is located in the substrate on the other side of the trench. 10. The non-volatile memory structure of claim 1, further comprising: a second dielectric layer disposed between the select gate and the substrate; and A third dielectric layer is disposed between the first charge storage layer and the substrate. 11. A method of fabricating a non-volatile memory structure, comprising: forming trenches in the substrate extending along the first direction; forming a select gate in the trench; A first charge storage layer is formed on the sidewall of the trench, wherein the first charge storage layer has a first side surface and a second side surface opposite to each other, and the first side surface and the second side surface are at each other. arranged in the first direction; forming a control gate on the select gate and the first charge storage layer in the trench, wherein the control gate covers the first side and the second side; and A first dielectric layer is formed between the control gate and the first charge storage layer. 12. The method for fabricating a non-volatile memory structure as claimed in claim 11, wherein the select gate, the first charge storage layer, the control gate and the substrate are electrically insulated from each other. 13. The method of manufacturing a non-volatile memory structure according to claim 11, wherein the first charge storage layer further has a third side surface connected between the first side surface and the second side surface, and the The control gate covers the third side surface. 14. The method for fabricating a non-volatile memory structure as claimed in claim 11, wherein the method for forming the first charge storage layer and the first dielectric layer comprises: Conformally forming a layer of charge storage material in the trench; performing an etch back fabrication process on the charge storage material layer to form charge storage spacers on the sidewalls of the trenches; performing a patterning process on the charge storage spacers to form the first charge storage layer; and After forming the first charge storage layer, the first dielectric layer overlying the first charge storage layer is formed. 15. The method of manufacturing a non-volatile memory structure of claim 11, further comprising: A second charge storage layer is formed on the other sidewall of the trench, wherein the second charge storage layer has a fourth side and a fifth side opposite to each other, and the fourth side and the fifth side are at Arranged in the first direction, the control gate covers the fourth side surface and the fifth side surface, and the first dielectric layer is disposed between the control gate and the second charge storage layer between. 16. The method of manufacturing a non-volatile memory structure according to claim 15, wherein the first charge storage layer and the second charge storage layer are arranged in a second direction, and the second direction intersects the the first direction. 17. The method of manufacturing a non-volatile memory structure according to claim 15, wherein the second charge storage layer further has a sixth side surface connected between the fourth side surface and the fifth side surface, and the second charge storage layer further has a sixth side surface connected between the fourth side surface and the fifth side surface, and the The control gate covers the sixth side surface. 18. The method of fabricating a non-volatile memory structure of claim 11, further comprising: forming a first doped region in the substrate below the trench; and A second doped region is formed in the substrate on one side of the trench. 19. The method of fabricating a non-volatile memory structure of claim 18, further comprising: A third doped region is formed in the substrate on the other side of the trench. 20. The method of manufacturing a non-volatile memory structure of claim 11, further comprising: forming a second dielectric layer between the select gate and the substrate; and A third dielectric layer is formed between the first charge storage layer and the substrate.

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