JP2009267208A - Semiconductor device, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress interference between neighboring cells by reducing capacitor capacitance between neighboring cells. <P>SOLUTION: A semiconductor device includes: a semiconductor substrate 2; a gate insulating film 8 formed on the semiconductor substrate 2; a floating gate electrode 9 formed on the gate insulating film 8; a device isolating groove 3 formed on a surface of the semiconductor substrate 2; and a device isolating and insulating film 5 constituted of a lower portion embedded in the device isolating groove 3 and an upper portion protruded upward from the surface of the semiconductor substrate 2, wherein, inside the device isolating and insulating film 5, a cavity is formed from the upper portion to the lower portion. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device that is suitable for a flash memory device and the like and capable of suppressing interference between adjacent cells when miniaturization progresses, and a manufacturing method thereof.

  For example, a semiconductor device such as a flash memory device employs an element isolation structure by STI (Shallow Trench Isolation) in order to form a fine element isolation structure. In this STI structure, a device isolation region is formed by forming an elongated device isolation groove on the surface of a semiconductor substrate and forming an element isolation insulating film in the device isolation trench. 2. Description of the Related Art In recent years, with the expansion of demand for increasing the capacity of semiconductor devices, transistors and cell structures have been rapidly miniaturized. Among them, the influence between adjacent cells due to the narrowing of the cell wiring pitch is one of the major issues as miniaturization progresses. Therefore, in order to suppress interference between adjacent cells, that is, to reduce the capacitance of the capacitor between adjacent cells, a configuration is known in which elements are insulated by a space, that is, an air gap (for example, Patent Documents). 1).

In the configuration disclosed in Patent Document 1, an air gap is provided in a silicon oxide film embedded in an element isolation trench. In the case of this configuration, the position of the upper end of the air gap is substantially the same as the position of the upper surface of the active region of the silicon substrate. When the above-mentioned Patent Document 1 was filed, miniaturization has not progressed so far, and therefore the interference between adjacent cells could be sufficiently suppressed by the air gap having the above-described configuration. However, when the miniaturization further progresses, the air gap having the above configuration causes a problem that interference between adjacent cells cannot be sufficiently suppressed.
JP 2001-15616 A

  An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can reduce the capacitance of a capacitor between adjacent cells and suppress interference between adjacent cells.

  The semiconductor device of the present invention includes a semiconductor substrate having an element isolation groove formed on a surface thereof, and an element region partitioned by the element isolation groove, a gate insulating film formed on the element region of the semiconductor substrate, An element isolation insulating film comprising a floating gate electrode formed on a gate insulating film, a lower part embedded in the element isolation trench, and an upper part protruding from the surface of the semiconductor substrate, the upper part being the floating gate electrode And an element isolation insulating film having a side surface portion in contact with the side surface of the semiconductor substrate and an upper surface portion whose height from the semiconductor substrate is lower than the height of the upper surface of the floating gate electrode. It is characterized in that a cavity is formed from the lower part to the upper part.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the step of forming a gate insulating film on a surface of a semiconductor substrate, the step of forming a polycrystalline silicon film on the gate insulating film, and the silicon on the polycrystalline silicon film. A step of forming a nitride film; a step of etching the silicon nitride film, the polycrystalline silicon film, the gate insulating film and the semiconductor substrate to form an element isolation groove; and an upper end portion in the element isolation groove. Forming a first element isolation insulating film so as to protrude above the position of the upper surface of the active region of the semiconductor substrate and disposed between the polycrystalline silicon films; and silicon on a side surface of the polycrystalline silicon film Forming a film so as to protrude into the element isolation trench; and etching the first element isolation insulating film using the silicon film as a mask material to form the first element isolation insulating film. Forming a part, in the film formation conditions in which the groove is not filled, it has a feature where the comprising the step of forming a second element isolation insulating film on the first element isolation insulating film.

  ADVANTAGE OF THE INVENTION According to this invention, the capacitor capacity between adjacent cells can be made small and interference between adjacent cells can be suppressed.

(First embodiment)
Hereinafter, a first embodiment in which the present invention is applied to a NAND flash memory device will be described with reference to FIGS. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic and show mainly the characteristic portions according to the present embodiment, and the relationship between the thickness and the planar dimension, the ratio of the thickness of each layer, and the like are different from the actual ones.

  First, the electrical configuration of the NAND flash memory device according to this embodiment will be described. The flash memory device is divided into a memory cell region in which a memory cell array is configured and a peripheral circuit region in which a peripheral circuit for driving the memory cell array is configured. In the present embodiment, since the characteristic structures in both regions are the same part, the following description will mainly focus on the structure in the memory cell region. FIG. 1 is an equivalent circuit diagram of a part of a memory cell array in a memory cell region of a NAND flash memory device.

  In the memory cell array Ar of the NAND flash memory device 1, a NAND cell unit Su including a plurality of (for example, 32) memory cell transistors Trm connected in series between the two select gate transistors Trs1 and Trs2 is a matrix. It is comprised by forming in a shape.

  In the NAND cell unit Su, a plurality of memory cell transistors Trm are formed by sharing adjacent source / drain regions. The memory cell transistors Trm arranged in the X direction (corresponding to the word line direction and the gate width direction) in FIG. 1 are commonly connected by a word line (control gate line) WL.

  Further, the selection gate transistors Trs1 arranged in the X direction in FIG. 1 are commonly connected by a selection gate line SGL1, and the selection gate transistors Trs2 are commonly connected by a selection gate line SGL2. A bit line contact CB (see FIG. 2) is connected to the drain region of the select gate transistor Trs1. The bit line contact CB is connected to a bit line BL extending in the Y direction (corresponding to the gate length direction and the bit line direction) orthogonal to the X direction in FIG. The select gate transistor Trs2 is connected to the source line SL via the source region.

  FIG. 2 is a plan view showing a layout pattern of a part of the memory cell region. As shown in FIG. 2, an element isolation region Sb having an STI (Shallow Trench Isolation) structure is formed in the memory cell region M along the Y direction in FIG. A plurality of element isolation regions Sb are arranged in parallel in the X direction at a predetermined interval, whereby an element region (active region: active area) Sa is formed along the Y direction in FIG. A compartment is formed.

  The word lines WL are formed along the X direction so as to intersect the element region Sa, and a plurality of word lines WL are formed apart from each other in the Y direction. A selection gate line SGL1 for connecting the gate electrode SG of the selection gate transistor is formed along the X direction in FIG. A pair of these select gate lines SGL1 is formed in the Y direction, and bit line contacts CB are formed on the plurality of element regions Sa located between the pair of select gate lines SGL1, respectively.

  A gate electrode MG of the memory cell transistor is formed on the element region Sa intersecting with the word line WL. A gate electrode SG of the selection gate transistor is formed on the element region Sa intersecting with the selection gate line SGL1.

  FIG. 3 schematically shows a cross-sectional view (cross-sectional view along the line AA in FIG. 2) along the word line direction (channel width direction) of each memory cell, and the gate electrode MG of the memory cell transistor is shown. Shown in the center. As shown in FIG. 3, a plurality of element isolation trenches 3 are formed in an upper portion of a silicon substrate (semiconductor substrate) 2, and a plurality of element regions Sa are separated in the X direction shown in FIG. A gate insulating film (tunnel insulating film) 8 made of a silicon oxide film and a polycrystalline silicon film 9 as a floating gate electrode FG are formed on the element region Sa of the silicon substrate 2 partitioned by the element isolation trench 3. Yes. An element isolation insulating film 4 is formed in the element isolation region Sb. This element isolation insulating film 4 is composed of a lower part embedded in the element isolation trench 3 and an upper part protruding upward from the surface of the element region (active region) Sa of the silicon substrate 2. The upper surface of the element isolation insulating film 4 protruding from the silicon substrate 2 is in contact with the side surface of the floating gate electrode FG formed on the element region Sa of the silicon substrate 2 with its side surface adjacent to the element isolation insulating film 4. In addition, the height of the upper surface relative to the silicon substrate 2 is formed to be lower than the height of the upper surface of the floating gate electrode FG.

  The element isolation insulating film 4 includes a silicon oxide film 5 which is a main body buried inside the element isolation trench 3 and between the side surfaces of the floating gate electrode FG, and a high density plasma CVD (on the silicon oxide film 5). It is composed of a silicon oxide film (HDP film) 6 which is a lid formed by the HDP-CVD method. The silicon oxide film 5 is composed of a coating type insulating film (for example, a polysilazane film). Grooves 7 are formed in the silicon oxide film 5 from the upper surface to a position below the surface of the silicon substrate 2 by a predetermined distance. By forming the silicon oxide film 6 so as not to fill the groove 7, a cavity (air gap) 7 is formed in the element isolation insulating film 4. The air gap 7 is disposed between the side surfaces of the element isolation trench 3 and between the side surfaces of the floating gate electrode FG. The upper end portion of the air gap 7 is configured to be positioned between the lower end surface and the upper end surface of the floating gate electrode FG, that is, in the middle portion of the side surface of the floating gate electrode FG.

  On the polycrystalline silicon film 9 and the element isolation insulating film 4, an interpoly insulating film (conductive interlayer insulating film) 10 made of an ONO (Oxide-Nitride-Oxide) film and a polycrystalline silicon film 11 as a control gate electrode CG are provided. Are stacked. A metal silicide film (not shown) is preferably laminated on the polycrystalline silicon film 11 as necessary. Gate insulating film 8 is formed by thermally oxidizing silicon substrate 2, and polycrystalline silicon films 9 and 11 are doped with impurities such as phosphorus.

  Next, a manufacturing method according to the above structure will be described with reference to FIGS. 4A to 12A schematically show a longitudinal sectional view in one stage of the manufacturing process of the memory cell region M, and FIG. 4B to FIG. 12B show a peripheral circuit. The longitudinal cross-sectional view in the one step of the manufacturing process of the area | region P is shown typically. The difference between the structural elements of the memory cell region M and the peripheral circuit region P is only the difference in the gate width, gate length, and film thickness of the gate insulating film (silicon oxide film) 8 of the transistor. The manufacturing method of the structure will be mainly described.

  In the following description, the characteristic portion according to the present embodiment will be mainly described. However, in the present invention, any of the steps described below may be omitted as necessary, and other portions not shown in the figure may be omitted. If there is a process necessary to configure, it may be added.

  First, as shown in FIG. 4, after ion implantation for forming a well and a channel region is performed on the silicon substrate 2, the silicon substrate 2 is thermally oxidized to form a gate for a high voltage transistor on the surface of the silicon substrate 2. An insulating film (silicon oxide film) 12 is formed with a thickness of 35 nm, for example. Subsequently, the silicon oxide film 12 is selectively removed only in the memory cell region (cell array portion) M and the low voltage transistor region, and then a gate insulating film (tunnel insulating film, silicon oxide film) 8 is formed to 8 nm, for example. Different gate insulation film thickness. Thereafter, a polycrystalline silicon film 9 is deposited as a floating gate electrode FG, for example, about 100 nm.

  Next, an element for forming an element isolation region (STI: Shallow Trench Isolation) Sb using the silicon nitride film 13 as a mask material by using a well-known lithography method and reactive ion etching (RIE) method. The separation groove 3 is patterned (see FIG. 5). Thereafter, as shown in FIG. 6, the element isolation trench 3 is filled with a silicon oxide film 5 and buried, and is planarized by a chemical mechanical polishing (CMP) method. The buried silicon oxide film 5 is preferably composed of, for example, a coating type insulating film (polysilazane film). Then, after planarization, the silicon oxide film 5 in the element isolation trench 3 is etched back for the purpose of adjusting the position of the upper end portion of the air gap described later.

  The silicon nitride film 13 used for forming the element isolation trench 3 is left for use as an etch-back mask material for the silicon film 14 and a stopper material for CMP in a later process.

  Next, as shown in FIG. 7, the side surface of the exposed floating gate electrode FG (polycrystalline silicon film 9) is subjected to selective epitaxial growth (SEG), so that the silicon film 14 is formed in the element isolation trench 3, that is, Projecting on the silicon oxide film 5. In this case, the opening dimension (the dimension in the left-right direction in FIG. 8) at the upper end of the air gap, which will be described later, is adjusted by the growth amount of the silicon film 14, that is, the projecting dimension in the lateral direction.

  Subsequently, as shown in FIG. 8, using the grown silicon film 14 as a mask material, a space portion serving as an air gap is etched by the RIE method in the silicon oxide film 5 in the element isolation trench 3 to form a trench portion 7. To do. The depth of the air gap region can be adjusted by the etching amount at this time.

  Next, as shown in FIG. 9, the silicon film 14 protruding as a mask material on the silicon oxide film 5 in the element isolation trench 3 is removed by the RIE method. Thereafter, as shown in FIG. 10, the silicon oxide film 6 is formed between the floating gate electrodes FG (polycrystalline silicon film 9) and between the silicon nitride films 13 under film forming conditions that do not fill the space portion of the high aspect trench 7. Then, a cavity (air gap) 7 is formed. In this case, if the silicon oxide film 6 is composed of a silicon oxide film (HDP oxide film) formed by a high density plasma CVD (HDP-CVD) method, the space portion of the groove portion 7 is not filled.

  Thereafter, as shown in FIG. 11, after the planarized silicon oxide film 6 is planarized by the CMP method, the silicon oxide film 6 in the element isolation trench 3 is formed for the purpose of adjusting the cell coupling ratio. Re-etch bag. As a result, an element isolation insulating film 4 composed of the silicon oxide film 5 as the main body and the silicon oxide film 6 as the lid is formed. Subsequently, the silicon nitride film 13 is removed. Next, as shown in FIG. 12, an interpoly insulating film 10 made of, for example, an ONO film is deposited. Thereafter, as shown in FIG. 3, a polycrystalline silicon film 11 is formed on the interpoly insulating film 10 to form a laminated gate electrode.

  According to the present embodiment having such a configuration, the position of the upper end portion of the air gap 7 provided in the silicon oxide film 5 embedded in the element isolation trench 3 is set to the upper surface of the active region (element region Sa) of the silicon substrate 2. The capacitor capacity between the floating gate electrodes FG can be reduced because it is arranged so as to protrude upward from the position of and located between the intermediate portions of the side surfaces of the polycrystalline silicon film 9 (floating gate electrode FG). Thereby, since the capacitor capacity between adjacent cells can be further reduced as compared with the conventional configuration, the interference between adjacent cells can be suppressed even when the miniaturization is further advanced.

  In the above embodiment, when the air gap 7 is formed in the silicon oxide film 5, the silicon film 14 formed so as to protrude in the element isolation groove 3 inward from the side surface of the polycrystalline silicon film 9 is used as the mask material. Therefore, the structure for forming the air gap 7 can be easily realized. In the above embodiment, the height of the air gap 7, that is, the position of the upper end can be adjusted by the etch back amount of the silicon oxide film 5.

(Second Embodiment)
FIGS. 13 to 15 show a second embodiment of the present invention. The difference from the first embodiment is a method of forming a mask material when forming the groove 7. In addition, the same code | symbol is attached | subjected about the same part as 1st Embodiment. Of the manufacturing steps shown in the first embodiment, the steps from FIG. 4 to FIG. 6 are the same in the second embodiment. In the second embodiment, after executing the process shown in FIG. 6, the process proceeds to the process shown in FIG.

  That is, after the silicon oxide film 5 in the element isolation trench 3 is etched back, a silicon film 15 is deposited by LP-CVD or the like as shown in FIG. Thereafter, as shown in FIG. 14, spacers (side walls) 16 are formed on the side surfaces of the silicon nitride film 13 and the polycrystalline silicon film 9 by etching back the silicon film 15. The spacer 16 protrudes in the element isolation trench 3, that is, on the silicon oxide film 5, and the spacer 16 is used as a mask material at the time of air gap processing. In this case, the opening dimension (the dimension in the left-right direction in FIG. 15) of the upper end of the air gap 7 is determined by the projecting dimension of the spacer 16 into the element isolation groove 3, that is, the deposition amount (film thickness) of the silicon film 15. Can be adjusted.

  Next, as shown in FIG. 15, using the spacer 16 as a mask material, the space portion that becomes the air gap 7 is etched by the RIE method in the silicon oxide film 5 in the element isolation trench 3 to form the trench portion 7. The depth of the air gap region can be adjusted by the etching amount at this time. Subsequently, the spacer 16 protruding as a mask material on the silicon oxide film 5 in the element isolation trench 3 is removed by the RIE method. After this, the process proceeds to the process shown in FIG. 10 of the first embodiment, and the same manufacturing process as that of the first embodiment is performed thereafter.

  The configuration of the second embodiment other than that described above is the same as that of the first embodiment. Therefore, also in the second embodiment, substantially the same operational effects as in the first embodiment can be obtained.

(Other embodiments)
The present invention is not limited to the above embodiments, and can be modified or expanded as follows.

  In each of the embodiments described above, in the step shown in FIG. 11, after the backfilled silicon oxide film 6 is planarized by CMP, the silicon oxide film 6 in the element isolation trench 3 is re-etched and then silicon nitrided. Instead of this, the back-filled silicon oxide film 6 is planarized by the CMP method, the silicon nitride film 13 is removed, and then the silicon in the element isolation trench 3 is removed. The oxide film 6 may be re-etched.

  In each of the above embodiments, the present invention is applied to the NAND flash memory device 1, but may be applied to other NOR flash memory devices.

FIG. 3 is an electrical configuration diagram of a part of the memory cell region showing the first embodiment of the present invention; A plan view schematically showing a layout pattern of a part of a memory cell region The figure which shows typically the longitudinal cross section in alignment with the AA in FIG. Longitudinal sectional view schematically showing one stage of the manufacturing process (Part 1) Longitudinal sectional view schematically showing one stage of the manufacturing process (Part 2) Longitudinal sectional view schematically showing one stage of the manufacturing process (Part 3) Vertical sectional view schematically showing one stage of the manufacturing process (No. 4) Vertical sectional view schematically showing one stage of the manufacturing process (No. 5) Vertical sectional view schematically showing one stage of the manufacturing process (No. 6) Vertical sectional view schematically showing one stage of the manufacturing process (No. 7) Longitudinal sectional view schematically showing one stage of the manufacturing process (No. 8) Longitudinal sectional view schematically showing one stage of the manufacturing process (No. 9) The longitudinal cross-sectional view which shows the 2nd Embodiment of this invention and shows typically one step of a manufacturing process (the 10) Longitudinal sectional view schematically showing one stage of the manufacturing process (No. 11) Longitudinal sectional view schematically showing one stage of the manufacturing process (No. 12)

Explanation of symbols

  In the drawings, 1 is a NAND flash memory device (semiconductor device), 2 is a silicon substrate (semiconductor substrate), 3 is an element isolation trench, 4 is an element isolation insulating film, 5 is a silicon oxide film, 6 is a silicon oxide film, 7 Is a cavity (groove), 8 is a gate insulating film, 9 is a polycrystalline silicon film, 10 is an interpoly insulating film, 11 is a polycrystalline silicon film, 14 is a silicon film, and 15 is a silicon film.

Claims (5)

A semiconductor substrate in which an element isolation groove is formed on the surface, and an element region is partitioned by the element isolation groove;
A gate insulating film formed on the element region of the semiconductor substrate;
A floating gate electrode formed on the gate insulating film;
An element isolation insulating film comprising a lower part embedded in the element isolation trench and an upper part protruding from the surface of the semiconductor substrate, wherein the upper part is formed from a side surface contacting the side surface of the floating gate electrode and from the semiconductor substrate And an element isolation insulating film having an upper surface portion whose height is lower than the height of the upper surface of the floating gate electrode,
A semiconductor device, wherein a cavity is formed in the element isolation insulating film from the lower part to the upper part.   The element isolation insulating film includes a main body portion having a groove portion and a lid portion formed on the main body portion, and the cavity portion is formed by covering the groove portion with the lid portion. The semiconductor device according to claim 1.   3. The semiconductor device according to claim 2, further comprising an interelectrode insulating film formed on the lid and the floating gate electrode, and a control gate electrode formed on the interelectrode insulating film. Forming a gate insulating film on the surface of the semiconductor substrate;
Forming a polycrystalline silicon film on the gate insulating film;
Forming a silicon nitride film on the polycrystalline silicon film;
Etching the silicon nitride film, the polycrystalline silicon film, the gate insulating film, and the semiconductor substrate to form an element isolation trench;
Forming a first element isolation insulating film in the element isolation trench so that an upper end portion projects above the position of the upper surface of the active region of the semiconductor substrate and is disposed between the polycrystalline silicon films; ,
Forming a silicon film on the side surface of the polycrystalline silicon film so as to protrude into the element isolation trench;
Etching the first element isolation insulating film using the silicon film as a mask material to form a groove in the first element isolation insulating film;
And a step of forming a second element isolation insulating film on the first element isolation insulating film under film forming conditions that do not fill the groove. Forming a gate insulating film on the surface of the semiconductor substrate;
Forming a polycrystalline silicon film on the gate insulating film;
Forming a silicon nitride film on the polycrystalline silicon film;
Etching the silicon nitride film, the polycrystalline silicon film, the gate insulating film, and the semiconductor substrate to form an element isolation trench;
Forming a first element isolation insulating film in the element isolation trench so that an upper end portion projects above the position of the upper surface of the active region of the semiconductor substrate and is disposed between the polycrystalline silicon films; ,
Forming a silicon film on the side surfaces of the silicon nitride film and the polycrystalline silicon film so as to protrude into the element isolation trench;
Etching the first element isolation insulating film using the silicon film as a mask material to form a groove in the first element isolation insulating film;
And a step of forming a second element isolation insulating film on the first element isolation insulating film under film formation conditions that do not fill the groove.

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