CN111312135B - Source driver and operation method thereof - Google Patents

Abstract

A source driver and an operating method thereof. In the source driver, the clock data recovery circuit is used for receiving an original data signal from an external device and generating a clock signal and a first data signal according to the original data signal. The digital circuit receives the clock signal and the first data signal and generates a cut-off power signal according to the first data signal. The signal detection circuit is used for receiving a control signal from an external device and generating a starting power supply signal according to the control signal. The power control circuit cuts off the power supply signal to power off the clock data recovery circuit, and the power control circuit cuts off the power supply signal to power on the clock data recovery circuit.

Description

Source driver and method of operation

Technical field

The present invention relates to a display device, and in particular to a source driver and an operating method thereof.

Background technique

With the advancement of electronic technology, consumer electronic products have become essential tools in people's lives. In order to provide a good human-machine interface, it has become a trend to configure high-quality display devices on consumer electronic products. Reducing the power consumption of the display device during the non-display time interval will be a task for those skilled in the art.

Contents of the invention

The present invention provides a source driver and an operating method thereof, which can effectively reduce the power consumption of the source driver in non-display time intervals.

The source driver of the present invention includes a clock data recovery (CDR) circuit, a digital circuit, a signal detection circuit and a power control circuit. The clock data recovery circuit is used to receive an original data signal from an external device and generate a clock signal and a first data signal based on the original data signal. The digital circuit is coupled to the clock data recovery circuit to receive the clock signal and the first data signal, and generates a power-off signal according to the first data signal. The signal detection circuit is used to receive a control signal from an external device and generate a starting power signal according to the control signal. The power control circuit is coupled to the digital circuit to receive the power-off signal, and is coupled to the signal detection circuit to receive the start-up power signal, wherein the power control circuit turns off the clock data recovery circuit according to the power-off signal, and the power control circuit turns off the power according to the start-up power signal. The signal restores power to the clock data recovery circuit.

The operating method of the present invention includes: the clock data recovery circuit generates a clock signal and a data signal based on the original data signal; the digital circuit generates a power-off signal based on the first data signal; and the signal detection circuit generates a start-up power signal based on the control signal; The power control circuit de-energizes the clock data recovery circuit according to the power-off signal; the power control circuit de-energizes the clock data recovery circuit according to the start-up power signal.

Based on the above, the source driver according to the embodiments of the present invention can use the power control circuit to cut off the power supply signal to cause at least one or all of the clock data recovery circuit, the digital circuit and the driving circuit to be powered off. Furthermore, the power control circuit is used to restore power to at least one or all of the clock data recovery circuit, the digital circuit and the driving circuit according to the start power signal. In this way, the source driver of the present invention can further reduce the overall power consumption of the source driver when operating in the non-display time interval.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, embodiments are given below and described in detail with reference to the accompanying drawings.

Description of the drawings

FIG. 1 is a circuit block diagram of a source driver according to an embodiment of the present invention.

FIG. 2 is a schematic diagram illustrating the signal timing of the source driver shown in FIG. 1 according to an embodiment of the present invention.

FIG. 3 is a flowchart of an operating method of a source driver according to an embodiment of the present invention.

Detailed ways

The word "coupling (or connection)" used throughout the specification (including claims) of this case may refer to any direct or indirect connection means. For example, if a first device is described as coupled (or connected) to a second device, it should be understood that the first device can be directly connected to the second device, or the first device can be connected through other devices or channels. A connection means is indirectly connected to the second device. In addition, wherever possible, components/components/steps with the same reference numbers are used in the drawings and embodiments to represent the same or similar parts. Components/components/steps using the same numbers or using the same terms in different embodiments can refer to the relevant descriptions of each other.

FIG. 1 is a circuit block diagram of a source driver 100 according to an embodiment of the present invention. The source driver 100 receives the original data signal TX and the control signal CS from the external device 160, and drives the display panel 170 to display an image according to receiving the original data signal TX and the control signal CS. Specifically, the external device 160 of this embodiment may include a timing controller (Timing Controller, TCON). In this embodiment, the external device 160 can generate an original data signal TX and a control signal CS to the source driver 100 , where the original data signal TX includes the display data that the display panel 170 needs to display, and the control signal CS It is used to indicate the valid data period and invalid data (such as training pattern, training pattern) period in the original data signal TX. Generally speaking, an invalid data period is scheduled after a vertical blanking period (before the transmission period of valid frame data). Therefore, the control signal CS carries the phase (time point) information that "the vertical blanking period has ended."

Referring to FIG. 1 , the source driver 100 includes a clock data recovery circuit 110 , a digital circuit 120 , a signal detection circuit 130 , a power control circuit 140 and a driving circuit 150 . Among them, a power on/off reset (POFR) circuit is configured in the power control circuit 140 . The clock data recovery circuit 110 can be used to parse out the clock signal CLK and data signal DS1 mounted in the original data signal TX. The data signal DS1 may include pixel data, a vertical blanking start signal VBK, a line latch signal and other control signals, but this embodiment is not limited thereto. Generally speaking, the vertical blanking start signal VBK can indicate/define a starting phase (starting time point) of a vertical blanking period.

The digital circuit 120 of this embodiment may be, for example, a controller or a data processor, but the invention is not limited thereto. The digital circuit 120 is coupled to the clock data recovery circuit 110 to receive the clock signal CLK and the data signal DS1. The digital circuit 120 may process the data signal DS1 to generate a processed data signal DS2, such as pixel data. In addition, the digital circuit 120 can also generate the power cutoff signal CPS according to the data signal DS1. For example, in this embodiment, the digital circuit 120 can detect the vertical blanking start signal VBK in the data signal DS1, and generate the power-off signal CPS to the power control circuit 140 according to the vertical blanking start signal VBK. . In other embodiments, the digital circuit 120 may detect other information in the data signal DS1 and generate the power-off signal CPS based on the other information.

The driving circuit 150 is coupled to the digital circuit 120 to receive the clock signal CLK. The driving circuit 150 is also coupled to the digital circuit 120 to receive the data signal DS2. The driving circuit 150 can generate the source driving signals S1˜Sn according to the clock signal CLK and the data signal DS2, and the driving circuit 150 can use the source driving signals S1˜Sn to drive the display panel 170 . This embodiment does not limit the implementation of the driving circuit 150. For example, in some embodiments, the driving circuit 150 may include a shift register (Shift Register), a data buffer (DataRegister), a level shifter (Level Shifter), and a digital/analog converter that are well known to those skilled in the art. (Digital-to-AnalogConverter, DAC) and output buffer (Output Buffer), the relevant operations in each component will not be described in detail here.

On the other hand, the signal detection circuit 130 is coupled to the external device 160 to receive the control signal CS. The control signal CS carries the phase (time point) information of “the vertical blanking period has ended”, so the signal detection circuit 130 can generate the start power signal SPS according to the control signal CS. For example, in some application scenarios, the control signal CS having a first logic level (eg, a high level) may indicate a valid data period in the original data signal TX, while having a second logic level (eg, a low level) may indicate a valid data period in the original data signal TX. bit) of the control signal CS may indicate periods of invalid data (eg, training patterns) in the original data signal TX. Based on this, the signal detection circuit 130 can detect the falling edge of the control signal CS, and generate the startup power signal SPS to the power-on/power-off reset circuit of the power control circuit 140 according to the falling edge of the control signal CS. In other application scenarios, the control signal CS with a low level may indicate valid data periods in the original data signal TX, and the control signal CS with a high level may indicate invalid data in the original data signal TX (eg, training style) period. Based on this, the signal detection circuit 130 can detect the rising edge of the control signal CS, and generate the startup power signal SPS to the power-on/power-off reset circuit of the power control circuit 140 according to the rising edge of the control signal CS.

The power-on/power-off reset circuit of the power control circuit 140 is coupled to the digital circuit 120 to receive the power-off signal CPS. The power-on/power-off reset circuit of the power control circuit 140 is coupled to the signal detection circuit 130 to receive the startup power signal SPS. The power-on/power-off reset circuit of the power control circuit 140 can control the power supply of the clock data recovery circuit 110, the digital circuit 120, and/or the driving circuit 150. The power control circuit 140 can provide power control signals PCS1, PCS2 and PCS3 to the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150 according to the power off signal CPS and the power on signal SPS respectively to control the clock data recovery circuit 110 and the digital circuit 150. The circuit 120 and the driving circuit 150 operate in a power-off state or a power-on restoration state. For example, the power control circuit 140 can power off the clock data recovery circuit 110 during the non-display time interval, and power up the clock data recovery circuit 110 during the display time interval.

For details of the operation of the source driver 100, please refer to both FIG. 1 and FIG. 2. FIG. 2 is a signal timing diagram illustrating the source driver 100 shown in FIG. 1 according to an embodiment of the present invention. According to design requirements, the non-display time interval TND includes the vertical blanking period and/or other times. The embodiment shown in FIG. 2 takes the vertical blanking period as an example of the non-display time interval TND. Specifically, in this embodiment, the digital circuit 120 can detect the vertical blanking start signal VBK of the data signal DS1 in the vertical blanking time interval TBK. The vertical blanking start signal VBK means the start of the vertical blanking period (non-display time interval TND). Therefore, the digital circuit 120 can set the power-off signal CPS to an enabled (eg, high voltage level) state during the vertical blanking time interval TBK according to the vertical blanking start signal VBK. At the same time, the signal detection circuit 130 may receive the control signal CS. Because the control signal CS still remains at a high level during the vertical blanking period, the signal detection circuit 130 can keep the startup power signal SPS in a disabled state (eg, a low voltage level).

When the power-off signal CPS is in an enabled state, the power-on/power-off reset circuit of the power control circuit 140 can know that a power-off reset event occurs. Therefore, the power-on/power-off reset circuit of the power control circuit 140 can provide power control signals PCS1˜PCS3 in a disabled (eg, low voltage level) state to the corresponding clock data recovery circuit 110 according to the power-off signal CPS. , the digital circuit 120 and the driving circuit 150, so that the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150 are powered off.

On the other hand, in the embodiment shown in FIG. 2 , the control signal CS with a high level may indicate a valid data period in the original data signal TX, and the control signal CS with a low level may indicate that during the original data signal TX Invalid data in (e.g. training style) period. The falling edge of the control signal CS means the end of the vertical blanking period (non-display time interval TND). Therefore, the signal detection circuit 130 can detect the falling edge of the control signal CS, and according to the falling edge of the control signal CS, generate a startup power supply with an enabled (eg, high voltage level) state at the end time TEND of the non-display time interval TND. The signal SPS is provided to the power-on/power-off reset circuit of the power control circuit 140 .

When the startup power signal SPS is in an enabled state, the power-on/power-off reset circuit of the power control circuit 140 can know that a power-on reset event occurs. Therefore, the power-on/power-off reset circuit of the power control circuit 140 can provide power control signals PCS1˜PCS3 in an enabled (eg, high voltage level) state to the corresponding clock data recovery circuit 110 according to the startup power signal SPS. , the digital circuit 120 and the driving circuit 150, so that the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150 are restored.

In other words, in this embodiment, the source driver 100 can determine the start and end of the vertical blanking period (non-display time interval TND) through the digital circuit 120 and the signal detection circuit 130 . When the digital circuit 120 detects the beginning of the vertical blanking period (non-display time interval TND) according to the vertical blanking time interval TBK, the digital circuit 120 can trigger the power on/off of the power control circuit 140 by cutting off the power signal CPS. Power-off reset event that resets the circuit. Therefore, the power-on/power-off reset circuit of the power control circuit 140 can power off the clock data recovery circuit 110 , the digital circuit 120 and the driving circuit 150 to reduce the power consumption of the source driver 100 . When the signal detection circuit 130 detects the end of the vertical blanking period (non-display time interval TND) based on the falling edge of the control signal CS, the signal detection circuit 130 can trigger the power on/off of the power control circuit 140 by activating the power signal SPS. Power-on reset event for power-off reset circuit. Therefore, the power-on/power-off reset circuit of the power control circuit 140 can perform power restoration operations on the clock data recovery circuit 110, the digital circuit 120, and the drive circuit 150, thereby causing the clock data recovery circuit 110, the digital circuit 120, and the drive circuit 150 to The relevant circuit operations are restarted at the end time TEND.

Next, when the source driver 100 operates in the display time interval TD, since the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150 all operate in the normal operating state according to the corresponding power control signals PCS1˜PCS3, at this time, The driving circuit 150 can normally generate the source driving signals S1˜Sn according to the clock signal CLK and the data signal DS2. Using the source driving signals S1˜Sn, the driving circuit 150 can drive the display panel 170 so that the display panel 170 displays a picture in the display time interval TD.

It is worth mentioning that in this embodiment, those skilled in the art can decide which internal components of the source driver 100 are to be powered off or restored according to the design requirements of the source driver 100 . For example, when the source driver 100 operates in the non-display time interval TND (such as the vertical blanking period), the power control circuit 140 of this embodiment can enable the clock data recovery circuit 110 and the digital circuit 120 according to the cut-off power signal CPS. And at least one or all of the driving circuits 150 are powered off. In contrast, when the non-display time interval TND ends, the power control circuit 140 can re-power at least one or all of the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150 according to the start power signal SPS.

According to the above, it can be known that the power control circuit 140 of the source driver 100 in this embodiment can cut off the power of the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150 in the non-display time interval TND according to the power cut signal CPS, so as to The power consumption of the source driver 100 is reduced. On the other hand, when the non-display time interval TND ends, the power control circuit 140 of the source driver 100 can restore the power of the clock data recovery circuit 110, the digital circuit 120 and the driving circuit 150 according to the startup power signal SPS, causing the clock data to be restored. The circuit 110, the digital circuit 120 and the driving circuit 150 can restart related circuit operations after the end time point TEND of the non-display time interval TND.

FIG. 3 is a flowchart of an operating method of the source driver 100 according to an embodiment of the present invention. Please refer to FIG. 1 and FIG. 3 simultaneously. In step S310, the source driver 100 can generate the clock signal CLK and the data signal DS1 according to the original data signal TX through the clock data recovery circuit 110. In step S320 , the source driver 100 may generate the power-off signal CPS according to the data signal DS1 through the digital circuit 120 . In step S330, the source driver 100 may power off the clock data recovery circuit 110 through the power control circuit 140 according to the power cutoff signal CPS.

Next, in step S340, the source driver 100 can generate the start power signal SPS according to the control signal CS through the signal detection circuit 130. In step S350, the source driver 100 can restore power to the clock data recovery circuit 110 according to the startup power signal SPS through the power control circuit 140.

The implementation details of each step are described in detail in the foregoing embodiments and implementation modes, and will not be described in detail below.

To sum up, the source driver according to the embodiments of the present invention can use the power control circuit to power off at least one or all of the clock data recovery circuit, the digital circuit and the driving circuit according to cutting off the power signal. Furthermore, the power control circuit is used to restore power to at least one or all of the clock data recovery circuit, the digital circuit and the driving circuit according to the start power signal. In this way, the source driver according to the embodiments of the present invention can reduce the overall power consumption of the source driver during the non-display time interval, thereby achieving a power saving effect.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Any person skilled in the art can make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention is The scope of protection shall be determined by the appended claims.

Claims (8)

1. A source driver, comprising: A clock data recovery circuit for receiving an original data signal from an external device and generating a clock signal and a first data signal based on the original data signal; a digital circuit coupled to the clock data recovery circuit to receive the clock signal and the first data signal, and generate a power-off signal according to the first data signal; A signal detection circuit to receive a control signal from the external device and generate a startup power signal based on the control signal; and A power control circuit is coupled to the digital circuit to receive the power-off signal, and is coupled to the signal detection circuit to receive the start-up power signal, wherein the power control circuit enables the power-off signal according to the power-off signal. The clock data recovery circuit is powered off, and the power control circuit restores power to the clock data recovery circuit according to the startup power signal. 2. The source driver of claim 1, wherein the power control circuit powers off the clock data recovery circuit during non-display time intervals. 3. The source driver of claim 2, wherein the non-display time interval includes a vertical blanking period. 4. The source driver of claim 1, wherein the digital circuit detects a vertical blanking start signal in the first data signal, and generates the power-off function based on the vertical blanking start signal. signal to the power control circuit. 5. The source driver of claim 1, wherein the signal detection circuit detects a falling edge of the control signal, and generates the startup power signal to the power control according to the falling edge of the control signal. circuit. 6. The source driver of claim 1, wherein the power control circuit further powers off the digital circuit in response to the power-off signal, and the power control circuit further powers the digital circuit in response to the start-up power signal. Digital circuit power is restored. 7. The source driver of claim 1, wherein the digital circuit outputs a second data signal according to the first data signal, the source driver further comprising: A driving circuit coupled to the digital circuit to receive the clock signal, and coupled to the digital circuit to receive the second data signal, wherein the driving circuit is used to drive according to the second data signal display panel; The power control circuit also powers off the driving circuit according to the power-off signal, and the power control circuit also restores power to the driving circuit according to the start-up power signal. 8. The source driver of claim 1, wherein the power control circuit includes a power-on/power-off reset circuit.