CN111312135A - Source driver and operating method thereof - Google Patents

Abstract

A source driver and a method of operating the same. In the source driver, the clock data recovery circuit is used for receiving an original data signal from an external device and generating a clock signal and a first data signal according to the original data signal. The digital circuit receives a clock signal and a first data signal and generates a power-off signal according to the first data signal. The signal detection circuit is used for receiving a control signal from an external device and generating a starting power supply signal according to the control signal. The power control circuit powers off the clock data recovery circuit according to the power-off signal, and powers back the clock data recovery circuit according to the power-on signal.

Description

Source driver and method of operation thereof

technical field

The present invention relates to a display device, and more particularly, to a source driver and an operating method thereof.

Background technique

With the advancement of electronic technology, consumer electronic products have become an essential tool in people's lives. In order to provide a good human-machine interface, it has become a trend to configure high-quality display devices on consumer electronic products. Reducing the power consumption of the display device during the non-display time period will be the subject of those skilled in the art.

SUMMARY OF THE INVENTION

The present invention provides a source driver and an operation method thereof, which can effectively reduce the power consumption of the source driver in the non-display time interval.

The source driver of the present invention includes a clock data recovery (CDR) circuit, a digital circuit, a signal detection circuit and a power control circuit. The clock data recovery circuit is used for receiving the original data signal from the external device, and generating the clock signal and the first data signal according to the original data signal. The digital circuit is coupled to the clock data recovery circuit to receive the clock signal and the first data signal, and generate a power-off signal according to the first data signal. The signal detection circuit is used for receiving a control signal from an external device, and generating a start-up power signal according to the control signal. The power control circuit is coupled to the digital circuit to receive a power-off signal, and is coupled to the signal detection circuit to receive a power-on signal, wherein the power control circuit powers off the clock data recovery circuit according to the power-off signal, and the power control circuit starts the power according to The signal powers up the clock data recovery circuit.

The operation method of the present invention includes: generating a clock signal and a data signal by a clock data recovery circuit according to an original data signal; generating a power-off signal by a digital circuit according to the first data signal; generating a power-on signal by a signal detection circuit according to a control signal; The clock data recovery circuit is powered off by the power control circuit according to the cut-off power signal; the clock data recovery circuit is powered on by the power control circuit according to the start power signal.

Based on the above, the source driver according to the embodiments of the present invention can use the power control circuit to power off at least one or all of the clock data recovery circuit, the digital circuit and the driving circuit according to the power off signal. In addition, at least one or all of the clock data recovery circuit, the digital circuit and the driving circuit are recovered by using the power control circuit according to the start-up power signal. In this way, the source driver of the present invention can further reduce the overall power consumption of the source driver when operating in the non-display time interval.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

Description of drawings

FIG. 1 is a circuit block diagram of a source driver according to an embodiment of the present invention.

FIG. 2 is a schematic diagram illustrating signal timing of the source driver shown in FIG. 1 according to an embodiment of the present invention.

FIG. 3 is a flowchart of an operating method of a source driver according to an embodiment of the present invention.

Detailed ways

The term "coupled (or connected)" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes that a first device is coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be connected to the second device through other devices or indirectly connected to the second device by a connecting means. Also, where possible, components/components/steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Components/components/steps that use the same reference numerals or use the same terminology in different embodiments may refer to the relevant descriptions of each other.

FIG. 1 is a schematic block diagram of a circuit of a source driver 100 according to an embodiment of the present invention. The source driver 100 receives the original data signal TX and the control signal CS from the external device 160, and drives the display panel 170 to display an image according to the received original data signal TX and the control signal CS. Specifically, the external device 160 in this embodiment may include a timing controller (Timing Controller, TCON). In this embodiment, the external device 160 can generate the original data signal TX and the control signal CS to the source driver 100, wherein the original data signal TX includes the display data to be displayed by the display panel 170, and the control signal CS It is used to indicate the valid data period and the invalid data period (eg, training pattern) in the original data signal TX. Generally speaking, an invalid data period is arranged after a vertical blanking period (before the transmission period of valid frame data). Therefore, the control signal CS carries the phase (time point) information of "the vertical blanking period has ended".

Referring to FIG. 1 , the source driver 100 includes a clock data recovery circuit 110 , a digital circuit 120 , a signal detection circuit 130 , a power control circuit 140 and a driving circuit 150 . The power control circuit 140 is configured with a power on/off reset (POFR) circuit. The clock data recovery circuit 110 can be used to parse out the clock signal CLK and the data signal DS1 carried in the original data signal TX. The data signal DS1 may include pixel data, a vertical blanking start signal VBK, a line latch signal and other control signals, but this embodiment is not limited thereto. Generally speaking, the vertical blanking start signal VBK may indicate/define the starting phase (starting time point) of a vertical blanking period.

The digital circuit 120 in this embodiment may be, for example, a controller or a data processor, but the present invention is not limited thereto. The digital circuit 120 is coupled to the clock data recovery circuit 110 to receive the clock signal CLK and the data signal DS1. The digital circuit 120 may process the data signal DS1 to generate a processed data signal DS2, eg, pixel data. In addition, the digital circuit 120 can also generate a power-off signal CPS according to the data signal DS1. For example, in this embodiment, the digital circuit 120 can detect the vertical blanking start signal VBK in the data signal DS1, and generate the power-off signal CPS to the power control circuit 140 according to the vertical blanking start signal VBK . In other embodiments, the digital circuit 120 may detect other information in the data signal DS1 and generate the power-off signal CPS according to the other information.

The driving circuit 150 is coupled to the clock data recovery circuit 110 to receive the clock signal CLK. The driving circuit 150 is also coupled to the digital circuit 120 to receive the data signal DS2. The driving circuit 150 can generate the source driving signals S1 ˜Sn according to the clock signal CLK and the data signal DS2 , and the driving circuit 150 can use the source driving signals S1 ˜Sn to drive the display panel 170 . This embodiment does not limit the implementation of the driving circuit 150 . For example, in some embodiments, the driving circuit 150 may include a shift register (Shift Register), a data register (Data Register), a level shifter (Level Shifter), a digital/analog A converter (Digital-to-AnalogConverter, DAC) and an output buffer (Output Buffer), the related operations in each component will not be repeated here.

On the other hand, the signal detection circuit 130 is coupled to the external device 160 to receive the control signal CS. The control signal CS carries the phase (time point) information of "the vertical blanking period has ended", so the signal detection circuit 130 can generate the start power signal SPS according to the control signal CS. For example, in some application scenarios, the control signal CS with a first logic level (eg, high level) may indicate a valid data period in the original data signal TX, while the control signal CS with a second logic level (eg, low level) bit) of the control signal CS may indicate periods of invalid data (eg, training patterns) in the original data signal TX. Based on this, the signal detection circuit 130 can detect the falling edge of the control signal CS, and generate the start-up power signal SPS to the power-on/power-off reset circuit of the power control circuit 140 according to the falling edge of the control signal CS. In other application scenarios, the control signal CS with a low level may indicate valid data periods in the original data signal TX, while the control signal CS with a high level may indicate invalid data in the original data signal TX (eg training style). Based on this, the signal detection circuit 130 can detect the rising edge of the control signal CS, and generate the start-up power signal SPS to the power-on/power-off reset circuit of the power control circuit 140 according to the rising edge of the control signal CS.

The power-on/power-off reset circuit of the power control circuit 140 is coupled to the digital circuit 120 to receive the power-off signal CPS. The power-on/power-off reset circuit of the power control circuit 140 is coupled to the signal detection circuit 130 to receive the start-up power signal SPS. The power-on/power-off reset circuit of the power control circuit 140 can control the power supply of the clock data recovery circuit 110 , the digital circuit 120 and/or the driving circuit 150 . The power control circuit 140 can respectively provide the power control signals PCS1 , PCS2 and PCS3 to the clock data recovery circuit 110 , the digital circuit 120 and the driving circuit 150 according to the power-off signal CPS and the power-on signal SPS to control the clock data recovery circuit 110 , the digital The circuit 120 and the driving circuit 150 operate in a power-off state or a power-recovery state. For example, the power control circuit 140 can power off the clock data recovery circuit 110 during the non-display time period, and power on the clock data recovery circuit 110 during the display time period.

For details of the operation of the source driver 100 , please refer to FIG. 1 and FIG. 2 at the same time. FIG. 2 is a schematic diagram illustrating signal timing of the source driver 100 shown in FIG. 1 according to an embodiment of the present invention. According to design requirements, the non-display time interval TND includes a vertical blanking period and/or other times. The embodiment shown in FIG. 2 takes the vertical blanking period as an example of the non-display time interval TND. In detail, in this embodiment, the digital circuit 120 can detect the vertical blanking start signal VBK of the data signal DS1 in the vertical blanking time interval TBK. The vertical blanking start signal VBK means the start of the vertical blanking period (non-display time period TND). Therefore, the digital circuit 120 can set the power-off signal CPS to an enabled (eg, high voltage level) state during the vertical blanking time interval TBK according to the vertical blanking start signal VBK. At the same time, the signal detection circuit 130 may receive the control signal CS. Because the control signal CS is still kept at a high level during the vertical blanking period, the signal detection circuit 130 can keep the start-up power signal SPS in a disabled (eg, a low voltage level) state.

When the power-off signal CPS is in an enabled state, the power-on/power-off reset circuit of the power control circuit 140 can know that a power-off reset event has occurred. Therefore, the power-on/power-off reset circuit of the power control circuit 140 can provide the power control signals PCS1 ˜ PCS3 having a disabled (eg, low voltage level) state to the corresponding clock data recovery circuit 110 according to the power-off signal CPS , the digital circuit 120 and the driving circuit 150 , so that the clock data recovery circuit 110 , the digital circuit 120 and the driving circuit 150 are powered off.

On the other hand, in the embodiment shown in FIG. 2 , the control signal CS with a high level may indicate a valid data period in the original data signal TX, and the control signal CS with a low level may indicate a valid data period in the original data signal TX Invalid data (e.g. training style) in . The falling edge of the control signal CS means the end of the vertical blanking period (non-display time period TND). Therefore, the signal detection circuit 130 can detect the falling edge of the control signal CS, and according to the falling edge of the control signal CS, at the end time TEND of the non-display time period TND, a startup power supply having an enabled (eg, high voltage level) state can be generated The signal SPS is given to the power-on/power-off reset circuit of the power control circuit 140 .

When the start-up power signal SPS is in an enabled state, the power-on/power-off reset circuit of the power control circuit 140 can know that a power-on reset event has occurred. Therefore, the power-on/power-off reset circuit of the power control circuit 140 can provide the power control signals PCS1 - PCS3 having an enabled (eg, high voltage level) state to the corresponding clock data recovery circuit 110 according to the start-up power signal SPS , the digital circuit 120 and the driving circuit 150 , so that the clock data recovery circuit 110 , the digital circuit 120 and the driving circuit 150 are recovered.

In other words, in this embodiment, the source driver 100 can determine the start and end of the vertical blanking period (non-display time period TND) through the digital circuit 120 and the signal detection circuit 130 . When the digital circuit 120 detects the start of the vertical blanking period (non-display time period TND) according to the vertical blanking time interval TBK, the digital circuit 120 can trigger the power-on/power-off of the power control circuit 140 by cutting off the power signal CPS A power-off reset event that resets the circuit. Therefore, the power-on/power-off reset circuit of the power control circuit 140 can power off the clock data recovery circuit 110 , the digital circuit 120 and the driving circuit 150 to reduce the power consumption of the source driver 100 . When the signal detection circuit 130 detects the end of the vertical blanking period (non-display time interval TND) according to the falling edge of the control signal CS, the signal detection circuit 130 can trigger the power-on/off of the power control circuit 140 by enabling the power signal SPS A power-on reset event for the power-off reset circuit. Therefore, the power-on/power-off reset circuit of the power control circuit 140 can restore the clock data recovery circuit 110 , the digital circuit 120 and the driving circuit 150 , thereby enabling the clock data recovery circuit 110 , the digital circuit 120 and the driving circuit 150 to recover power. The related circuit operation is restarted at the end time TEND.

Next, when the source driver 100 operates in the display time interval TD, since the clock data recovery circuit 110 , the digital circuit 120 and the driving circuit 150 all operate in the normal working state according to the corresponding power control signals PCS1 - PCS3 , therefore The driving circuit 150 can normally generate the source driving signals S1 ˜Sn according to the clock signal CLK and the data signal DS2 . Using the source driving signals S1 ˜Sn, the driving circuit 150 can drive the display panel 170 , so that the display panel 170 displays a picture in the display time interval TD.

It is worth mentioning that, in this embodiment, those skilled in the art can determine which internal components of the source driver 100 are powered off or reset according to the design requirements of the source driver 100 . For example, when the source driver 100 operates in the non-display time period TND (eg, the vertical blanking period), the power control circuit 140 of this embodiment can restore the clock data to the circuit 110 and the digital circuit 120 according to the power-off signal CPS and at least one or all of the driving circuits 150 are powered off. On the other hand, when the non-display time period TND ends, the power control circuit 140 can make at least one or all of the clock data recovery circuit 110 , the digital circuit 120 and the driving circuit 150 be powered up again according to the start-up power signal SPS.

According to the above, the power control circuit 140 of the source driver 100 in this embodiment can cut off the power of the clock data recovery circuit 110 , the digital circuit 120 and the driving circuit 150 in the non-display time interval TND according to the power cut signal CPS, so as to The power consumption of the source driver 100 is reduced. On the other hand, when the non-display time period TND ends, the power control circuit 140 of the source driver 100 can restore the power of the clock data recovery circuit 110 , the digital circuit 120 and the driving circuit 150 according to the start power signal SPS, so that the clock data is recovered The circuit 110 , the digital circuit 120 and the driving circuit 150 can start the related circuit operations again after the end time point TEND of the non-display time interval TND.

FIG. 3 is a flowchart of an operating method of the source driver 100 according to an embodiment of the present invention. 1 and FIG. 3 at the same time, in step S310, the source driver 100 can generate the clock signal CLK and the data signal DS1 through the clock data recovery circuit 110 according to the original data signal TX. In step S320, the source driver 100 can generate the power-off signal CPS according to the data signal DS1 through the digital circuit 120. In step S330 , the source driver 100 may power off the clock data recovery circuit 110 through the power control circuit 140 according to the power-off signal CPS.

Next, in step S340 , the source driver 100 may generate the start-up power signal SPS according to the control signal CS through the signal detection circuit 130 . In step S350, the source driver 100 can restore the clock data recovery circuit 110 through the power control circuit 140 according to the start power signal SPS.

The implementation details of each step are described in detail in the foregoing embodiments and implementation manners, and details are not repeated below.

To sum up, the source driver according to the embodiments of the present invention can use the power control circuit to power off at least one or all of the clock data recovery circuit, the digital circuit and the driving circuit according to the power off signal. In addition, at least one or all of the clock data recovery circuit, the digital circuit and the driving circuit are recovered by using the power control circuit according to the start-up power signal. In this way, the source driver according to the embodiments of the present invention can reduce the overall power consumption of the source driver during the non-display time interval, thereby achieving the effect of power saving.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection shall be defined by the appended claims.

Claims (8)

1. A source driver, comprising: a clock data recovery circuit for receiving an original data signal from an external device, and generating a clock signal and a first data signal according to the original data signal; a digital circuit, coupled to the clock data recovery circuit for receiving the clock signal and the first data signal, and generating a power-off signal according to the first data signal; a signal detection circuit for receiving a control signal from the external device, and generating a start-up power signal according to the control signal; and A power supply control circuit, coupled to the digital circuit to receive the power-off signal, and coupled to the signal detection circuit to receive the start-up power signal, wherein the power control circuit makes all the power-off signals according to the power-off signal The clock data recovery circuit is powered off, and the power control circuit powers up the clock data recovery circuit according to the start-up power signal. 2. The source driver of claim 1, wherein the power control circuit powers off the clock data recovery circuit during a non-display time period. 3. The source driver of claim 2, wherein the non-display time period includes a vertical blanking period. 4. The source driver of claim 1, wherein the digital circuit detects a vertical blanking start signal in the first data signal, and generates the power-off according to the vertical blanking start signal signal to the power control circuit. 5. The source driver of claim 1, wherein the signal detection circuit detects a falling edge of the control signal, and generates the start-up power signal for the power control according to the falling edge of the control signal circuit. 6. The source driver of claim 1, wherein the power control circuit further powers down the digital circuit in accordance with the power-off signal, and the power control circuit also powers the digital circuit in accordance with the start-up power signal. Re-energize digital circuits. 7. The source driver of claim 1, wherein the digital circuit outputs a second data signal according to the first data signal, the source driver further comprising: a driving circuit, coupled to the clock data recovery circuit to receive the clock signal, and coupled to the digital circuit to receive the second data signal, wherein the driving circuit is used for receiving the second data signal to drive the display panel; The power control circuit also powers off the drive circuit according to the power cutoff signal, and the power control circuit also restores power to the drive circuit according to the start power signal. 8. The source driver of claim 1, wherein the power control circuit comprises a power-on/power-off reset circuit.

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