[go: up one dir, main page]

CN111276447B - 双侧冷却功率模块及其制造方法 - Google Patents

双侧冷却功率模块及其制造方法 Download PDF

Info

Publication number
CN111276447B
CN111276447B CN201911222003.9A CN201911222003A CN111276447B CN 111276447 B CN111276447 B CN 111276447B CN 201911222003 A CN201911222003 A CN 201911222003A CN 111276447 B CN111276447 B CN 111276447B
Authority
CN
China
Prior art keywords
lower substrate
substrate
semiconductor chip
power module
double
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201911222003.9A
Other languages
English (en)
Other versions
CN111276447A (zh
Inventor
赵汉信
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hyundai Mobis Co Ltd
Original Assignee
Hyundai Mobis Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Mobis Co Ltd filed Critical Hyundai Mobis Co Ltd
Publication of CN111276447A publication Critical patent/CN111276447A/zh
Application granted granted Critical
Publication of CN111276447B publication Critical patent/CN111276447B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49531—Additional leads the additional leads being a wiring board
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H01L23/49844—Geometry or layout for individual devices of subclass H10D
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
    • H01L2021/60097—Applying energy, e.g. for the soldering or alloying process
    • H01L2021/60195—Applying energy, e.g. for the soldering or alloying process using dynamic pressure, e.g. ultrasonic or thermosonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60277—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving the use of conductive adhesives
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/1329—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/13294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/132 - H01L2224/13291
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298—Fillers
    • H01L2224/13299—Base material
    • H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29075—Plural core members
    • H01L2224/2908—Plural core members being stacked
    • H01L2224/29082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/29294—Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/3001—Structure
    • H01L2224/3003—Layer connectors having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/3301—Structure
    • H01L2224/3303—Layer connectors having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92225—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本发明提供了一种双侧冷却功率模块及其制造方法，该双侧冷却功率模块包括在其至少一个表面上包括凹陷部的下基板、形成在凹陷部中的半导体芯片、形成在下基板的两端的引线框架、以及形成在半导体芯片、引线框架的至少一部分以及下基板上的上基板。

Description

双侧冷却功率模块及其制造方法
相关申请的交叉引用
本申请要求于2018年12月5日提交的韩国专利申请第10-2018-0155073号的优先权，其内容通过引用并入本文。
技术领域
本发明涉及一种双侧冷却功率模块及其制造方法，并且更具体地，涉及一种双侧冷却功率模块及其制造方法，该双侧冷却功率模块应用于用于环保型车辆(混合动力电动车辆(HEV)、电动车辆(EV)、插电式混合动力车辆(PHEV)等)的逆变器，并且该双侧冷却功率模块应用了SiC元件。
背景技术
一种应用于用于环保型车辆(HEV、EV、PHEV等)的逆变器的双侧冷却功率模块，当其采用其中多个SiC元件形成多芯片的配置时，可以满足电气规格。使用引线接合方法安装多个SiC元件。在这种情况下，每个元件芯片具有彼此不同的布线的长度，这引起寄生电感的问题。
在芯片性能保持在200℃或更高的SiC元件的结温(Tj)的情况下需要模块技术才能发挥优势。常规地，SiC元件通过焊接方法接合。然而，在焊接方法的情况下，由于焊料的熔点在从180℃至220℃的范围内，因此当焊料在高温下使用时会发生过早劣化。
另外，由于双侧冷却功率模块是通过焊接制造的，因此由于其中的材料之间的热膨胀系数(CTE)的差异而发生翘曲(warpage)，从而导致模块的高故障率。由于施加了SiC元件的模块的芯片尺寸较小，因此存在一个问题，即与具有较大芯片尺寸的绝缘栅双极晶体管(IGBT)相比，该模块将热量传递到芯片的上基板的面积较小，从而增加了热阻。
发明内容
已经做出本发明以解决包括(including)以上问题的各种问题，并且本发明的目的是提供一种双侧冷却功率模块及其制造方法，在该双侧冷却功率模块中，可以简化模块的内部结构用于高效双侧冷却。然而，以上目的是示例性的，并且本发明的范围不限于此。
根据本发明的一个方面，提供了一种双侧冷却功率模块。该双侧冷却功率模块可以包括：下基板，在其至少一个表面上具有凹陷部；半导体芯片，其形成在凹陷部中；引线框架，形成在下基板的两端；以及上基板，形成在半导体芯片、引线框架的至少一部分以及下基板上。
在双侧冷却功率模块中，可以通过将下基板的上表面的至少一部分处理为阶梯状使得半导体芯片不向下基板的上表面凸出来形成凹陷部。
在双侧冷却功率模块中，凹陷部与半导体芯片之间的内部空间可以填充有底部填充物。
在双侧冷却功率模块中，下基板的两端可以被处理成阶梯状，使得引线框架不向下基板的上表面凸出。
在双侧冷却功率模块中，半导体芯片可以通过使用导电性粘合剂接合到下基板的上表面和上基板的下表面。
在双侧冷却功率模块中，半导体芯片可以包括SiC MOSFET元件。
在双侧冷却功率模块中，上基板的下表面的两端可以被处理成阶梯状。
在双侧冷却功率模块中，下基板的两端和上基板的两端可以通过在其上施加非导电性粘合剂而彼此接合。
在双侧冷却功率模块中，可以提供形成为围绕下基板、引线框架以及上基板的外周表面的模制部，并且引线框架的至少一部分可以向模制部外部凸出。
根据本发明的另一方面，提供了一种双侧冷却功率模块的制造方法。该双侧冷却功率模块的制造方法可以包括以下处理：在下基板的至少一个表面上形成凹陷部；在凹陷部中形成半导体芯片；在下基板的两端形成引线框架；并且在半导体芯片、引线框架的至少一部分以及下基板上形成上基板。
在双侧冷却功率模块的制造方法中，凹陷部可以被处理成阶梯状，使得半导体芯片不向下基板的上表面凸出，并且形成半导体芯片的处理可以包括以下处理：将导电性粘合剂施加到半导体芯片的下表面，并且然后将半导体芯片接合到凹陷部中；以及用底部填充物填充凹陷部与半导体芯片之间的内部空间。
在双侧冷却功率模块的制造方法中，形成引线框架的处理可以包括以下处理：将下基板的两端处理为阶梯状，使得在引线框架接合到下基板的两端之前，引线框架不向下基板的上表面凸出；以及使用烧结方法或超声波焊接方法将引线框架接合到阶梯状的下基板的两端。
在双侧冷却功率模块的制造方法中，形成上基板的处理可以包括以下处理：将导电性粘合剂施加到半导体芯片的上表面；将非导电性粘合剂施加到除了半导体芯片的上表面之外的下基板和引线框架；将非导电性粘合剂施加到上基板的下表面的两端；以及将施加了非导电性粘合剂的下基板和上基板设置为彼此面对，并且然后将下基板和上基板接合。
在双侧冷却功率模块的制造方法中，可以在将非导电性粘合剂施加到上基板的下表面的两端的处理之前，提供将上基板的下表面的两端处理为阶梯状的处理。
在双侧冷却功率模块的制造方法中，可以在形成上基板的处理之后，提供形成围绕下基板、引线框架以及上基板的外周表面的模制部的处理，并且引线框架的至少一部分可以向模制部外部凸出。
根据如上所述配置的本发明的一个实施方式，由于电流路径的匹配和电阻组件的减少，对于多芯片的SiC MOSFET的快速开关可以实现大的减小效果，芯片温度可以在200℃以上使用，从而减少混合动力电动车辆的冷却系统，通过用两个平板压力机压制、加热以及接合，可以最大限度地减小由于模块厚度和材料的热膨胀系数中的差异而引起的热形变(thermal deformation)，并且热阻可以比常规IGBT模块的热阻低，使得芯片内部的热量可以更快地释放，从而减少冷却系统上的负载。
另外，由于具有良好的导热性的烧结接合部，因此可以实现具有除垫片以外的散热路径的双侧冷却功率模块及其制造方法，从而能够实现高效散热。还应当理解，本发明的范围不受以上效果的限制。
附图说明
图1至图13是按其处理顺序(sequence)的次序(order)示意性地示出根据本发明的一个实施方式的双侧冷却功率模块的制造方法的截面图。
图14是示意性地示出根据本发明的比较示例的双侧冷却功率模块的截面图。
具体实施方式
在下文中，将参考附图详细描述本发明的实施方式。然而，应当理解，本发明不限于以下描述的实施方式，并且可以以各种不同的形式来实现，并且提供以下实施方式以使本发明的公开完整并且将本发明的范围完全传达给本领域技术人员。另外，为了便于描述，可以夸大或减小图中的组件的尺寸。
在下文中，下面将参考图1至图13描述由双侧冷却功率模块的结构和处理导致的问题及其解决方案。
首先，图14是示意性地示出根据本发明的比较示例的双侧冷却功率模块的截面图。双侧冷却功率模块2000可以包括下基板100、半导体芯片200、引线框架300、垫片400、上基板500以及模制部600。
例如，将有源金属钎焊铜(AMC)基板或直接接合铜(DBC)基板用于下基板100和上基板500。首先，通过使用第一焊料预制件802焊接到下基板100上来接合用于驱动混合动力车辆的马达的半导体芯片200。这里，半导体芯片200具有作为发射极的上表面和作为集电极的下表面，并且被操作使得电流从集电极流向发射极。二极管也以类似的方式工作。
此后，引线框架300形成在下基板100上，并且半导体芯片200和引线框架300中的任何一个通过引线接合彼此连接。随后，通过使用第二焊料预制件804焊接在半导体芯片200上来接合垫片400，并且通过使用第三焊料预制件806焊接在垫片400上来接合上基板500，然后第三焊料预制件806被模制部600封装以形成整体结构。
另一方面，例如，可以将诸如铜(Cu)的具有良好的导电性的金属用于垫片400，并且垫片400具有按次序保持下基板100与上基板500之间的间隙以便保护电连接半导体芯片200和第一外部引线310的布线900的功能。
上述结构导致以下问题。多个半导体芯片200使用例如SiC元件并且使用引线接合方法安装。在这种情况下，每个半导体芯片200具有彼此不同的布线的长度，这引起寄生电感的问题。此外，芯片性能保持在200℃或更高的SiC元件的结温Tj，这需要模块技术才能发挥其优势。常规地，半导体芯片200通过焊接接合。然而，在焊接方法的情况下，由于焊料的熔点在从180℃至220℃的范围内，因此当焊料在高温下使用时会发生过早劣化。
另外，由于双侧冷却功率模块2000是通过焊接制造的，因此由于其中的材料之间的热膨胀系数(CTE)的差异而发生翘曲，从而导致模块的高故障率。由于施加了SiC元件的模块具有小的芯片尺寸，因此存在一个问题，即与具有较大芯片尺寸的绝缘栅双极晶体管(IGBT)相比，该模块将热量传递到芯片的上基板的面积较小，从而增加热阻。
为了解决该问题，本发明提供了一种双侧冷却功率模块及其制造方法，在该双侧冷却功率模块中，简化了模块的内部结构，由于坚固的结构而提高了模块的性能，提供了其中在模块的两侧可以冷却的结构，将散热表面设计为绝缘，并且提供了接合接触，使得芯片的功率端子和信号端子可以接合到模块的外部控制板，从而提供良好的冷却效率。
图1至图13是按其处理顺序的顺序示意性地示出根据本发明的一个实施方式的双侧冷却功率模块的制造方法的截面图。
首先，参考图13，根据本发明的实施方式的双侧冷却功率模块1000可以包括在其至少一个表面上具有凹陷部110的下基板100、形成在凹陷部110中的半导体芯片200、形成在下基板100的两端的引线框架300、以及形成在半导体芯片200、引线框架300的至少一部分以及下基板100上的上基板500。
这里，凹陷部110可以通过将下基板100的上表面的至少一部分处理为阶梯状来形成，使得半导体芯片200不向下基板100的上表面凸出。Cu布线可以形成在凹陷部110和下基板100的上表面上。在阶梯处理中，半导体芯片200可以形成为不向下基板100的上表面凸出。然而，更优选的是提供其中半导体芯片200的接合部分形成为不在下基板100上凸出的结构。在这种情况下，半导体芯片200的上表面可以根据Cu凸块的高度形成为高于下基板100的上表面。
另一方面，例如，半导体芯片200可以包括SiC MOSFET元件。在半导体芯片200中，可以在栅极和源极电极焊盘210上形成Cu凸块220，并且可以在其上层压并接合第一导电性粘合剂810。例如，可以将Ag膜或浆料用于第一导电性粘合剂810。
此时，凹陷部110与半导体芯片200之间的内部空间填充有底部填充物120。例如，诸如环氧树脂等的树脂可以用于底部填充物120的材料。
另外，下基板100的两端可以被处理成阶梯状，使得引线框架300不向下基板100的上表面凸出。引线框架300形成在两个阶梯状端部处，以用作功率端子和信号端子。在形成引线框架300之后，可以将非导电性粘合剂施加到需要绝缘的区域(在下基板100的两端)，可以将非导电性粘合剂施加到对应于该区域的上基板500的下表面的两端，并且随后它们可以接合以彼此面对。这里，任选地，上基板500的下表面的两端可以以阶梯形式接合以增加与半导体芯片200的接合，并且将导电性粘合剂施加到半导体芯片200的上表面以将下基板100和上基板500彼此接合。在这种情况下，使用第二导电性粘合剂820将半导体芯片200的上表面直接接合到上基板500的下表面，使得可以省略常规使用的垫片。
另一方面，提供形成为围绕下基板100、引线框架300以及上基板500的外周表面的模制部600，并且引线框架300的至少一部分可以向模制部600外部凸出。
在下文中，将参考图1至图13详细描述根据本发明的一个实施方式的双侧冷却功率模块1000的制造方法。
参考图1和图2，在根据本发明的一个实施方式的双侧冷却功率模块1000的制造方法中，可以在下基板100的至少一个表面上形成凹陷部110。这里，下基板100包括直接接合铜(DBC)基板，并且DBC基板包括在第一金属层102与第二金属层106之间的陶瓷层104。
凹陷部110形成在所准备的下基板100的至少一个表面上，例如，下基板100的上表面上。凹陷部110已被处理成阶梯状，使得稍后将被接合的半导体芯片(图3所示的200)不会向下基板100的上表面凸出。然而，根据下基板100的厚度或第二金属层106的厚度，凹陷部110可以被处理成阶梯状，以具有图3所示的半导体芯片200的接合部分不凸出到其上的高度。
此后，如图3所示，半导体芯片200可以形成在凹陷部110中。半导体芯片200具有其中凸块220形成在焊盘210上，并且通过倒装芯片接合到凹陷部110来接合的结构。在这种情况下，凸块220的接合表面使用导电膏或膜来接合。如图4所示，在完成接合之后，底部填充物120填充在凹陷部110与半导体芯片200之间的内部空间中。
如图5所示，第一阶梯130形成在将形成图6所示的引线框架300的位置处。第一阶梯130可以被处理成在下基板100的两端上为阶梯状，使得图6所示的引线框架300不向下基板100的上表面凸出。此后，如图6所示，可以使用烧结方法或超声波焊接方法将引线框架300接合到第一阶梯130。
参考图7，在接合引线框架300之后，可以将第二导电性粘合剂820施加到半导体芯片200的上表面，并且可以应用第一非导电性粘合剂830以使未应用第二导电性粘合剂820的下基板100的上表面与引线框架300的至少一部分绝缘。
另一方面，参考图8至图10，上基板500可以使用与下基板100相同类型的基板，并且可以在第一金属层502与第二金属层506之间设置有陶瓷层504。可以将第二非导电性粘合剂840施加到所准备的上基板500的下表面(即，第一金属层502的两端)，使得第二非导电性粘合剂840可以对应于在相同区域中应用于下基板100的两端的第一非导电性粘合剂830。这里，第一非导电性粘合剂830和第二非导电性粘合剂840可以相同。
任选地，在将第二非导电性粘合剂840施加到上基板500的下表面的两端之前，第二阶梯530可以形成在上基板500的第一金属层502的两端上。不一定形成第二阶梯530，但是可以理解，执行用于形成阶梯的部分处理以增强接合到半导体芯片200的部分的接合特性。
接下来，参考图11和图12，可以将施加了第一非导电性粘合剂830的下基板100和施加了第二非导电性粘合剂840的上基板500设置为彼此面对，并且随后可以将下基板100和上基板500彼此接合。在这种情况下，加热器框700设置在下基板100的第一金属层102的下表面和上基板500的第二金属层506的上表面上，并且然后通过在箭头方向应用力而被热压缩，上基板500可以被热压缩并接合到半导体芯片200、引线框架300的至少一部分以及下基板100。
这里，半导体芯片200通过经由第二导电性粘合剂820烧结而接合，并且粘合剂的固化反应发生在施加了第一非导电性粘合剂830和第二非导电性粘合剂840的绝缘区域中，由此半导体芯片200的上表面经由第二导电性粘合剂820直接接合到上基板500的下表面，使得可以省略常规使用的垫片。
如图13所示，在接合上基板500之后，模制部600形成为围绕下基板100、引线框架300以及上基板500的外周表面，使得引线框架300的至少一部分向模制部600外部凸出，由此可以制造具有简化的内部结构的双侧冷却功率模块1000，以适用于用于环保型车辆的逆变器。
这里，例如，诸如环氧模塑化合物(EMC)或聚酰亚胺基材料的具有良好的绝缘和保护性能的聚合物材料可以用于模制部600。模制部600可以封装除了引线框架300暴露的区域、下基板100的下表面以及上基板500的上表面之外的所有区域。由于以上结构不使用垫片，因此可以容易地绝缘和固定模块的边缘与功率端子和信号端子之间的区域，而无需用模制部600填充在下基板100与上基板500之间形成的间隙。
尽管未在图中示出，但是最后，在形成模制部600之后，可以修剪引线框架300的至少一部分。在修剪引线框架300的不必要部分之后，模块可以具有其中仅信号端子和功率端子向模制部600外部凸出的形式。
如上所述，在根据本发明的实施方式的双侧冷却功率模块中，可以通过使用Ag凸块和Cu图案(而不是Al引线)接合的倒装芯片接合SiC元件来省略垫片，并且可以减小或消除下DBC基板和上DBC基板之间的模制部，从而提供良好的散热特性。
另外，可以减小由于引线接合引起的电阻-电容(RC)延迟，即使在200℃或更高的高温下也能保持芯片性能，并且可以控制模制处理期间基板的翘曲。由于模块内部全部填充有材料，因此即使从上方和下方对模块应用热压力，温度和压力分布也均匀地影响整个区域，而无需集中在芯片上，并且因此可以平稳地执行模制处理。
此外，常规地，模块通过与设置在其中的垫片金属焊接而接合。因此，向其应用具有大的热阻的焊料层，这导致减小其厚度的限制。然而，根据本发明，由于可以在减小厚度的同时形成比IGBT模块中的Cu层相对更厚的Cu层，因此可以通过增加芯片的横向上的热量的扩散速率来实现高效冷却。
尽管已参考图中所示的实施方式描述了本发明，但是应当理解，这些实施方式仅仅是示例性的，并且本领域技术人员可以基于以上进行各种修改和等同的其他实施方式。因此，本发明的真实技术范围应由所附权利要求的技术精神来限定。
参考文献的说明
100 下基板
110 凹陷部
120 底部填充物
130 第一阶梯
102、502 第一金属层
104、504 陶瓷层
106、506 第二金属层
200 半导体芯片
210 焊盘
220 Cu凸块
300 引线框架
400 垫片
500 上基板
530 第二阶梯
600 模制部
700 加热器框
802 第一焊料预制件
804 第二焊料预制件
806 第三焊料预制件
810 第一导电性粘合剂
820 第二导电性粘合剂
830 第一非导电性粘合剂
840 第二非导电性粘合剂
900 布线
1000、2000 双侧冷却功率模块。

Claims (13)

1.一种双侧冷却功率模块，包括：
下基板，在所述下基板的至少一个表面上包括凹陷部；
半导体芯片，形成在所述凹陷部中；
引线框架，形成在所述下基板的两端；以及
上基板，所述上基板形成在所述半导体芯片、所述引线框架的至少一部分以及所述下基板上，
其中，所述上基板和所述下基板包括直接接合铜DBC基板，
其中，所述半导体芯片通过使用导电性粘合剂接合到所述下基板的上表面和所述上基板的下表面，
其中，通过在所述下基板的两端和所述上基板的两端上施加非导电性粘合剂而使所述下基板的两端和所述上基板的两端彼此接合。
2.根据权利要求1所述的双侧冷却功率模块，其中，所述凹陷部是通过将所述下基板的上表面的至少一部分处理成阶梯状而形成的，以使所述半导体芯片不向所述下基板的上表面凸出。
3.根据权利要求1所述的双侧冷却功率模块，其中，在所述凹陷部与所述半导体芯片之间的内部空间中填充有底部填充物。
4.根据权利要求1所述的双侧冷却功率模块，其中，所述下基板的两端被处理成阶梯状，以使所述引线框架不向所述下基板的上表面凸出。
5.根据权利要求1所述的双侧冷却功率模块，其中，所述半导体芯片包括SiC MOSFET元件。
6.根据权利要求1所述的双侧冷却功率模块，其中，所述上基板的所述下表面的两端被处理成阶梯状。
7.根据权利要求1所述的双侧冷却功率模块，还包括模制部，所述模制部形成为围绕所述下基板、所述引线框架以及所述上基板的外周表面，
其中，所述引线框架的至少一部分向所述模制部的外部凸出。
8.一种双侧冷却功率模块的制造方法，所述方法包括以下处理：
在下基板的至少一个表面上形成凹陷部；
在所述凹陷部中形成半导体芯片；
在所述下基板的两端形成引线框架；并且
在所述半导体芯片、所述引线框架的至少一部分以及所述下基板上形成上基板，
其中，形成所述半导体芯片包括：
将导电性粘合剂施加到所述半导体芯片的下表面，并且随后将所述半导体芯片接合到所述凹陷部中，
其中，形成所述上基板包括：
将非导电性粘合剂施加到所述下基板的两端和所述上基板的下表面的两端；并且
将施加了所述非导电性粘合剂的所述下基板和所述上基板设置为彼此面对，并且随后将所述下基板和所述上基板接合，
其中，所述下基板和所述上基板包括直接接合铜DBC基板。
9.根据权利要求8所述的双侧冷却功率模块的制造方法，
其中，所述凹陷部被处理成阶梯状，以使所述半导体芯片不向所述下基板的上表面凸出，并且
形成所述半导体芯片的处理还包括以下处理：
用底部填充物填充所述凹陷部与所述半导体芯片之间的内部空间。
10.根据权利要求8所述的双侧冷却功率模块的制造方法，
其中，形成所述引线框架的处理包括以下处理：
将所述下基板的两端处理为阶梯状，以使在将所述引线框架接合到所述下基板的两端之前，所述引线框架不向所述下基板的上表面凸出；并且
使用烧结方法或超声波焊接方法将所述引线框架接合到阶梯状的所述下基板的两端。
11.根据权利要求8所述的双侧冷却功率模块的制造方法，
其中，形成所述上基板的处理还包括以下处理：在将所述非导电性粘合剂施加到所述下基板的两端和所述上基板的下表面的两端之前，
将导电性粘合剂施加到所述半导体芯片的上表面；
将非导电性粘合剂施加到除所述半导体芯片的上表面之外的所述引线框架。
12.根据权利要求8所述的双侧冷却功率模块的制造方法，还包括以下处理：其中，在将所述非导电性粘合剂施加到所述上基板的下表面的两端的处理之前，将所述上基板的下表面的两端处理成阶梯状。
13.根据权利要求8所述的双侧冷却功率模块的制造方法，还包括以下处理：在形成所述上基板的处理之后，围绕所述下基板、所述引线框架以及所述上基板的外周表面形成模制部，
其中，所述引线框架的至少一部分向所述模制部外部凸出。
CN201911222003.9A 2018-12-05 2019-12-03 双侧冷却功率模块及其制造方法 Active CN111276447B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2018-0155073 2018-12-05
KR1020180155073A KR102163662B1 (ko) 2018-12-05 2018-12-05 양면 냉각 파워 모듈 및 이의 제조방법

Publications (2)

Publication Number Publication Date
CN111276447A CN111276447A (zh) 2020-06-12
CN111276447B true CN111276447B (zh) 2023-06-23

Family

ID=70776489

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911222003.9A Active CN111276447B (zh) 2018-12-05 2019-12-03 双侧冷却功率模块及其制造方法

Country Status (4)

Country Link
US (2) US11251112B2 (zh)
KR (1) KR102163662B1 (zh)
CN (1) CN111276447B (zh)
DE (1) DE102019132837B4 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021125722A1 (ko) * 2019-12-16 2021-06-24 주식회사 아모센스 파워모듈용 세라믹 기판 및 이를 포함하는 파워모듈
KR20210129483A (ko) * 2020-04-20 2021-10-28 현대자동차주식회사 솔더링 구조, 이를 갖는 파워 모듈 및 파워 모듈의 제조 방법
KR20220005260A (ko) 2020-07-06 2022-01-13 엘지전자 주식회사 전력모듈 신터링 장비
CN111933604B (zh) * 2020-07-08 2021-07-27 南京晟芯半导体有限公司 一种提高半导体场效应晶体管芯片短路能力的结构及方法
US11776871B2 (en) * 2020-12-15 2023-10-03 Semiconductor Components Industries, Llc Module with substrate recess for conductive-bonding component
KR20230001943A (ko) 2021-06-29 2023-01-05 현대자동차주식회사 파워 모듈 및 파워 모듈 제조 방법
US12230601B2 (en) * 2022-02-08 2025-02-18 Semiconductor Components Industries, Llc High power module package structures

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102324407A (zh) * 2011-09-22 2012-01-18 日月光半导体制造股份有限公司 半导体封装件及其制造方法
CN102456634A (zh) * 2010-10-19 2012-05-16 联京光电股份有限公司 封装板与其制造方法
CN103378018A (zh) * 2012-04-13 2013-10-30 三星电机株式会社 双侧冷却功率半导体模块及使用该模块的多堆叠功率半导体模块包
KR101847168B1 (ko) * 2016-12-08 2018-04-09 현대오트론 주식회사 파워 모듈 패키지의 제조방법 및 이를 이용한 파워 모듈 패키지
CN107919349A (zh) * 2016-10-06 2018-04-17 现代自动车株式会社 双侧冷却式电源模块及其制造方法
JP2018074059A (ja) * 2016-11-01 2018-05-10 株式会社デンソー 半導体装置

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4538170A (en) 1983-01-03 1985-08-27 General Electric Company Power chip package
JP3362530B2 (ja) * 1993-12-16 2003-01-07 セイコーエプソン株式会社 樹脂封止型半導体装置およびその製造方法
KR100583494B1 (ko) * 2000-03-25 2006-05-24 앰코 테크놀로지 코리아 주식회사 반도체패키지
US6906414B2 (en) * 2000-12-22 2005-06-14 Broadcom Corporation Ball grid array package with patterned stiffener layer
JP4270095B2 (ja) * 2004-01-14 2009-05-27 株式会社デンソー 電子装置
DE102004011203B4 (de) * 2004-03-04 2010-09-16 Robert Bosch Gmbh Verfahren zum Montieren von Halbleiterchips und entsprechende Halbleiterchipanordnung
US20060284301A1 (en) * 2005-06-17 2006-12-21 Corisis David J CSP semiconductor chip and BGA assembly with enhanced physical protection, protective members and assemblies used with same, and methods of enhancing physical protection of chips and assemblies
US20060289892A1 (en) * 2005-06-27 2006-12-28 Lee Jae S Method for preparing light emitting diode device having heat dissipation rate enhancement
TWI296037B (en) * 2006-04-28 2008-04-21 Delta Electronics Inc Light emitting apparatus
JP2006310887A (ja) * 2006-07-25 2006-11-09 Nippon Leiz Co Ltd 光源装置の製造方法
KR100888195B1 (ko) * 2007-08-06 2009-03-12 한국과학기술원 능동소자가 내장된 유기기판 제조방법
US20110247197A1 (en) * 2008-01-09 2011-10-13 Feinics Amatech Teoranta Forming channels for an antenna wire of a transponder
JP5365627B2 (ja) 2008-04-09 2013-12-11 富士電機株式会社 半導体装置及び半導体装置の製造方法
US7759778B2 (en) * 2008-09-15 2010-07-20 Delphi Technologies, Inc. Leaded semiconductor power module with direct bonding and double sided cooling
US8354740B2 (en) * 2008-12-01 2013-01-15 Alpha & Omega Semiconductor, Inc. Top-side cooled semiconductor package with stacked interconnection plates and method
US8680656B1 (en) * 2009-01-05 2014-03-25 Amkor Technology, Inc. Leadframe structure for concentrated photovoltaic receiver package
KR20120018811A (ko) * 2009-05-27 2012-03-05 쿠라미크 엘렉트로닉스 게엠베하 냉각 전기 회로
JP5936810B2 (ja) * 2009-09-11 2016-06-22 ローム株式会社 発光装置
US8613132B2 (en) * 2009-11-09 2013-12-24 Feinics Amatech Teoranta Transferring an antenna to an RFID inlay substrate
KR20130143061A (ko) * 2010-11-03 2013-12-30 쓰리엠 이노베이티브 프로퍼티즈 컴파니 와이어 본드 프리 다이를 사용한 가요성 led 디바이스
US8927339B2 (en) * 2010-11-22 2015-01-06 Bridge Semiconductor Corporation Method of making thermally enhanced semiconductor assembly with bump/base/flange heat spreader and build-up circuitry
US8354684B2 (en) * 2011-01-09 2013-01-15 Bridgelux, Inc. Packaging photon building blocks having only top side connections in an interconnect structure
US8350376B2 (en) 2011-04-18 2013-01-08 International Rectifier Corporation Bondwireless power module with three-dimensional current routing
US9178093B2 (en) * 2011-07-06 2015-11-03 Flextronics Ap, Llc Solar cell module on molded lead-frame and method of manufacture
US8716864B2 (en) 2012-06-07 2014-05-06 Ixys Corporation Solderless die attach to a direct bonded aluminum substrate
DE102013220880B4 (de) * 2013-10-15 2016-08-18 Infineon Technologies Ag Elektronisches Halbleitergehäuse mit einer elektrisch isolierenden, thermischen Schnittstellenstruktur auf einer Diskontinuität einer Verkapselungsstruktur sowie ein Herstellungsverfahren dafür und eine elektronische Anordung dies aufweisend
US9847235B2 (en) * 2014-02-26 2017-12-19 Infineon Technologies Ag Semiconductor device with plated lead frame, and method for manufacturing thereof
KR102337876B1 (ko) * 2014-06-10 2021-12-10 삼성전자주식회사 반도체 패키지 및 그 제조 방법
KR20170024254A (ko) * 2015-08-25 2017-03-07 현대자동차주식회사 파워 반도체 모듈 및 이의 제조 방법
KR20170039431A (ko) * 2015-10-01 2017-04-11 현대자동차주식회사 솔더링 접합방식 인버터 및 이를 적용한 하이브리드 차량
US9952110B2 (en) * 2016-03-29 2018-04-24 Infineon Technologies Ag Multi-die pressure sensor package
KR101897641B1 (ko) * 2016-11-29 2018-10-04 현대오트론 주식회사 파워 모듈 패키지의 제조방법 및 이를 이용한 파워 모듈 패키지
JP6885175B2 (ja) 2017-04-14 2021-06-09 富士電機株式会社 半導体装置
JP6834815B2 (ja) * 2017-07-06 2021-02-24 株式会社デンソー 半導体モジュール
JP7040032B2 (ja) * 2018-01-17 2022-03-23 株式会社デンソー 半導体装置
JP2019153752A (ja) * 2018-03-06 2019-09-12 トヨタ自動車株式会社 半導体装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102456634A (zh) * 2010-10-19 2012-05-16 联京光电股份有限公司 封装板与其制造方法
CN102324407A (zh) * 2011-09-22 2012-01-18 日月光半导体制造股份有限公司 半导体封装件及其制造方法
CN103378018A (zh) * 2012-04-13 2013-10-30 三星电机株式会社 双侧冷却功率半导体模块及使用该模块的多堆叠功率半导体模块包
CN107919349A (zh) * 2016-10-06 2018-04-17 现代自动车株式会社 双侧冷却式电源模块及其制造方法
JP2018074059A (ja) * 2016-11-01 2018-05-10 株式会社デンソー 半導体装置
KR101847168B1 (ko) * 2016-12-08 2018-04-09 현대오트론 주식회사 파워 모듈 패키지의 제조방법 및 이를 이용한 파워 모듈 패키지

Also Published As

Publication number Publication date
US11862542B2 (en) 2024-01-02
US11251112B2 (en) 2022-02-15
KR102163662B1 (ko) 2020-10-08
DE102019132837B4 (de) 2022-06-15
KR20200068285A (ko) 2020-06-15
US20220102249A1 (en) 2022-03-31
DE102019132837A1 (de) 2020-06-10
US20200185310A1 (en) 2020-06-11
CN111276447A (zh) 2020-06-12

Similar Documents

Publication Publication Date Title
CN111276447B (zh) 双侧冷却功率模块及其制造方法
KR102585450B1 (ko) 브레이징된 전기 전도성 층을 포함하는 칩 캐리어를 구비한 몰딩된 패키지
US9171773B2 (en) Semiconductor device
JP6115738B2 (ja) 半導体装置およびその製造方法
US11776867B2 (en) Chip package
JP2009536458A (ja) 半導体モジュール及びその製造方法
US11127651B2 (en) High power module semiconductor package with multiple submodules
JP2019079905A (ja) 半導体装置および半導体装置の製造方法
CN110268519A (zh) 功率半导体模块
JP5899952B2 (ja) 半導体モジュール
JP4096741B2 (ja) 半導体装置
EP3739624A1 (en) Semiconductor arrangement with a compressible contact element encapsulated between two carriers and corresponding manufacturing method
US11594510B2 (en) Assembly processes for semiconductor device assemblies including spacer with embedded semiconductor die
JP2023054418A (ja) 電力用半導体装置及びその製造方法
JP5895549B2 (ja) 半導体装置及びその製造方法
US11177224B2 (en) Method of manufacturing semiconductor device
US9263421B2 (en) Semiconductor device having multiple chips mounted to a carrier
CN111354710A (zh) 半导体装置及其制造方法
JP2012238737A (ja) 半導体モジュール及びその製造方法
CN115206919A (zh) 半导体装置
CN117043937A (zh) 半导体装置以及半导体装置的制造方法
JP4258391B2 (ja) 半導体装置
JP2024106085A (ja) 半導体装置、電力変換装置、及び半導体装置の製造方法
JP2002134560A (ja) 半導体装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20210311

Address after: Seoul, South Kerean

Applicant after: HYUNDAI MOBIS Co.,Ltd.

Address before: Seoul, South Kerean

Applicant before: HYUNDAI AUTRON Co.,Ltd.

GR01 Patent grant
GR01 Patent grant