CN111276406B - 扇出型晶圆级封装结构及其制造方法 - Google Patents
扇出型晶圆级封装结构及其制造方法 Download PDFInfo
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- 238000004806 packaging method and process Methods 0.000 title claims description 40
- 238000004519 manufacturing process Methods 0.000 title claims description 24
- 239000010410 layer Substances 0.000 claims abstract description 235
- 238000000034 method Methods 0.000 claims abstract description 38
- 239000012790 adhesive layer Substances 0.000 claims abstract description 33
- 238000005520 cutting process Methods 0.000 claims abstract description 9
- 229920006336 epoxy molding compound Polymers 0.000 claims description 19
- 238000002161 passivation Methods 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 238000010030 laminating Methods 0.000 claims 1
- 238000003475 lamination Methods 0.000 claims 1
- 238000005498 polishing Methods 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 description 9
- 238000013461 design Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 6
- 238000012858 packaging process Methods 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000004033 plastic Substances 0.000 description 3
- XBWAZCLHZCFCGK-UHFFFAOYSA-N 7-chloro-1-methyl-5-phenyl-3,4-dihydro-2h-1,4-benzodiazepin-1-ium;chloride Chemical compound [Cl-].C12=CC(Cl)=CC=C2[NH+](C)CCN=C1C1=CC=CC=C1 XBWAZCLHZCFCGK-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000012459 cleaning agent Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000013036 cure process Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000002355 dual-layer Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000499 gel Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000000741 silica gel Substances 0.000 description 1
- 229910002027 silica gel Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
- H01L2224/17104—Disposition relative to the bonding areas, e.g. bond pads
- H01L2224/17106—Disposition relative to the bonding areas, e.g. bond pads the bump connectors being bonded to at least one common bonding area
- H01L2224/17107—Disposition relative to the bonding areas, e.g. bond pads the bump connectors being bonded to at least one common bonding area the bump connectors connecting two common bonding areas
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Abstract
提供一种扇出型晶圆级封装结构及其制造方法,该方法包括:提供支撑晶片层,于支撑晶片层上形成粘合剂层;将多个裸片粘合至粘合剂层表面,裸片具有接脚,接脚面对粘合剂层表面;于粘合剂层和裸片远离支撑晶片层的一侧形成预固化层,预固化层覆盖裸片;于预固化层远离支撑晶片层的一侧形成固化层;去除支撑晶片层和粘合剂层,暴露出裸片的接脚;于暴露出裸片的接脚的一侧表面形成重布线层,并于重布线层上形成球形接脚;打磨固化层至预定厚度;切割,形成扇出型晶圆级封装结构;其中,固化层与预固化层具有不同的热膨胀系数,且固化层与裸片具有相同的热膨胀系数。该方法生产的封装结构减小了在扇出型晶圆级封装工艺中晶圆的翘曲。
Description
技术领域
本发明涉及半导体芯片封装领域,具体而言,涉及一种扇出型晶圆级封装结构及其制造方法。
背景技术
在动态随机存储存储器(DRAM,Dynamic Random Access Memory)制备工艺的发展过程中,相关技术中用窗口球形矩阵排列(WBGA,Windows-Ball Grid Array)方式对DRAM封装结构100(如图1A所示)进行封装,包括裸片101,塑封层102以及接脚103。对于开口110,裸片101上的焊垫位置的设计有严格要求,并且需要与基板厂的制造能力相互匹配。另外,采用WBGA方式的DRAM封装结构需要通过基板传输信号,DRAM封装结构的厚度以及基板中的金属布线线都有严格要求。
相关技术中的扇出型晶圆级封装结构(如图1B所示),包括裸片101',塑封层102'以及球形接脚103'。由于,塑封层与裸片的热膨胀系数差异较大,导致在形成塑封层之后,结构整体易产生翘曲,加大了形成重布线层以及球形接脚工艺的难度。
需要说明的是,在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解,因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
有鉴于上述问题,本发明提供一种扇出型晶圆级封装结构及其制造方法,进而在一定程度上解决基板设计的瓶颈以及扇出型晶圆级封装结构的翘曲问题。
本发明提供一种扇出型晶圆级封装结构的制造方法,包括:提供支撑晶片层,于支撑晶片层上形成粘合剂层;将多个裸片粘合至粘合剂层表面,裸片具有接脚,接脚面对粘合剂层表面;于粘合剂层和裸片远离支撑晶片层的一侧形成预固化层,预固化层覆盖裸片;于预固化层远离支撑晶片层的一侧形成固化层;去除支撑晶片层和粘合剂层,暴露出裸片的接脚;于暴露出裸片的接脚的一侧表面形成重布线层,并于重布线层上形成球形接脚;打磨固化层至预定厚度;切割,形成扇出型晶圆级封装结构;其中,固化层与预固化层具有不同的热膨胀系数,且固化层与裸片具有相同的热膨胀系数。
在本发明的一些实施例中,形成预固化层的步骤包括:在100~120℃下,将预固化层贴覆至粘合剂层和裸片远离支撑晶片层的一侧,贴覆时间是1min;贴覆之后,在100~120℃下,预固化0.5~1.5h。
在本发明的一些实施例中,于预固化层远离支撑晶片层的一侧形成固化层的温度在150~200℃之间,时间是1~3h。
在本发明的一些实施例中,预固化层的厚度是200~250μm,固化层的预定厚度是200~400μm。
在本发明的一些实施例中,预固化层是环氧塑封料,固化层是硅晶片。
应用上述制造方法,本发明还提供一种扇出型晶圆级封装结构,包括:裸片、预固化层、重布线层、多个球形接脚以及固化层。裸片具有接脚;预固化层覆盖并包覆裸片,并且裸片的接脚一侧暴露出预固化层表面;重布线层形成于裸片的接脚暴露出的一侧,重布线层包括钝化层和金属层;多个球形接脚形成于重布线层上,球形接脚通过金属层与裸片的接脚电连接;固化层形成于预固化层远离重布线层的一侧,覆盖预固化层;其中固化层与预固化层具有不同的热膨胀系数,且固化层与裸片具有相同的热膨胀系数。
在本发明的一些实施例中,预固化层是环氧塑封料,固化层是硅晶片。
在本发明的一些实施例中,预固化层的厚度是200~250μm。
在本发明的一些实施例中,固化层的厚度是200~400μm。
在本发明的一些实施例中,裸片是动态随机存储存储器。
本发明的有益效果在于,该封装方法利用扇出型晶圆级封装技术进行重布线,在重布线开口上进行植球工艺,取代传统封装中的基板设计,贴片,布线等制程,能够提高封装结构传输性能,以及减少封装结构尺寸,规避了传统WBGA封装方式中基板设计的瓶颈。并且,本发明的方法通过在预固化层上多施加一层固化层,减小了在扇出型晶圆级封装工艺中,特别是在形成重布线层和焊球接脚的过程中晶圆的翘曲,减小了后续工艺难度,同时也减小了切割后的封装结构的翘曲,有利于后续的再封装工艺。
附图说明
图1A为现有技术的WBGA方式的DRAM封装结构的示意图。
图1B为现有技术中常规的扇出型晶圆级封装结构的示意图。
图1C为现有技术中常规的扇出型晶圆级封装结构发生翘曲的情况示意图。
图2A-图2I为本发明的扇出型晶圆级封装结构在制造方法的各个步骤中的状态示意图。
图3为应用本发明的扇出型晶圆级封装结构的制造方法制成的扇出型晶圆级封装结构。
图4为本发明的扇出型晶圆级封装结构的制造方法的一个实施例的流程示意图。
具体实施方式
以下是通过特定的具体实例来说明本发明所公开有关“扇出型晶圆级封装结构的制造方法”及“扇出型晶圆级封装结构”的实施方式,本领域技术人员可由本说明书所公开的内容了解本发明的优点与效果。本发明可通过其他不同的具体实施例加以施行或应用,本说明书中的各项细节也可基于不同观点与应用,在不悖离本发明的构思下进行各种修改与变更。以下的实施方式将进一步详细说明本发明的相关技术内容,但所公开的内容并非用以限制本发明的保护范围。
本发明提供一种扇出型晶圆级封装结构的制造方法。参见图2A-图2I以及图4。图2A-图2I为本发明的扇出型晶圆级封装结构在制造方法的各个步骤中的状态示意图。制造方法在一待加工元件200上进行。具体步骤如下:
步骤S101.提供支撑晶片层,在支撑晶片层上形成粘合剂层。
如图2A所示的,提供一支撑晶片层207,在支撑晶片层207的一侧表面上涂敷粘合剂,以形成粘合剂层208。粘合剂层208要完全覆盖支撑晶片层207表面。然后做好对位标记,按裸片规格,间隔相同的预定距离设置多个对位标记。支撑晶片层207可以选择为透明玻璃或硅晶片,支撑晶片层207上具有切口标记,粘合剂层208可以为硅胶,本领域技术人员可根据实际需要选择合适的材质。
步骤102.将多个裸片粘合至粘合剂层表面。
如图2B所示的,将预先切割好的多个单颗裸片201粘合至粘合剂层208表面,根据先前的对位标记将各裸片201粘接至指定位置形成预定的排布。裸片具有接脚,接脚面对粘合剂层表面。裸片201间的间隔距离为80~120μm,例如裸片201间的间隔距离为90μm、100μm或110μm。本公开对此不做具体限制。
步骤S103.于粘合剂层和裸片远离支撑晶片层的一侧形成预固化层。
如图2C所示,将环氧塑封料(EMC)层通过粘合剂层粘合至支撑晶片层表面,形成一预固化层202。预固化层202覆盖先前粘接好的多个单颗裸片201。具体的,预固化步骤S103在一真空操作室内进行,首先将EMC层通过粘合剂层208贴覆至支撑晶片层207表面,覆盖并包覆先前粘接好的多个单颗裸片201。EMC层贴覆在100~120℃条件下,1min内完成。之后保持100~120℃的条件下,预固化0.5~1.5h,即完成环氧塑封料的预固化。在本公开的一实施方式中,EMC层在110℃贴覆完成,然后在110℃下,预固化1h。预固化后的环氧塑封料呈一固态胶体的形态。预固化层厚度可以为200~250μm,例如,预固化层厚度可以为210μm、220μm、230μm或240μm。本领域技术人员可根据实际需要选择合适的厚度,本公开对此不做限制。预固化过程中可通过自下向上观察,即从支撑晶片层207向预固化层202方向观察,裸片201与形成预固化层并包覆裸片201的EMC之间没有气泡存在,即可认为预固化步骤完成。
步骤S104.于预固化层远离支撑晶片层的一侧形成固化层。
如图2D所示,在预固化层202远离支撑晶片层207的一侧面形成固化层204,固化层204完全覆盖预固化层202,然后进行固化。在一些优选实施例中,选用硅晶片作为固化层202。本领域技术人员也可根据实际需要,选择其他的材料作为固化层。固化步骤S104在在上述真空操作室内进行,将固化层204贴覆至预固化层202表面,完全覆盖预固化层202,在150~200℃条件下,维持约1~3h,即完成固化。例如,在180℃条件下,固化2h。固化层厚度可以为750~850μm,例如固化层厚度可以为800μm。本领域技术人员可根据实际需要选择合适的厚度。由于预固化步骤中的EMC中还存有部分未完全挥发的挥发物,因此固化层如硅晶片附着上时可形成粘接。待挥发物完全挥发后即完全固化成型。在预固化层的表面形成固化层,因固化层和裸片的热膨胀系数相同,这样减小了整片晶圆的翘曲,减小了后续形成重布线层和球形接脚的工艺难度。
步骤S105.去除支撑晶片层和粘合剂层。如图2E所示的,去除支撑晶片层207以及粘合剂层208,使得预固化层202中排布好的裸片201的接脚2011暴露出来。之后,对暴露出来的裸片201进行清洗,确保裸片201的接脚2011表面没有粘合剂层残留。
步骤S106.于暴露出裸片的接脚的一侧表面形成重布线层。
如图2F所示的,在预固化层202暴露出裸片接脚2011的一侧表面沉积第一钝化层,接着通过光刻、显影和蚀刻方法形成凹槽,凹槽暴露出裸片接脚2011,然后在凹槽内沉积金属,形成金属层,最后在金属层表面及第一钝化层表面沉积第二钝化层,最终形成重布线层205。重布线层包括第一钝化层、第二钝化层和金属层。沉积第一钝化层和第二钝化层的方法可以为化学气相沉积或原子层沉积。钝化层的材料可以为聚酰亚胺(polyimide)。沉积金属层的方法可以为物理气相沉积或电镀。金属层的材料可以为铜、铝、钨等中的一种或上述材料的合金材料。本公开对此不做限制。
在本公开的一实施方式中,第一钝化层和第二钝化层的厚度在5~10μm,例如,可以为6μm、7μm、8μm或9μm。第一钝化层和第二钝化层的厚度可以相同或不同。金属层的厚度在3~5μm之间,例如,可以为4μm。本公开对此不做限制。
步骤S107.于重布线层上形成球形接脚。
如图2G所示的,将锡球焊接至重布线层205表面,与暴露出的裸片接脚2011接通,形成球形接脚203。在本公开的一实施方式中,植球方式可以从使用植球器、模板、刷焊膏或手工贴装的方法中根据实际需要进行选择。
S108.打磨固化层至预定厚度。
如图2H所示的,采用机械抛光的方法,将固化层远离球形接脚的一侧面进行打磨,使固化层204打磨至预定厚度,以符合封装规格。打磨后的固化层的厚度在200~400μm之间,例如,固化层的厚度可以为250μm、300μm或350μm,本领域技术人员可根据实际需要,选择合适的厚度。本公开对此不做限制。
S109.切割,形成扇出型晶圆级封装结构。
如图2I所示的,对打磨好的待加工元件200进行测量、标记,之后按照标记进行切割,如图2I中箭头位置。将待加工元件200应用激光或金刚石切割的方式切割成如图3所示的包含单个裸片的扇出型晶圆级封装结构300。本领域技术人员也可根据实际需要,选择其他的切割方式。扇出型晶圆级封装结构300包括单个裸片301、预固化层302、裸片接脚303、固化层304、重布线层305。
在一些实施例中,该制造方法用于制造动态随机存储存储器的封装结构,即,裸片201/301为动态随机存储存储器。
以上所述的流程中,为了进行后续步骤,并保证扇出型晶圆级封装结构的电性能,需要在去支撑步骤S105后对去除粘合剂层和支撑裸片层后的裸片表面进行清洗。通常在去支撑步骤S105后,钝化布线步骤S106之前,进行清洗步骤。采用清洗剂将粘合剂层和支撑晶片层在预固化层表面的残留物去除,使裸片暴露出的部分保持清洁,以保证电性能。例如,清洗方法可以为水洗,清洁剂选择为水。
以上为本发明的扇出型晶圆级封装结构的制造方法,该方法利用扇出型晶圆级封装技术,取代传统封装中的基板设计、贴片等制程,能够提高扇出型晶圆级封装结构传输性能,以及减少扇出型晶圆级封装结构尺寸,规避了传统WBGA封装方式中基板设计的瓶颈。并且,本发明的方法通过在预固化层上多施加一层固化层,减小了在扇出式晶片级封装工艺中,特别是在形成重布线层和焊球接脚的过程中晶圆的翘曲,减小了后续工艺难度,同时也减小了切割后的扇出型晶圆级封装结构的翘曲,有利于后续的再封装工艺。
应用本发明的制造方法,本发明还提供一种扇出式扇出型晶圆级封装结构,参见图3。如图3所示的,扇出型晶圆级封装结构300包括:裸片301,预固化层302,重布线层305,球形接脚303以及固化层304。重布线层305包括钝化层和金属层。预固化层302一般为环氧塑封料,预固化层302覆盖并包覆裸片301,并且裸片301的接脚一侧暴露出预固化层302的表面。重布线层305形成于预固化层302上裸片301的接脚暴露出的一侧,与裸片301的接脚接通。多个球形接脚303形成于重布线层305上。固化层304形成于预固化层远离重布线层的一侧,并完全覆盖预固化层302。固化层304与预固化层302具有不同的热膨胀系数,固化层304与裸片301具有相同的热膨胀系数。
该扇出型晶圆级封装结构与传统的WBGA封装的封装结构主要区别在于,在EMC层(本公开中预固化层)上施加了与EMC热膨胀系数不同且与裸片热膨胀系数相同的固化层。EMC层先行预固化,待贴合固化层后再进行二次固化。由于双层固化的原因,封装工艺与传统扇出型晶圆级封装工艺也不同。首先裸片201/301的排布是通过粘接在一施加有粘合剂层208的支撑晶片层207表面上实现。之后将EMC通过粘合剂层208贴覆至支撑晶片层207表面,覆盖并包覆先前粘接好的多个单颗裸片201/301,在设定的温度压力条件下进行一段时间,完成预固化。预固化后的EMC呈一固态胶体的形态。预固化完成后将固化层204贴覆至预固化层202表面,完全覆盖预固化层202,在设定的温度压力条件下进行一段时间,完成固化。并在固化后,去除支撑晶片层以及粘合剂层,再进行铺设重布线层以及植球、打磨、切割等后续步骤。
在一些优选实施例中,选用硅晶片作为固化层304。本领域技术人员也可以根据实际需要,选择其他的材料作为固化层。固化层304的厚度优选为200~400μm。预固化层302的厚度优选为200~250μm。本领域技术人员可根据实际需要选择相应的厚度,以符合封装标准。
在一些实施例中,上述扇出型晶圆级封装结构为动态随机存储存储器的封装结构,即,裸片301为动态随机存储存储器。
此种扇出型晶圆级封装结构的有益效果在于,取代传统封装中的基板设计、贴片等制程,能够提高封装结构传输性能,以及减少封装结构尺寸,规避了传统WBGA封装方式中基板设计的瓶颈。并且,本发明的封装结构通过在预固化层上多施加一层固化层,减小了在扇出型晶圆级封装工艺中,特别是在形成重布线层和焊球接脚的过程中晶圆的翘曲,减小了后续工艺难度,同时也减小了切割后的封装结构的翘曲,有利于后续的再封装工艺。
以上为本发明所提供的扇出型晶圆级封装结构及其制造方法的一些实施例,通过实施例的说明,相信本领域技术人员能够了解本发明的技术方案及其运作原理。然而以上仅为本发明的优选实施例,并非对本发明加以限制。本领域技术人员可根据实际需求对本发明所提供技术方案进行适当修改,所做修改及等效变换均不脱离本发明所要求保护的范围。本发明所要求保护的权利范围,当以所附的权利要求书为准。
Claims (10)
1.一种扇出型晶圆级封装结构的制造方法,其特征在于,包括:
提供支撑晶片层,于所述支撑晶片层上形成粘合剂层;
将多个裸片粘合至所述粘合剂层表面,所述裸片具有接脚,所述接脚面对所述粘合剂层表面;
于所述粘合剂层和所述裸片远离所述支撑晶片层的一侧形成预固化层,所述预固化层覆盖所述裸片;
于所述预固化层远离所述支撑晶片层的一侧形成固化层;
去除所述支撑晶片层和所述粘合剂层,暴露出所述裸片的所述接脚;
于暴露出所述裸片的所述接脚的一侧表面形成重布线层,并于所述重布线层上形成球形接脚;
打磨所述固化层至预定厚度;
切割,形成所述扇出型晶圆级封装结构;
其中,所述固化层与所述预固化层具有不同的热膨胀系数,且所述固化层与所述裸片具有相同的热膨胀系数。
2.根据权利要求1所述的扇出型晶圆级封装结构的制造方法,其特征在于,形成所述预固化层的步骤包括:
在100~120℃下,将所述预固化层贴覆至所述粘合剂层和所述裸片远离所述支撑晶片层的一侧,贴覆时间是1min;
贴覆之后,在100~120℃下,预固化0.5~1.5h。
3.根据权利要求1所述的扇出型晶圆级封装结构的制造方法,其特征在于,于预固化层远离所述支撑晶片层的一侧形成固化层的温度在150~200℃之间,时间是1~3h。
4.根据权利要求1所述的扇出型晶圆级封装结构的制造方法,其特征在于,所述预固化层的厚度是200~250μm,所述固化层的所述预定厚度是200~400μm。
5.根据权利要求1所述的扇出型晶圆级封装结构的制造方法,其特征在于,所述预固化层是环氧塑封料,所述固化层是硅晶片。
6.一种扇出型晶圆级封装结构,其特征在于,包括:
裸片,所述裸片具有接脚;
预固化层,所述预固化层覆盖并包覆所述裸片,并且所述裸片的所述接脚一侧暴露出所述预固化层表面;
重布线层,所述重布线层形成于所述裸片的接脚暴露出的一侧,所述重布线层包括第一钝化层、第二钝化层和金属层;
多个球形接脚,形成于所述重布线层上,所述球形接脚通过所述金属层与所述裸片的所述接脚电连接;以及
固化层,所述固化层形成于预固化层远离所述重布线层的一侧,所述固化层覆盖所述预固化层;
所述固化层与所述预固化层具有不同的热膨胀系数,且所述固化层与所述裸片具有相同的热膨胀系数。
7.根据权利要求6所述的扇出型晶圆级封装结构,其特征在于,所述预固化层是环氧塑封料,所述固化层是硅晶片。
8.根据权利要求6所述的扇出型晶圆级封装结构,其特征在于,所述预固化层的厚度是200~250μm。
9.根据权利要求6所述的扇出型晶圆级封装结构,其特征在于,所述固化层的厚度是200~400μm。
10.根据权利要求6所述的扇出型晶圆级封装结构,其特征在于,所述裸片是动态随机存储存储器。
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