CN111259613B - Layout method of electronic device and integrated circuit - Google Patents

Abstract

The invention provides an electronic device and a layout method of an integrated circuit. The layout method of the integrated circuit comprises the following steps: receiving layout information, analyzing the layout information and obtaining a plurality of blank areas in the integrated circuit; presetting a plurality of virtual blocks, wherein the virtual blocks have different sizes; selecting at least one of the virtual blocks according to the size of each blank area so as to perform filling action on the central position of each blank area and generate updated layout information; performing a layout density check on the updated layout information to obtain a check result; and reducing the size of a plurality of set virtual blocks in the integrated circuit according to the checking result, and generating output layout information.

Description

Layout method of electronic device and integrated circuit

technical field

The present invention relates to an electronic device and an implemented integrated circuit layout method, in particular to an electronic device that can easily adjust the layout density and the implemented layout method.

Background technique

In the layout of integrated circuits, layout engineers tend to layout circuits with a relatively high density in order to maximize chip utilization. After completing the layout of the main circuit, the layout engineer will perform a filling operation of the virtual block for the blank area in the integrated circuit. After all blank areas are filled with virtual blocks, the integrated circuit may fail to meet design/layout specification requirements due to too high layout density. In such a situation, layout engineers can only manually adjust each blank area to meet the requirements of the design/layout specification.

The above-mentioned layout adjustment method requires a lot of manpower, and the manual adjustment action of the layout engineer may not be in place at one time, and often requires repeated adjustment actions to meet the requirements of the design/layout specification, wasting time and manpower.

Contents of the invention

The invention provides an electronic device and a layout method of the implemented integrated circuit, which can easily adjust the layout density.

The integrated circuit layout method of the present invention includes: receiving layout information, analyzing the layout information and obtaining multiple blank areas in the integrated circuit; preset multiple virtual blocks, the virtual blocks have different sizes; according to the size of each blank area , select at least one of the virtual blocks to fill in the center positions of each blank area, and generate updated layout information; perform a layout density check on the updated layout information to obtain a check result; and, according to the check result to reduce the size of a plurality of set virtual blocks in the integrated circuit and generate output layout information.

The electronic device of the present invention is used for performing the layout operation of the integrated circuit. The electronic device includes a memory and a processor. The memory is used for storing layout information and preset layout information of a plurality of virtual blocks, wherein the virtual blocks have different sizes. The processor is used to: receive layout information, analyze the layout information and obtain a plurality of blank areas in the integrated circuit; select at least one of the virtual blocks according to the size of each blank area, so as to fill in the center positions of each blank area Action, and generate updated layout information; perform layout density check on the updated layout information to obtain check results; reduce the size of a plurality of set virtual blocks in the integrated circuit according to the check results, and generate output layout information.

Based on the above, the present invention automatically adjusts the layout density of the integrated circuit by filling the blank areas of the integrated circuit with virtual blocks of different sizes and adjusting the size of the set virtual blocks. In this way, the adjustment of the layout density of the integrated circuit can be completed in an automated manner, eliminating the trouble of manual adjustment, and enabling the layout density of the integrated circuit to be set more precisely.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

Fig. 1 shows the flowchart of the layout method of the integrated circuit of an embodiment of the present invention;

2A to 2C show schematic diagrams of multiple virtual blocks according to an embodiment of the present invention;

3A and 3B are schematic diagrams showing a step of a layout method according to an embodiment of the present invention;

Fig. 4 shows a schematic diagram of another step of the layout method of the embodiment of the present invention;

5 and 6 are schematic diagrams of another step of the layout method of the embodiment of the present invention;

FIG. 7 shows a flowchart of a layout method according to another embodiment of the present invention;

FIG. 8 shows a schematic diagram of an electronic device according to an embodiment of the present invention.

Explanation of reference signs

S110～S150, S810～S850: Layout steps of integrated circuits

100: integrated circuit

110～190, 1100, 1110, 1120: blank area

DA1: Block of First Density

DA2: Second Density Block

210, 220, 230: virtual blocks

BA1: blank area

DA31～DA33: Third Density Block

DB1, DB2, DB12, DB13, DB1A, DB1B, DB1C: virtual block

DB1A’, DB1D’: replace virtual blocks

900: Electronics

910: Processor

920: memory

IGDS: layout information

DBN: virtual block

Detailed ways

Referring to FIG. 1 , step S110 receives layout information, and obtains a plurality of blank areas in the integrated circuit by analyzing the layout information. Here, the layout information may be related information in a Graphic Database System (GDSII) format, which is used to record the plane geometry of the integrated circuit layout, text labels, and related information about structural composition. Regarding the analysis details of the blank area, the first random blank area in the integrated circuit (as shown in FIG. 3A ) can be obtained according to the layout information, and the first rectangle with the largest area in the first random blank area can be found. Next, the first rectangle is removed from the first cluttered blank area to be updated to obtain a second cluttered blank area, and then a second rectangle with the largest area is found from the second cluttered blank area. By repeatedly executing the above steps until the area of the N+1th rectangle with the largest area is smaller than the predetermined target, the analysis of the blank area can be completed. Wherein the aforementioned first to Nth rectangles are blank areas.

Please refer to FIG. 1 and FIG. 3B at the same time below. FIG. 3B is the result of analyzing the layout information. In FIG. 3B , a plurality of blank areas 110 - 190 , 1100 , 1110 , and 1120 in integrated circuit 100 are identified. The identified blank areas 110˜190, 1100, 1110, and 1120 may be framed in the form of a rectangle. The blank areas 110˜190, 1100, 1110, and 1120 may have the same or different sizes.

Next, in step S120, a plurality of virtual block preset actions are performed. Please refer to FIG. 1 and FIG. 2A to FIG. 2C synchronously. In FIG. . The first density block DA1 may be formed by active area components of an integrated circuit. In this embodiment, in addition to the block DA1 of the first density, the virtual block 210 may include a blank area BA1 of a certain size.

In FIG. 2B , the virtual block 220 includes a first density block DA1 , a second density block DA2 and a blank area BA1 . The second density block DA2 is disposed around the first density block DA1 and surrounds the first density block DA1. It is worth mentioning that the size of the virtual block 220 is larger than that of the virtual block 210 . The second density block DA2 can be formed by, for example, a polysilicon layer in an integrated circuit.

In FIG. 2C , the virtual block 230 includes a first density block DA1 , a second density block DA2 , a plurality of third density blocks DA31 - DA33 and a blank area BA1 . The second density block DA2 is disposed on the edge of the first density block DA1. The blocks DA31 - DA33 of the third density are inserted into the block DA2 of the second density. The first density block DA1 and the third density blocks DA31 - DA33 may have the same layout density, and may be formed by active area components of an integrated circuit. The second density block DA2 can be formed by, for example, a polysilicon layer in an integrated circuit. In some embodiments of the present invention, the virtual block 230 may not have the second density block DA2, or may not have the third density blocks DA31˜DA33. In addition, in the case that the virtual block 230 includes the third density blocks DA31˜DA33, the number of the third density blocks DA31˜DA33 can be one, two or more than three. The third density shown in FIG. 2C The number of blocks DA31 - DA33 (3) is just an example for illustration, and is not intended to limit the scope of the present invention. It is worth mentioning that the size of the virtual block 230 is larger than that of the virtual block 220 , and the size of the virtual block 220 is larger than that of the virtual block 210 .

In this embodiment, the virtual block 210 , the virtual block 220 and the virtual block 230 have different layout densities.

Next, please refer to FIG. 1 again. In step S130, according to the size of each blank area in the integrated circuit, at least one of the virtual blocks is selected to fill in the center positions of each blank area, and generate Updated layout information. Please refer to FIG. 1 and FIG. 4 simultaneously. In FIG. 4 , taking the blank area 140 as an example, the blank area 140 is filled with a plurality of virtual blocks DB1 of the same size. Taking the blank area 110 as an example, the blank area 110 is filled with a plurality of virtual blocks DB1 and a plurality of virtual blocks DB2, wherein the sizes of the virtual blocks DB1 and the virtual blocks DB2 are different.

Please note here that regarding the filling action of the virtual block, in the embodiment of the present invention, multiple frames can be respectively established according to multiple preset virtual blocks, wherein the frames can be based on the respective corresponding virtual blocks. edge to build. Moreover, when filling the virtual block into the blank area, the frame corresponding to the selected virtual block can be filled into the blank area.

Regarding the details of the filling action of the virtual block, N accommodating quantities can be calculated according to the size of each blank area and the size of a first frame, and N first frames are filled in each blank area, where N is An integer not less than 0. In detail, first calculate the long side and short side dimensions in the blank area of the rectangle, and calculate the accommodated quantity (=X) of the first frame on the long side and the accommodated quantity of the first frame on the short side ( =Y), and thereby determine the largest number of first frames (X*Y=N), and fill in the largest number of frames in the rectangular blank area. Next, each blank area can generate one or more sub-blank areas, and the embodiment of the present invention can calculate M accommodating quantities according to the size of the sub-blank areas and the size of a second frame. Then M second frames with smaller sizes are sequentially filled in the sub-blank areas.

By repeatedly performing the filling operation above for each blank area in the integrated circuit, each blank area in the integrated circuit can be filled with a dummy block to complete step S130 and generate updated layout data.

Please refer to FIG. 1 again. In step S140, the layout density check is performed on the updated layout data. If the check result indicates that the layout density of the integrated circuit is higher than a preset critical value, then step S150 is executed to determine the layout density according to the check result. Reducing the size of a plurality of set virtual blocks in the integrated circuit and generating output layout information.

Regarding the implementation details of step S150, please refer to FIG. 1, FIG. 5 and FIG. Among them, one of the plurality of adjacent virtual blocks is a set virtual block. In FIG. 5 , one of the two adjacent virtual blocks is set as the set virtual block. For example, in the integrated circuit 100 , taking the blank area 140 as an example, the virtual block DB1A and the virtual block DB1B are adjacent in the horizontal direction. Therefore, the virtual block DB1A can be set as a set virtual block, and the set virtual block DB1B can be set as a non-set virtual block. In addition, the virtual block DB1A and the virtual block DB1C are adjacent in the vertical direction, and the virtual block DB1A has been set as a set virtual block, therefore, the virtual block DB1C can be set as a non-set virtual area piece. By analogy, the virtual block DB1D can be set as the set virtual block.

The above critical value can be obtained from the design specification and/or layout specification provided by the integrated circuit production factory.

In FIG. 5 , virtual blocks represented by dotted frames are set virtual blocks, while virtual blocks represented by solid frames are non-configured virtual blocks. In the actual setting details, the setting operation of the graphics data system (GDS) number can be performed for the set virtual block and the non-set virtual block respectively. Wherein, the GDS number of all configured virtual blocks can be 1, and the GDS number of all non-configured virtual blocks can be 0, so as to identify the type of virtual block.

Incidentally, the setting method of setting the virtual block can also be set by making one or two of the adjacent three virtual blocks a set virtual block, or making the adjacent four virtual blocks One, two or three of the blocks are set virtual blocks, and there is no special limitation.

Incidentally, regarding the above-mentioned actions of setting virtual blocks and non-setting virtual blocks, in other embodiments of the present invention, it may be performed for the frame corresponding to the virtual blocks. Wherein, when only relevant information of frames is filled in the blank area, one of the multiple adjacent frames can be set as a set frame, and the other can be set as a non-set frame. Correspondingly, the above-mentioned setting operation of the graphic data system number can be performed for the set frame and the non-set frame.

Next, in FIG. 6, the size reduction operation of setting the virtual block is performed. Wherein, in the integrated circuit 100, taking the blank area 140 as an example, the positions of the originally set virtual blocks DB1A and DB1D are replaced with relatively small-sized replaced virtual blocks DB1A' and DB1D', instead of non-set virtual blocks. Blocks DB1B and DB1C remain unchanged. In this embodiment, the virtual blocks DB1A' and DB1D' can be replaced by the virtual block 220 in FIG. 2B , and the virtual blocks DB1B and DB1C can be the virtual block 230 in FIG. 2C .

By performing block replacement by setting the virtual blocks DB1B and DB1C, the positions of the originally configured virtual blocks DB1B and DB1C can have more blank areas, and therefore, the layout density of the integrated circuit 100 can be automatically adjusted. drop.

Incidentally, if the filling operation for the blank area is performed through the frame corresponding to the virtual block, when the replacement operation for the virtual block is performed, the replacement can be performed for the corresponding frame.

After the step S150 is completed, the output layout information meeting the specification requirements can be effectively generated.

Incidentally, after the step of generating the output layout information is completed, the layout density distribution information of the integrated circuit can be generated according to the output layout information. The layout density distribution information can be presented in the form of data, and through data analysis, it can be provided to layout engineers and/or design engineers for analysis.

Also, the output layout information is information that can conform to specifications. Thus, output layout information can be provided to fabricate photomasks and physical integrated circuits produced by semiconductor fabrication plants.

It is not difficult to know from the above description that the layout method of the embodiment of the present invention can adjust the layout density of the integrated circuit in an automatic way to make it conform to the specification. In this way, the trouble of manual adjustment can be avoided, and the adjustment of the layout density can be completed quickly and accurately.

Referring to FIG. 7 below, FIG. 7 shows a flowchart of a layout method according to another embodiment of the present invention. Wherein, step S810 identifies blank areas in the integrated circuit, and then, step S820 performs a virtual block filling operation according to the center positions of each blank area. Step S820 can first fill in the blank area according to the frame of the virtual block, and after step S820 is completed, then execute step S830 to make the frame of the virtual block and its corresponding layout information perform a mapping operation, so that the virtual area The actual layout content of the block fills in the empty space. After completing the mapping operations of the frame and layout information of all the virtual blocks, the updated layout information can be generated (step S840 ).

Step S850 may perform a layout density check, and check whether the layout density of the integrated circuit is too high, and if the layout density of the integrated circuit is too high, perform step S860 to replace the virtual block. The layout density of the integrated circuit can be effectively reduced by replacing the dummy block with a relatively high density with a replacement dummy block with a relatively low density. After repeating the layout density checking operations, and when the layout density of the integrated circuit meets the specification, the layout operation of this embodiment ends.

The details of the above steps have been described in detail in the foregoing embodiments, and will not be repeated here.

Please refer to FIG. 8 below. FIG. 8 is a schematic diagram of an electronic device according to an embodiment of the present invention. The electronic device 900 includes a processor 910 and a memory 920 . The processor 910 and the memory 920 are coupled to each other. The memory 920 is used for storing the layout information IGDS and information of a plurality of preset virtual blocks DBN, wherein the virtual blocks DBN have different sizes. The processor 910 receives the layout information IGDS and the information of the virtual block DBN from the memory 920, and executes the layout methods as in the above-mentioned multiple embodiments, thereby adjusting the layout density of the integrated circuit.

Multiple implementation details of the layout method have been described in detail in the foregoing embodiments, and will not be repeated here.

To sum up, the present invention presets a plurality of virtual blocks, and makes the virtual blocks fill in according to the central position of the blank area, and then adjusts the layout density of the integrated circuit by replacing the virtual blocks. In this way, the stop operation of the layout density of the integrated circuit does not need to be performed manually, but can be performed automatically, thereby improving the efficiency of the layout work.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall prevail as defined by the claims.

Claims (12)

1. A layout method of an integrated circuit, comprising:

receiving layout information, analyzing the layout information and obtaining a plurality of blank areas in the integrated circuit;

presetting a plurality of virtual blocks, wherein the plurality of virtual blocks have different sizes;

selecting at least one of the plurality of virtual blocks according to the size of each blank area so as to perform filling action on the central position of each blank area and generate updated layout information;

performing a layout density check on the updated layout information to obtain a check result; and

reducing the size of a plurality of set virtual blocks in the integrated circuit according to the checking result and generating output layout information, comprising:

setting at least one of the adjacent virtual blocks in the plurality of virtual blocks in the integrated circuit as a set virtual block; when the inspection result indicates that the layout density of the integrated circuit is higher than a critical value, each of the plurality of set virtual blocks is replaced by a replacement virtual block,

the density of the replaced virtual blocks is smaller than that of the corresponding multiple set virtual blocks.

2. The layout method according to claim 1, wherein the step of selecting at least one of the plurality of virtual blocks to fill in the center position of each of the blank areas according to the size of each of the blank areas comprises:

generating a plurality of frames according to the edges of the virtual blocks; and

selecting at least one of the virtual blocks, and enabling the frame corresponding to the selected virtual block to perform filling action on the central position of each blank area.

3. The layout method according to claim 2, wherein the step of selecting at least one of the plurality of virtual blocks to perform the filling action on the center position of each of the blank areas according to the size of each of the blank areas further comprises:

and calculating N receivable numbers according to the size of each blank area and the size of the first frame, and filling N first frames into each blank area, wherein N is an integer not less than 0.

4. The layout method according to claim 3, wherein after the N first frames are filled into each of the blank areas, generating at least one sub-blank area, selecting at least one of the plurality of virtual blocks according to the size of each of the blank areas, so as to perform the filling action on the center position of each of the blank areas further comprises:

and calculating M receivable numbers according to the sizes of the sub-blank areas and the sizes of the second frames, and filling M second frames into the sub-blank areas, wherein M is an integer not smaller than 0.

5. The layout method of claim 4, wherein the first frame has a size that is larger than a size of the second frame.

6. The layout method of claim 4, wherein the step of reducing the size of the plurality of set virtual blocks in the integrated circuit according to the inspection result comprises:

the plurality of setting frames corresponding to the plurality of setting virtual blocks are replaced by a plurality of second frames respectively,

wherein the size of each of the set frames is larger than the size of each of the second frames.

7. The layout method according to claim 1, wherein the output layout information is provided as information for manufacturing the integrated circuit.

8. The layout method of claim 1, further comprising:

generating layout density distribution information of the integrated circuit according to the output layout information.

9. The layout method of claim 1, wherein each of the dummy blocks comprises a first density block.

10. The layout method of claim 9, wherein each of the dummy blocks further comprises a second density block, wherein the second density block is disposed at an edge of the first density block.

11. The layout method of claim 10, wherein each of the dummy blocks further comprises at least one third density block disposed in the second density block, the at least one third density block having the same density as the first density block.

12. An electronic device for performing layout actions of an integrated circuit, comprising:

the memory is used for storing layout information and information of a plurality of preset virtual blocks, wherein the plurality of virtual blocks have different sizes; and

a processor for:

receiving the layout information, analyzing the layout information and obtaining a plurality of blank areas in the integrated circuit;

selecting at least one of the plurality of virtual blocks according to the size of each blank area so as to perform filling action on the central position of each blank area and generate updated layout information;

performing a layout density check on the updated layout information to obtain a check result; and

reducing the size of a plurality of set virtual blocks in the integrated circuit according to the checking result and generating output layout information, comprising:

setting at least one of the adjacent virtual blocks in the plurality of virtual blocks in the integrated circuit as a set virtual block; when the inspection result indicates that the layout density of the integrated circuit is higher than a critical value, each of the plurality of set virtual blocks is replaced by a replacement virtual block,

the density of the replaced virtual blocks is smaller than that of the corresponding multiple set virtual blocks.