CN111199697B - Display device and display method for reducing dynamic blurring - Google Patents

Abstract

A display device and display method for reducing dynamic blur, the display device includes: the device comprises a liquid crystal display panel, a driving module, a backlight module and a processing module. The processing module receives the input display data to generate output display data, so that the output display data has an output picture data section and a redundant output picture data section for data transmission with an output pixel clock higher than the input pixel clock within a picture time of the same length as the input display data, and drives the liquid crystal display panel to generate a display picture according to the output display data. The processing module controls the backlight module to be started only in the redundant output picture data interval, and the liquid crystal display panel is started after the liquid crystal display panel responds to the output picture data corresponding to the output picture data interval.

Description

Display device and display method for reducing motion blur

technical field

The present invention relates to display technology, and in particular to a display device and display method for reducing motion blur.

Background technique

A common liquid crystal display is implemented as a hold-type display, and the screen is updated every 16.67 milliseconds (millisecond) at 60 updates per second (60 Hz). The currently displayed picture is static until a new picture is updated. However, when the user's eyes track the object in the picture, they will have an expected position according to the moving speed of the object. However, due to the discontinuity of the update time of the liquid crystal display, there will be some errors between the actual position of the object on the screen and the expected position of the user's brain. The persistence of vision and motion compensation mechanism of the human eye will allow the brain to continue the process of tracking objects with a similar integration effect, resulting in motion blur.

Therefore, how to design a new display device and display method for reducing motion blur to solve the above deficiency is an urgent problem to be solved in the industry.

Contents of the invention

The object of the present invention is to provide a display device for reducing motion blur, comprising: a liquid crystal display panel, a driving module, a backlight module and a processing module. The driving module is electrically coupled to the liquid crystal display panel. The backlight module is configured to generate backlight to the liquid crystal display panel. The processing module is electrically coupled to the backlight module and the driving module, and configured to receive input display data, wherein the input display data corresponds to the frame time between two adjacent input vertical sync signals (Vsync) signals, There is an input frame data interval for data transmission at an input pixel clock and an input blank interval after the input image data interval. The processing module is configured to generate output display data according to the input display data, so that the output display data has an output frame data interval for data transmission with an output pixel clock greater than the input pixel clock within the same length of frame time and in the The redundant output image data interval after the output image data interval is used to drive the liquid crystal display panel through the driving module to generate a display image according to the output display data. The processing module is further configured to control the backlight module to turn on only in the redundant output image data interval, after the liquid crystal display panel responds the output image data corresponding to the output image data interval.

Another object of the present invention is to provide a display method for reducing motion blur, which is applied to a display device. The display device includes a liquid crystal display panel, a driving module electrically coupled to the liquid crystal display panel, and configured to generate backlight to the liquid crystal display. The backlight module of the panel and the processing module electrically coupled to the backlight module and the driving module, the display method includes: making the processing module receive input display data, wherein the input display data corresponds to the interval between two adjacent input vertical synchronization signals In the screen time, there is an input screen data interval for data transmission with the input pixel clock and an input blank interval after the input screen data interval; the processing module generates output display data according to the input display data, so that the output display data is in In the frame time of the same length, there is an output frame data interval for data transmission with an output pixel clock greater than the input pixel clock and a redundant output frame data interval after the output frame data interval; the processing module can display data according to the output Drive the liquid crystal display panel to generate display images through the driving module; and enable the processing module to control the backlight module to turn on only in the redundant output image data interval, after the liquid crystal display panel responds to the output image data corresponding to the output image data interval.

The advantage of applying the present invention is that the display device can transmit the picture data to the liquid crystal display panel in a shorter time through the driving module by increasing the output pixel clock, so that the display unit has enough response time before turning on the backlight module, solving the problem of For the problem of insufficient response time of the liquid crystal display panel, the improvement range of reducing motion blur achieves a relatively consistent effect in the vertical direction.

Description of drawings

FIG. 1 is a block diagram of a display device for reducing motion blur in an embodiment of the present invention;

FIG. 2 is a timing diagram of inputting display data and outputting display data in an embodiment of the present invention;

FIG. 3 is a timing diagram of inputting display data and outputting display data in another embodiment of the present invention;

FIG. 4 is a flow chart of a display method for reducing motion blur in an embodiment of the present invention;

FIG. 5A is a schematic diagram of a backlight module in an embodiment of the present invention;

5B is a schematic diagram of a liquid crystal display panel in an embodiment of the present invention;

FIG. 5C is a timing diagram of inputting display data, outputting display data, and backlight module switch in an embodiment of the present invention; and

FIG. 6 is a flow chart of a display method for reducing motion blur in an embodiment of the present invention.

【Symbol Description】

1: display device

100: LCD display panel

101: Backlight

102: Drive module

103: Enter display data

104: Backlight module

105: Output display data

106: Processing Modules

108: storage unit

200, 300, 500: input screen data range

201: Part One

202, 302, 502: Enter a blank interval

203: Part Two

204, 304, 504A to 504D: output screen data interval

206, 506: output blank interval

306: Redundant output screen data interval

208, 308: Interval

400: display method

401 to 404: Steps

600: display method

601 to 602: Steps

BZ1 to BZ4: backlight component range

PZ1 to PZ4: Panel area

TD: preset time

TFI, TFO: Time to Frame

Vsync_in: input vertical synchronization signal

Vsync_out: output vertical synchronization signal

Detailed ways

Please also refer to Figure 1. FIG. 1 is a block diagram of a display device 1 for reducing motion blur in an embodiment of the present invention. The display device 1 includes: a liquid crystal display panel 100 , a driving module 102 , a backlight module 104 and a processing module 106 .

In one embodiment, the liquid crystal display panel 100 includes a plurality of display units (not shown) arranged in an array.

The driving module 102 is electrically coupled to the liquid crystal display panel 100 . In one embodiment, the driving module 102 includes a gate driver and a source driver (not shown). The gate driver is connected to the gates of transistors in a row of display units of the liquid crystal display panel, and is responsible for switching each row of transistors, and turns on a whole row of transistors at a time during scanning. When the transistor is turned on, the source driver can transmit the control voltage for controlling brightness, grayscale, and color to the pixels of the display unit through the channel formed by the source and drain of the transistor.

The backlight module 104 is configured to generate a backlight 101 to the liquid crystal display panel 100 to illuminate the panel so that the user can view the display images displayed on the liquid crystal display panel 100 .

In one embodiment, the processing module 106 is a scaler or a timing controller, but the invention is not limited thereto. The processing module 106 is electrically coupled to the backlight module 104 and the driving module 102 and configured to receive the input display data 103 and generate the output display data 105 according to the input display data 103 . The processing module 106 can drive the liquid crystal display panel 100 to generate a display image through the driving module 102 according to the output display data 105 . Further, the processing module 106 can output the display data 105 to control the backlight module 104 to generate the backlight 101 to illuminate the liquid crystal display panel 100, so as to provide display images for users to watch.

The following will describe in more detail the generation mechanism of the processing module 106 for the output display data 105 and the control mechanism of the backlight module 104 .

Please refer to Figure 2. FIG. 2 is a timing diagram of inputting display data 103 and outputting display data 105 in an embodiment of the present invention.

As shown in FIG. 2 , the input display data 103 has a plurality of input vertical synchronous signals Vsync_in, and every two adjacent input vertical synchronous signals Vsync_in will correspond to include data of a display frame.

Among them, the input display data 103 has an input frame data interval 200 for data transmission with an input pixel clock and an input frame data interval 200 after the input frame data interval 200 within the frame time TFI between two adjacent input vertical synchronous signals Vsync_in. The input blank interval 202 of .

In one embodiment, the input image data interval 200 is used to transmit actual image data, while the input blank interval 202 does not transmit image data. In one embodiment, the input frame data interval 200 transmits frame data with the input pixel clock. Taking the amount of picture data in the horizontal and vertical directions as 2000×1127 (the picture size is 1920×1080) and the picture update rate of 90 Hz as an example, the input pixel clock will be 2000×1127×90=202.86 MHz. The length of the input blank interval 202 is about 0.46 milliseconds.

Similarly, the output display data 105 has a plurality of output vertical synchronous signals Vsync_out, and every two adjacent output vertical synchronous signals Vsync_out will correspond to include data of a display frame. In this embodiment, the time length of the frame time TFO between two adjacent output vertical synchronization signals Vsync_out is the same as the time length of the frame time TFI.

Wherein, the output display data 105 has an output frame data interval 204 for data transmission at an output pixel clock greater than the input pixel clock and an output blank interval 206 after the output frame data interval 204 within the frame time TFO.

Similarly, the output image data interval 204 is used to transmit actual image data, while the output blank interval 206 does not transmit image data. Since the output pixel clock is greater than the input pixel clock, the output frame data interval 204 can transmit the amount of frame data corresponding to the input frame data interval 200 in a shorter time. Correspondingly, the output blanking interval 206 will thus be longer than the input blanking interval 202 .

Taking the output pixel clock rate increased to 596.88 MHz as an example, when the picture update rate is maintained at the same 90 Hz, the amount of picture data that can be transmitted in the horizontal and vertical directions is 2000×3316 (2000×3316×90=596.88 MHz) . However, since the frame size is still 1920×1080, the output frame data interval 204 can be greatly reduced to about 1/3 of the input frame data interval 200 . In contrast, the length of the output blank interval 206 can be extended to about 7.49 milliseconds.

In one embodiment, in order not to lose the frame data, the frame time TFO in the output display data 105 is delayed by a preset time TD from the corresponding frame time TFI in the input display data 103 . In other words, the output vertical synchronous signal Vsync_out corresponding to each frame time TFO is delayed by the predetermined time TD from the input vertical synchronous signal Vsync_in corresponding to the frame time TFI.

At this time, the input screen data corresponding to the input screen data interval 200 includes a first part 201 and a second part 203 . The processing module 106 can temporarily store the first part 201 through the included storage unit 108, so as to access the storage unit 108 to output the first part 201 and directly output the second part 203 in the output picture data interval 204 as the output picture data .

Therefore, the processing module 106 is further configured to control the backlight module 104 to turn on only in the output blank interval 206 after the liquid crystal display panel 100 has reflected the output image data corresponding to the output image data interval 204 . In FIG. 2 , the time when the backlight module 104 is turned on is represented by interval 208 .

In more detail, by turning off the backlight module 104, the display device 1 can achieve the effect of inserting black images between the display images, that is, the backlight inserts black, so that the duration of the images viewed by human eyes is reduced, thereby reducing dynamics. blur effect. However, since the liquid crystal reaction speed of the liquid crystal display panel 100 is not fast enough, it takes 4-6 milliseconds or more than 10 milliseconds to fully respond. If the timing of turning on the backlight module 104 is too early, the response time of the display unit on the liquid crystal display panel 100 that is updated according to the image data is likely to be insufficient, resulting in different effects of improving motion blur in the vertical direction.

Therefore, the display device 1 of the present invention can transmit image data to the liquid crystal display panel 100 through the driving module 102 in a shorter time by increasing the output pixel clock, so that the display unit has sufficient response time. The backlight module 104 can be turned on in the interval 208 after the liquid crystal display panel 100 finishes responding the output image data corresponding to the output image data interval 204 , so as to solve the problem of insufficient response time of the liquid crystal display panel 100 .

It should be noted that the preset delay time TD and the size of the first part 201 to be stored by the storage unit 108 can be determined according to the relationship between the output pixel clock and the input pixel clock and the response time of the liquid crystal display panel 100. Decide. Moreover, the backlight 101 generated by the backlight module 104 may be a strobe backlight, and the backlight module 104 determines the brightness of its illumination according to the length of time it is turned on. For example, when the backlight module 104 is turned on for a short time, the brightness of the illumination can be increased to prevent the brightness of the liquid crystal display panel 100 from being too dark.

Please refer to Figure 3. FIG. 3 is a timing diagram of inputting display data 103 and outputting display data 105 in another embodiment of the present invention.

As shown in FIG. 3 , the input display data 103 has a plurality of input vertical synchronous signals Vsync_in, and every two adjacent input vertical synchronous signals Vsync_in will correspond to include data of a display frame.

The input display data 103 has an input frame data interval 300 transmitted at the input pixel clock and an input blank interval 302 after the input frame data interval 300 within the frame time TFI between two adjacent input vertical synchronous signals Vsync_in.

In one embodiment, the input image data interval 300 is used to transmit actual image data, while the input blank interval 302 does not transmit image data.

Similarly, the output display material 105 has a plurality of output vertical synchronization signals Vsync_out. In this embodiment, the output display data 105 is equally divided into two sub-frame times by three output vertical synchronization signals Vsync_out in the frame time TFO having the same length as the frame time TFI. Wherein, the first sub-picture time is the output picture data period 304 , and the second sub-picture time is the redundant output picture data period 306 . In another embodiment, the frame time for outputting display data is equally divided into N−1 sub-frame times by N output vertical synchronization signals Vsync_out, wherein N is an integer greater than 3, but the present invention is not limited thereto. In addition, the output picture data interval 304 corresponds to the first sub-picture time, and the redundant output picture data period 306 corresponds to at least one sub-picture time after the first sub-picture time.

In one embodiment, in order not to lose the frame data, the frame time TFO in the output display data 105 is delayed by a preset time TD from the corresponding frame time TFI in the input display data 103 . In other words, the output vertical sync signal Vsync_out corresponding to both ends of each frame time TFO is delayed by the preset time TD compared to the input vertical sync signal Vsync_in corresponding to the frame time TFI.

At this time, the input screen data section 300 corresponds to the input screen data. The processing module 106 can temporarily store all the input image data through the included storage unit 108, so that in the output image data interval 304, by partially accessing the storage unit 108 and partially directly outputting, it can be larger than the input pixel time The output pixel clock pulse of the pulse is transmitted, and the input picture data is output as the output picture data. Further, the processing module 106 accesses the storage unit 108 in the redundant output frame data interval 306, transmits again with the output pixel clock greater than the input pixel clock, and outputs the input frame data as the redundant output frame data.

Therefore, the processing module 106 is further configured to control the backlight module 104 to turn on only in the redundant output image data interval 306 after the liquid crystal display panel 100 has reflected the output image data corresponding to the output image data interval 304 . In FIG. 3 , the time when the backlight module 104 is turned on is represented by interval 308 .

In more detail, by turning off the backlight module 104 , the display device 1 can achieve the effect of inserting black frames between the display frames, reducing the dwell time of the frames viewed by human eyes, thereby reducing the effect of motion blur. However, since the liquid crystal reaction speed of the liquid crystal display panel 100 is not fast enough, it takes 4-6 milliseconds or more than 10 milliseconds to fully respond. If the timing of turning on the backlight module 104 is too early, the response time of the display unit on the liquid crystal display panel 100 that is updated later according to the image data is likely to be insufficient, resulting in different effects of motion blur improvement.

Therefore, the display device 1 of the present invention can transmit the picture data to the liquid crystal display panel 100 in a shorter time through the driving module 102 by increasing the output pixel clock, and make the output display data 105 by repeating playing pictures. The frame update rate is actually 2 times the frame refresh rate of the input display data 103 or an integer multiple greater than 2, but has the same equivalent frame refresh rate. Due to the repetitive picture content, the display unit will have sufficient reaction time. The backlight module 104 can be turned on in the interval 308 after the liquid crystal display panel 100 finishes responding the output image data corresponding to the output image data interval 304, that is, the backlight is turned on only after the last repeated image, so as to solve the problem of the liquid crystal display panel. 100 problems with insufficient reaction time.

It should be noted that, the preset delay time TD mentioned above can be determined according to the relationship between the output pixel clock and the input pixel clock and the response time of the liquid crystal display panel 100 . Moreover, the above-mentioned implementation mode is an example of playing the output picture data at 2 times. In other embodiments, when the output pixel clock is more times higher than the input pixel clock, the output picture data can also be achieved at a higher magnification. function for playback.

Please refer to Figure 4. FIG. 4 is a flowchart of a display method 400 for reducing motion blur in an embodiment of the present invention. The display method 400 can be applied to the display device 1 in FIG. 1 . The display method 400 includes the following steps (it should be understood that the steps mentioned in this embodiment, unless the order is specifically stated, can be adjusted according to actual needs, and can even be executed simultaneously or partially simultaneously).

In step 401, the processing module 106 is made to receive the input display data 103, wherein the input display data 103 corresponds to the frame time TFI between two adjacent input vertical synchronous signals Vsync_in, and has an input frame data interval 200 transmitted with the input pixel clock. And the input blank interval 202 after the input screen data interval 200 .

In step 402, make the processing module 106 generate the output display data 105 according to the input display data 103, so that the output display data 105 has an output transmitted with an output pixel clock greater than the input pixel clock within the same length of frame time TFO The screen data interval and the output blank interval 206 or the redundant output screen data interval 306 after the output screen data interval.

In one embodiment, the processing module 106 can use the method shown in FIG. 2 to generate the output frame data interval 204 and the output blank interval 206 without sending the image data after the output frame data interval 204 . In another embodiment, the processing module 106 can use the method shown in FIG. 3 to generate the output image data interval 304 and after outputting the image data interval 304, transmit the redundant output image data interval 306 of the redundant image data. .

In step 403 , the processing module 106 drives the liquid crystal display panel 100 to generate a display image through the driving module 102 according to the output display data 105 .

In step 404, the processing module 106 is made to control the backlight module 104 only in the output blank interval 206 or the redundant output image data interval 306, and the liquid crystal display panel 100 has finished responding to the output image data interval (the output image data interval 204 or the output image data interval in FIG. 2 ). The output screen data corresponding to the output screen data interval 304) in FIG. 3 is turned on.

Please refer to FIG. 5A , FIG. 5B and FIG. 5C at the same time. FIG. 5A is a schematic diagram of the backlight module 104 in an embodiment of the present invention. FIG. 5B is a schematic diagram of the liquid crystal display panel 100 in an embodiment of the present invention. FIG. 5C is a timing diagram of input display data 103 , output display data 105 , and switching of the backlight module 104 in an embodiment of the present invention.

As shown in FIG. 5A and FIG. 5B , the backlight module 104 is divided into a plurality of backlight component zones BZ1, BZ2, BZ3 and BZ4, and the liquid crystal display panel 100 can be divided into panel zones PZ1, PZ2, PZ3 and PZ4. Wherein, the backlight assembly may be a light emitting diode (LED) or a cold cathode fluorescent lamp (CCFL), so as to be divided into a plurality of backlight assembly sections BZ1, BZ2, BZ3 and BZ4, the present invention is not limited thereto. In one embodiment, the size of the liquid crystal display panel 100 is substantially the same as that of the backlight module 104 , and the backlight component zones BZ1 , BZ2 , BZ3 and BZ4 respectively generate backlight to the corresponding panel zones PZ1 , PZ2 , PZ3 and PZ4 .

As shown in FIG. 5C , the input display data 103 has a plurality of input vertical synchronous signals Vsync_in, and every two adjacent input vertical synchronous signals Vsync_in will correspond to include data of a display frame.

Among them, the input display data 103 has an input frame data interval 500 transmitted with the input pixel clock within the frame time TFI between two adjacent input vertical synchronous signals Vsync_in, and an input blank interval 502 after the input frame data interval 500 .

In one embodiment, the input frame data section 500 is used to transmit actual frame data. And the input blank space 502 does not transmit the picture data.

Similarly, the output display data 105 has a plurality of output frame data intervals 504A, 504B, 504C and 504D transmitted with the output pixel clock within the frame time TFO between two adjacent output vertical synchronous signals Vsync_out, and in the output frame Input blank interval 506 after data intervals 504A to 504D.

In this embodiment, the output pixel clock is equal to the input pixel clock, and there is no delay between the frame time TFO of the output display data 105 and the corresponding frame time TFI of the input display data 103 . Therefore, the total time length of the output frame data intervals 504A to 504D is actually the same as the input frame data interval 500 . Wherein, the output picture data sections 504A to 504D sequentially transmit the input picture data corresponding to one of the panel areas PZ1 , PZ2 , PZ3 and PZ4 respectively. And the input blank space 502 does not transmit the picture data.

The processing module 106 is configured to control the backlight component sections BZ1, BZ2, BZ3, and BZ4 to turn on after the corresponding panel areas PZ1, PZ2, PZ3, and PZ4 respond to the output image data, so as to generate backlight to the panel areas PZ1, PZ2, PZ3, and PZ4.

In FIG. 5C , the time sequence of turning on the backlight assembly zones BZ1 , BZ2 , BZ3 and BZ4 of the backlight module 104 is shown. In this embodiment, the backlight component zone BZ1 is turned on at a time corresponding to the output image data zone 504D to illuminate the panel zone PZ1.

Therefore, relative to the panel area PZ1, the display units in this area have a response time equivalent to the length of the frame data intervals 504B and 504C. When the consecutive backlight assembly sections BZ2 to BZ3 are turned on to illuminate the panel areas PZ2 to PZ3 , the display units in these areas will also have the same length of response time.

In one embodiment, the turn-on time of the backlight unit sections BZ1, BZ2, BZ3, and BZ4 is equivalent to the time of outputting image data sections 504A to 504D, so that each panel area PZ2 to PZ3 can have an average response time and brightness.

Therefore, the display device 1 of the present invention can control the turn-on time of the backlight module 104 in different areas without changing the pixel clock and frame update rate of the output display data 105 relative to the input display data 103, so that the display unit It will have the effect of sufficient response time, and solve the problem of insufficient response time of the liquid crystal display panel 100 .

Please refer to Figure 6. FIG. 6 is a flowchart of a display method 600 for reducing motion blur in an embodiment of the present invention. The display method 600 can be applied to the display device 1 shown in FIG. 1 and FIG. 5A , FIG. 5B , and FIG. 5C . The display method 600 includes the following steps (it should be understood that the steps mentioned in this embodiment, unless the order is specifically stated, can be adjusted according to actual needs, and can even be executed simultaneously or partially simultaneously).

In step 601, the processing module 106 receives the input display data 103 to generate the output display data 105, and drives the liquid crystal display panel 100 through the driving module 102 to generate a display image according to the output display data 105, wherein the output display data 105 corresponds to adjacent In the frame time TFO between the two output vertical synchronous signals Vsync_out, there are a plurality of output frame data intervals 504A to 504D, and the output frame data corresponding to one of the panel regions are sequentially transmitted respectively.

In step 602, the processing module 106 controls the backlight component sections BZ1, BZ2, BZ3, and BZ4 to turn on after the corresponding panel areas PZ1, PZ2, PZ3, and PZ4 have finished responding to the output image data, so as to generate backlight to the panel areas PZ1, PZ2 , PZ3 and PZ4.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements within the principles of the present invention shall be included within the protection scope of the present invention.

Claims (8)

1. A display device for reducing motion blur, comprising: a liquid crystal display panel; a driving module, electrically coupled to the liquid crystal display panel; a backlight module configured to generate a backlight to the liquid crystal display panel; and A processing module, electrically coupled to the backlight module and the driving module, and configured to receive an input display data, wherein the input display data corresponds to two adjacent input vertical sync signals (Vsync) signals In a frame time between, there is an input frame data interval transmitted with an input pixel clock (pixelclock) and an input blank interval after the input image data interval; Wherein the processing module is configured to generate an output display data according to the input display data, so that the output display data has an output pixel clock that is greater than the input pixel clock during the frame time of the same length. Outputting the image data interval and a redundant output image data interval after the output image data interval, and driving the liquid crystal display panel through the drive module to generate a display image according to the output display data; The processing module is further configured to control the backlight module to turn on only in the redundant output image data interval, after the liquid crystal display panel responds to an output image data corresponding to the output image data interval, Wherein the picture time of the output display data is divided into N-1 sub-picture times by N output vertical synchronization signals, and the output picture data interval corresponds to the first sub-picture time, and the redundant output picture data interval corresponding to at least one of the sub-picture times after the first of the sub-picture times; Wherein the input screen data interval corresponds to an input screen data, and the processing module further includes a storage unit configured to temporarily store the input screen data so as to output the input screen data in the output screen data interval as the output screen data , and access the storage unit at each sub-picture time after the first sub-picture time to output the input picture data again as a redundant output picture data. 2. The display device according to claim 1, wherein the frame time of the output display data is delayed by a preset time compared with the frame time corresponding to the input display data. 3 . The display device according to claim 2 , wherein a frame refresh rate of the output display data is 2 times or an integral multiple greater than 2 of the frame refresh rate of the input display data. 4 . 4. The display device according to claim 1, wherein the processing module is a scaler or a timing controller. 5. A display method for reducing motion blur, applied in a display device, the display device comprising a liquid crystal display panel, a driving module electrically coupled to the liquid crystal display panel, configured to generate a backlight to the liquid crystal A backlight module of the display panel, and a processing module electrically coupled to the backlight module and the driving module, the display method includes: The processing module is made to receive an input display data, wherein the input display data corresponds to a frame time between two adjacent input vertical synchronous signals, has an input frame data interval transmitted with an input pixel clock and the input An input blank interval after the screen data interval; causing the processing module to generate an output display data according to the input display data, so that the output display data has an output frame transmitted with an output pixel clock greater than the input pixel clock within the same length of the frame time a data interval and a redundant output image data interval following the output image data interval; make the processing module drive the liquid crystal display panel to generate a display image through the driving module according to the output display data; and The processing module controls the backlight module to turn on only in the output blank interval, and the liquid crystal display panel responds to an output image data corresponding to the output image data interval, Wherein the picture time of the output display data is divided into N-1 sub-picture times by N output vertical synchronization signals, and the output picture data interval corresponds to the first sub-picture time, and the redundant output picture data interval Corresponding to at least one sub-picture time after the first sub-picture time, wherein the input picture data interval corresponds to an input picture data, the display method further includes: causing a storage unit included in the processing module to temporarily store the input screen data; outputting the input frame data in the output frame data interval as the output frame data; and The storage unit is accessed at each sub-picture time after the first sub-picture time to output the input picture data again as a redundant output picture data. 6. The display method according to claim 5, wherein the frame time of the output display data is delayed by a preset time compared with the frame time corresponding to the input display data. 7. The display method according to claim 5, wherein a frame update rate of the output display data is 2 times or an integral multiple greater than 2 of the frame update rate of the input display data. 8. The display method according to claim 5, wherein the processing module is a scaler or a timing controller.

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